Abstract: When U-shape formed electronic components having an axial lead shape are mounted upright on a printed board, two U-shape formed electronic components having an axial lead shape are arranged so as not to be in the same straight line, and a wiring pattern is formed in a state where bent-side lead wires have the same electric potential, and the electronic components are inclined so as to place the bent-side lead wires close to each other, whereby the electronic components that tend to fall in the inclined direction can be mutually supported by the bent-side lead wires. Thus, the electronic components can be prevented from falling without spoiling a heat dissipation performance of the electronic component and the board, and without greatly deteriorating an assembly performance of the board.

Abstract: A method is provided for producing a laminated substrate for mounting semiconductor chips. At least respective metal and plastic structure films having respective different recurrent contours are laminated together in such a way that a material strip is obtained. The lamination is followed by perforations or cuttings, and the method includes at least one of the following steps: A. the films are structured in such a way that superposition thereof makes it possible to obtain the areas which are devoid of overlap through the total width thereof; B. the films are not laminated through the total width of the laminate in partly recurrent areas; and C. recurrent segments of the recurrent contours are bent out of the surface of the laminated strip starting from the laminate.

Abstract: A method and a system for improving reliability of a semiconductor device are provided. In one embodiment, a semiconductor device is provided comprising a semiconductor chip, a metallization layer comprising a metallic material disposed over a surface of the semiconductor chip, and an alloy layer comprising the metallic material disposed over the metallization layer.

Abstract: At least one microspring has applied thereover a laminate structure to provide: mechanical protection during handling and wafer processing, a spring spacer layer, strengthening of the anchor between spring and substrate, provision of a gap stop during spring deflection, and moisture and contaminant protection. A fully-formed laminate structure may be applied over the microspring structure or a partly-formed laminate structure may be applied over the microspring structure then cured or hardened. The tip portion of the microspring may protrude through the laminate structure and be exposed for contact or may be buried within the contact structure. The laminate structure may remain in place in the final microspring structure or be removed in whole or in part. The laminate structure may be photolithographically patternable material, patterned and etched to remove some or all of the structure, forming for example additional structural elements such as a gap stop for the microspring.

Abstract: A semiconductor device comprises a semiconductor element having electrodes, a metal member, wires that electrically connect the semiconductor element and the metal member and/or electrodes within the semiconductor element, wherein the wires constitute at least a first wire loop and a second wire loop, the first wire loop is bonded at one end to a first bonding point and at the other end to a second bonding point, and has a flat part which includes the surface of a boll part and the wire located contiguously the ball part surface, and the second wire loop connects the surface of the ball part and a third bonding point.

Abstract: A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region.

Abstract: A device including a semiconductor chip and metal foils. One embodiment provides a device including a semiconductor chip having a first electrode on a first face and a second electrode on a second face opposite to the first face. A first metal foil is attached to the first electrode of the semiconductor chip in an electrically conductive manner. A second metal foil is attached to the second electrode of the semiconductor chip in an electrically conductive manner.

Abstract: Disclosed herein is a lead pin for a package substrate. The lead pin for the package substrate according to the exemplary embodiment of the present invention includes a head part having one surface opposite to the package substrate and the other surface that is an opposite side to the one surface; and a connection pin having a pin shape bonded to the other surface of the head part, wherein the head part has a concave depression part toward the package substrate.

Abstract: A component includes a first semiconductor chip attached to a first carrier and second semiconductor chip attached to a second carrier. The first carrier has a first extension, which forms a first external contact element. The second carrier has a second extension, which forms a second external contact element. The first and the second carriers are arranged in such a way that the first and the second extension point in different directions.

Abstract: An apparatus comprises an integrated circuit die including a main body having a top layer, a bottom layer, and a peripheral edge surface extending between the top layer and the bottom layer. The integrated circuit die also includes a bond pad on the main body, an edge contact at the peripheral edge surface and a line connecting the bond pad to the edge contact. The edge contact includes a bottom surface that substantially in the same plane as a surface of an encapsulant encasing the die. Additional apparatus, systems, and methods are disclosed.

Abstract: Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an external interconnect; forming a first planar terminal adjacent to the external interconnect and non-planar to a portion the external interconnect; mounting a first integrated circuit over the first planar terminal; connecting the first integrated circuit with the external interconnect; and forming an encapsulation over the first planar terminal covering the first integrated circuit and with the external interconnect extending from a non-horizontal side of the encapsulation and with the first planar terminal coplanar with the adjacent portion of the encapsulation exposing the first planar terminal.

Abstract: A device includes a semiconductor die having a surface, a plurality of proximity connectors proximate to the surface, and a circuit coupled to at least one of the plurality of proximity connectors. The semiconductor die is configured to communicate voltage-mode signals through capacitive coupling using one or more of the plurality of proximity connectors. The circuit also includes a filter with a capacitive-summing junction to equalize the signals.

Abstract: A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe having a lead, a first quad flat nonleaded package (QFN) connected to the lead, and a second quad flat nonleaded package invertly connected to a top surface of the first quad flat nonleaded package, wherein the second quad flat nonleaded package is wirebonded to the lead. A third embodiment of a semiconductor package includes a leadframe having a lead with a first level downset lead extension, a quad flat nonleaded package (QFN) connected to the first level downset lead extension, and a first wirebondable die attached to a top or bottom surface of the quad flat nonleaded package.

Abstract: An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken.

Abstract: High density circuit modules are formed by stacking integrated circuit (IC) chips one above another. Unused input/output (I/O) locations on some of the chips can be used to connect other I/O locations, resulting in decreased impedance between the chips. Additional apparatus, systems, and methods are disclosed.

Abstract: An integrated circuit includes a substrate; a sealing element spanning a periphery of the substrate that forms a protective boundary for the substrate; a plurality of copper lines spanning the substrate in at least two distinct layers contained within the protective boundary; a first conducting element disposed outside the sealing element; and one or more second conducting elements connecting at least two of the copper lines and that spans the sealing element; wherein the conducting elements are substantially non-oxidizing metals that are resistant to oxidization and that connect the copper line to the first conducting element.

Abstract: A chip unit includes: a first semiconductor chip and a second semiconductor chip disposed such that their surfaces for forming first bonding pads and second bonding pads face each other; first and second connection members disposed on the surfaces of the first and second semiconductor chips for forming the first and second bonding pads, and having redistribution lines which have one ends connected with the first and second bonding pads and the other ends projecting beyond one edges of the first and second semiconductor chips and films; an adhesive member interposed between the first connection members and the second connection members; and via patterns passing through the adhesive member and connecting projecting portions of the redistribution lines of the first and second connection members with each other.

Abstract: Semiconductor packages that contain isolated, stacked dies and methods for making such devices are described. The semiconductor package contains both a first die with a first integrated circuit and a second die with a second integrated circuit that is stacked onto the first die while also being isolated from the first die. The first and second dies are connected using an array of metal connectors containing both a base segment and a beam segment extending over the first die and supporting the second die. This configuration can provide a thinner semiconductor package since wire-bonding is not used. As well, since the integrated circuit devices in the first and second dies are isolated from each other, local heating and/or hot spots are diminished or prevented in the semiconductor package. Other embodiments are also described.

Abstract: A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source areas and a metalized gate area, a patterned source connection having a plurality of dimples formed thereon coupling the source lead to the semiconductor die metalized source areas, a patterned gate connection having a dimple formed thereon coupling the gate lead to the semiconductor die metalized gate area, a semiconductor die drain area coupled to the drain lead, and an encapsulant covering at least a portion of the semiconductor die and drain, source and gate leads.

Abstract: A semiconductor package with isolated inner lead(s) is revealed. A chip is disposed on a leadframe segment and encapsulated by an encapsulant. The leadframe segment includes a plurality of leads, an isolated lead, and an external lead where each lead has an internal portion and an external portion. The isolated inner lead is completely formed inside the encapsulant and the external lead is partially formed inside and extended outside the encapsulant. At least one of the internal portions of the leads is located between the isolated inner lead and the external lead. Two fingers are formed at two opposing ends of the isolated inner lead without covering by the chip. One of the fingers imitates a plurality of fingers of the leads to arrange along a first side of the chip. The other finger of the isolated inner lead and a finger of the external lead are arranged along a second side of the chip.

Abstract: A method of manufacturing a semiconductor package is provided, which can improve the quality of plating through reduction of plating deviation, and improve molding and soldering efficiencies in forming a molding compound and packaging the semiconductor package onto a printed circuit board.

Abstract: A semiconductor device that can cope with larger numbers of pins and finer pitches while suppressing lowering of the manufacturing yield and reliability includes: a semiconductor chip having a plurality of electrodes provided on an upper surface thereof; a plurality of lead terminals including inner lead portions disposed toward the semiconductor chip; a sheet-form wiring member having a plurality of conductors insulated from one another on one main surface thereof; and a sealing-resin layer for sealing at least the semiconductor chip, the inner lead portions and the wiring member. The electrodes of the semiconductor device and the inner lead portions of the lead terminals are electrically connected respectively to each other via the conductors of the wiring member.

Abstract: All lead terminals 21 to 24 formed on a first side of a first radiator plate 31 are set as terminals D which are connected to one of the main electrodes of a power semiconductor chip 11 through which a switching current flows. A lead terminal 25 formed on a second side of the first radiator plate 31 is set as a terminal S connected to the other one of the main electrodes of the power semiconductor chip 11. A lead terminal 28 formed on the second side of the first radiator plate 31 is set as a terminal FB to which a control signal of a control IC chip 12 is input. Lead terminals 26 and 27 formed between the lead terminals 25 and 28 are set as a terminal Vcc and a terminal GND, respectively.

Abstract: A power semiconductor chip (first semiconductor chip) 41 is mounted on the main surface of a first radiator plate 31, and a control IC chip (second semiconductor chip) 42 is mounted on the main surface of a second radiator plate 32. The first radiator plate 31 has an extending portion 31A extending toward the side on which the second radiator plate 32 is provided in the arrangement direction of first lead terminals (lead terminals 21 to 24). The first lead terminals (lead terminals 21 to 24) are connected to a first side of the first radiator plate 31 to function as extraction electrodes of a rear side electrode (D: drain electrode) of the power semiconductor chip 41. A second lead terminal (lead terminal 25) is connected to a bonding pad 411 serving as a source electrode (S). The third lead terminals (lead terminals 26 to 28) are connected to an electrode of the control IC chip 42.

Abstract: An interconnection structure suitable for use as an IC package, probe head or other electrical termination of high density where uninterrupted controlled impedance is desired is described.

Abstract: A functional block for assembly includes at least one element and a patterned magnetic film comprising at least one magnetic region attached to the element. A wafer includes a host substrate comprising a number of elements. The wafer further includes a patterned magnetic film attached to the elements and comprising a number of magnetic regions. The magnetic regions are attached to respective ones of the elements. A method of manufacture includes forming a number of magnetic regions on a host substrate having an array of elements. The forming step provides at least one of the magnetic regions for a respective group comprising at least one of the elements.

Abstract: One aspect of the invention relates to a power semiconductor device in lead frame technology and a method for producing the same. The power semiconductor device has a vertical current path through a power semiconductor chip. The power semiconductor chip has at least one large-area electrode on its top side and a large-area electrode on its rear side. The rear side electrode is surface-mounted on a lead frame chip island of a lead frame and the top side electrode is electrically connected to an internal lead of the lead frame via a connecting element. The connecting element has an electrically conductive film on a surface facing the top side electrode, the electrically conductive film extending from the top side electrode to the internal lead.

Abstract: According to one embodiment, a power transistor package includes an electrically conductive flange configured to be connected to a source of a power transistor device. The package further includes a first terminal mechanically fastened to the flange and configured to be electrically connected to a gate of the power transistor device and a second terminal mechanically fastened to the flange and configured to be electrically connected to a drain of the power transistor device. The package also includes a bus bar mechanically fastened to the flange which extends between and connects at least two different DC bias terminals mechanically fastened to the flange. The bus bar is configured to be electrically connected to the drain via one or more RF grounded connections.

Abstract: Packaging is substantially entirely removed from an integrated circuit die. The method allows the batch processing of several integrated circuit dies, such that packaging is removed from each die approximately simultaneously.

Abstract: An electrostatic capacitance-type input device includes: a first translucent conductive film that configures a first electrode that extends in a first direction in an input area on a substrate and second electrodes that extend in a second direction intersecting the first direction in the input area and are disconnected in intersection portions with the first electrode; an interlayer insulating film that is formed at least in areas overlapping the intersection portions; and a second translucent conductive film that configures relay electrodes formed on the interlayer insulating film to have sheet resistance lower than that of the first translucent conductive film and electrically connecting the second electrodes disconnected in the intersection portion by being electrically connected to the second electrodes in an area in which the interlayer insulating film is not formed and a peripheral wiring extending in a peripheral area of the substrate located to the outer side of the input area.

Abstract: A semiconductor device such as a field-effect transistor, improved to reduce device resistance, comprises a leadframe which includes a die paddle integral with a first set of leads and a second set of leads that is electrically isolated from the first set, a semiconductor die having its lower surface positioned on, and electrically connected to, the die paddle, and a conductive layer on the upper surface of the die. At least one electrically conductive wire, preferably plural wires, extend laterally across the second surface of the semiconductor die, are in electrical contact with the conductive layer, and interconnect corresponding second leads on opposite sides of the die. The plural wires may be welded to leads in succession by alternate ball and wedge bonds on each lead. The conductive layer may be an aluminized layer on which is formed a thin layer a solderable material, such as tin. A solder is deposited on the tin layer, enmeshing the wires.

Abstract: The semiconductor device comprises a support plate; a semiconductor element; and conductor posts consisting of a conductor having a first end at one end and a second end at the other end, the second end being connected to the semiconductor element and the conductor posts being connected to the support plate at a position on the side of the second end that is closer to the first end, wherein the conductor posts have a heat conductivity of approximately 200 W/m·K or higher and a Vickers hardness of approximately 70 or lower.

Abstract: A tape wiring substrate may have dispersion wiring patterns. The dispersion wiring patterns may be provided between input/output wiring pattern groups to compensate for the intervals therebetween. Connecting wiring patterns may be configured to connect the dispersion wiring patterns to a first end of the adjacent input/output wiring pattern.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead to include a first tip at one end, a second tip on the end opposite from the first tip with a connect area between each end located above the first tip, and a first tier section or a second tier section located between the connect area and the second tip; connecting a bottom component assembly to the first tier section or the second tier section; connecting a top component assembly over the connect area; and applying an encapsulant over and under the connect area with the first tip exposed.

Abstract: A semiconductor device (7) has gold coatings (1 to 5) which are applied to metallic or ceramic components (6) of the semiconductor device (7). The gold coatings (1 to 4) have a multifunctional multilayer metal coating (8) with a minimal gold layer (9). The gold layer has a thickness dG where dG?0.5 ?m. Moreover, at least one metallic interlayer (10) is arranged between the gold layer (9) and the metallic or ceramic components (6).

Abstract: The present invention proposes a semiconductor device including a semiconductor chip having a plurality of electrodes, a plurality of leads electrically connected to the plurality of electrodes of the semiconductor chip by bonding wires, and a resin for implementing the semiconductor chip, wherein the plurality of leads are comprised of two or more kinds of leads having different rigidities.

Abstract: A semiconductor device includes a semiconductor package, a circuit board and an interval maintaining member. The semiconductor package has a body and a lead protruded from the body. The circuit board has a first land electrically connected to the lead. The interval maintaining member is interposed between the circuit board and the body. The interval maintaining member maintains an interval between the lead and the first land. Thus, an interval between the lead and the land is uniformly maintained, so that a thermal and/or mechanical reliability of the semiconductor device is improved.

Abstract: A packaged electronic device includes a substrate with an upper surface interrupted by a well formed in the substrate. The well has a substrate bottom surface and a substrate sidewall. An electronic device is located in the well over the substrate bottom surface and has a device top surface and a device sidewall. A trench is bounded by the substrate bottom surface, the substrate sidewall and the device sidewall. An encapsulant at least partially fills the trench and contacts the substrate sidewall and the device sidewall. The encapsulant has a first elevation on the substrate sidewall with respect to the substrate bottom surface and a second elevation on the substrate device sidewall with respect to the substrate bottom surface that is at least about 35% greater than the first elevation.

Abstract: A semiconductor device includes an electrode pad and an external connection terminal. The external connection terminal contains Sn equal to or more than 50 wt %, Sn and Pb equal to or more than 90 wt % in total, or Pb equal to or more than 85 wt %, and the surface thereof is coated with an Au layer. The thickness of the Au layer is preferably equal to or more than 10 nm and equal to or less than 1 ?m. The weight of the Au layer is preferably equal to or less than 0.6% of the weight of the external connection terminal.

Abstract: An integrated circuit package system including providing a plurality of substantially identical package leads formed in a single row, and attaching bond wires having an offset on adjacent locations of the package leads.

Abstract: A semiconductor device has a chip, a first bump electrode, a conductive wire and a second bump electrode. The chip has at least one contact pad, and the first bump electrode is formed on the contact pad. The conductive wire is disposed on an active surface of the chip and electrically connected to the first bump electrode. The second bump electrode is formed on the conductive wire, and the second bump electrode is not disposed over any contact pad of the chip. In addition, a method for packaging a chip and an IC package are also disclosed.

Abstract: In one aspect of the invention, a method of attaching a semiconductor die to a microarray leadframe is described. The method comprises stamping an adhesive onto discrete areas of the microarray leadframe using a multi-pronged stamp tool. The adhesive is applied to the leadframe as a series of dots, each dot corresponding to an associated prong of the stamping tool. In some embodiments the adhesive used to attach the semiconductor die to a leadframe is a black epoxy based adhesive material. In an apparatus aspect of the invention, lead traces in a microarray leadframe are arranged to have tails that extend beyond their associated contact posts on the side of the contact post that is opposite a wire bonding region such that such lead traces extends on two opposing sides of their associated contact posts. The tails do not attach to other structures within the lead frame (such as a die attach structure).

Abstract: A packaging technique for electronic devices includes wafer fabrication of flexible contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed via a simple fabrication process with good wafer packing density. For one embodiment, a trench is formed from the back of the substrate, exposing an upper conductive layer on the top surface. A standoff is formed on the bottom surface of the substrate. A lower conductive layer is formed that runs from and electrically connects with the exposed portion of the upper conductive layer onto the substrate standoff. The standoff is removed, releasing the formed conductors, resulting in a flexible contact.

Abstract: Disclosed are molded ultra-thin semiconductor die packages, systems that incorporate such packages, and methods of making such packages. An exemplary package comprises a leadframe having an aperture formed between the leadframe's first and second surfaces, and a plurality of leads disposed adjacent to the aperture. The package further comprises a semiconductor disposed in the aperture of the leadframe with its top surface substantially flush with the leadframe's first surface, and at least one gap between at least one side surface of the semiconductor die and at least one lead of the leadframe. A body of electrically insulating material is disposed in the at least one gap. A plurality of conductive members interconnect leads of the leadframe with conductive regions on the die's top surface, with at least one conductive member having a portion disposed over at least a portion of the body of insulating material.

Abstract: A device includes a first device structure having a semiconductor platform, and a second device structure having a microstructure spaced from the semiconductor platform. The device further includes a cable having a plurality of beams to couple the microstructure to the first device structure. Each beam of the plurality of beams has a polymer coating and a serpentine-shaped region.

Abstract: A method of manufacturing a semiconductor package system including: forming a leadframe having a passive device; encapsulating the passive device to form an encapsulant interposer; attaching a first die to the encapsulant interposer; forming a substrate interposer having a second die; and stacking the encapsulant interposer over the substrate interposer.

Abstract: Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features.

Abstract: An apparatus and a method for packaging semiconductor devices. Disclosed are multi-die packaging apparatuses and techniques, especially useful for integrated circuit dice involving insulative substrates, such as silicon-on-insulator (SOI), where grounding of a base layer is not reasonably practical. Disclosed is a means for effectively grounding all layers of an integrated circuit device regardless of whether the device makes direct contact with a die-attach paddle.

Abstract: A chip-type semiconductor ceramic electronic component including a ceramic body made of a semiconductor ceramic, first external electrodes formed on opposite end surfaces of the ceramic body, and second external electrodes extending to cover surfaces of the first external electrodes and part of side surfaces of the ceramic body. A curvature radius of a corner portion of the ceramic body is R (?m), a maximum thickness of a layer of the first external electrode layer, which is in contact with the ceramic body, measured from the end surface of the ceramic body is y (?m), and a minimum thickness of a layer of the second external electrode, which is in contact with the side surface of the ceramic body, measured from an apex of the corner portion of the ceramic body is x (?m), and 20?R?50, ?0.4 x+0.6?y?0.4 is satisfied when 0.5?x?1.1, and ?0.0076 x+0.16836?y?0.4 is satisfied when 1.1?x?9.0.