Abstract: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.

Abstract: An interposer has a connection electrode formed on a surface of an insulating substrate, and a solder bump of a semiconductor chip connects to the connection electrode. The surface of the insulating substrate is roughened, and the connection electrode easily peels off from the surface of the insulating substrate. When thermal stress occurs between the semiconductor chip and the interposer, the thermal stress allows the connection electrode to peel off from the surface of the insulating substrate at the connection area with the solder bump to bring it into a floating state, and the thermal stress is absorbed due to elastic deformation of the connection electrode.

Abstract: A resin-encapsulated package includes a semiconductor IC chip, in which the ratio of the size of the semiconductor IC chip to the package size of the resin-encapsulated package including the semiconductor IC chip is large to miniaturize the resin-encapsulated package. The resin-encapsulated package is capable of dealing with increase in the operating speed of the semiconductor IC chip. The resin-encapsulated package includes a semiconductor IC chip (110) sealed in a resin molding, and a lead member (130B) having an arrangement of a plurality of discrete terminal sections (130A). Each of the terminal sections has inner terminal parts (131) to be electrically connected to terminals (115) of the semiconductor IC chip, outer terminal parts (132) to be connected to external circuits, and connecting parts (133) interconnecting the inner and the outer terminal parts.

Abstract: A method for connecting a chip to a leadframe includes forming bumps on a die by a Au stud-bumping technique, and attaching the chip to the leadframe by thermo-compression of the bumps onto bonding fingers of the leadframe. Also a flip chip-in-leadframe package is made according to the method. The package provides improved electrical performance particularly for devices used in RF applications.

Abstract: A surface mounted electronic component includes a case and a board mounting part. The board mounting part includes a leg bent in parallel with a printed circuit board at its tip, an outer frame soldered to a land of a mounted part on the board, and a projection disposed in the outer frame and inserted into a hole in the mounted part. The electronic component is mounted on a surface of the printed circuit board in various electronic instruments, and can keep to be mounted on the board tightly even when an external force is applied.

Abstract: It is to be made possible to eliminate unevenness of the inductances of bonding wires and to reduce the size of semiconductor devices. Over the surface of a semiconductor device in whose MISFET formation area a MISFET comprising a plurality of unit MISFETs connected in parallel, gate electrode pads electrically connected to the gate electrode of the MISFET and drain electrode pads electrically connected to the drain electrode of the same are arranged in a row each. The intervals of the gate electrode pads become gradually shorter from the end areas towards the central area of the electrode array of the gate electrode pads. The intervals of the drain electrode pads also become gradually shorter from the end areas towards the central area of the electrode array of the drain electrode pads.

Abstract: A system and method of assembling a ball grid array (BGA) package with IC die support is described. A stiffener is attached to a substrate that includes a centrally located opening with an integrated circuit (IC) die support structure removably held therein. An IC die is mounted to a central region of the stiffener. Further assembly process steps may be performed on the BGA package with IC die support. The IC die support structure is removed from the centrally located opening. In aspects of the invention, the IC die support structure is removably held in the opening by an adhesive tape or by one or more substrate tabs.

Abstract: A ball grid array semiconductor packaging technology is provided, which is characterized in that openings of a solder mask are formed on a given edge of a die attachment area, and entire or partial width of each opening is disposed outside the die attachment area. Accordingly, air within the opening of the solder mask is sufficiently eliminated during die bonding process, so as to prevent void formation as adhesive is filled into the opening. Therefore, in the follow-up steps, high temperature in reflowing process will not cause popcorn as in the prior-art, so as to remain good quality of the semiconductor package.

Abstract: A chip structure with bumps comprising: a chip and at least a bump. The chip has an active surface and at least a bonding pad that is formed on the active surface. The bump is disposed on the bonding pad, and the bump comprises a medium layer, a bump body and a bump body passivation layer. The medium layer whose material includes zinc is disposed on the bonding pad. The bump body whose material includes nickel is disposed on the medium layer. The bump body passivation layer whose material includes gold covers the bump body except for a portion of the bump body that connects to the medium layer.

Abstract: A method of packaging a QFN semiconductor uses a metal frame having multiple component carriers consisting of die pads and leads attached to a tape. Dies are respectively attached to and wire bonded to the component carriers. A glue wall is formed around all of the component carriers on the metal frame. When the transparent encapsulant is poured inside the glue wall, the dies and the component carriers are covered. After the tape is removed, the component carriers are cut out of the metal frame to complete the QFN semiconductors. Therefore, the method can increase the quantity and quality of QFN semiconductors produced without regard to the size of the individual QFN semiconductors.

Abstract: A semiconductor chip package includes an IC chip and a tape circuit substrate. The tape circuit substrate has a base film and a plurality of beam leads formed on the base film. One end portion of each beam lead extends from the base film, and the extended portion has a wavy portion. The wavy portion can be, for example, semicircular shaped, an S-shaped, or a zigzag shaped. The IC chip has chip pads formed on a top surface thereof. The beam lead is bonded to the chip pad through an inner lead bonding (ILB) process. During the ILB process, the wavy portion disperses the stress produced in the beam lead. Therefore, a crack or a break of the beam lead due to the stress can be effectively prevented, improving interconnection reliability between the IC chip and the tape circuit substrate.

Abstract: There is provided a high performance onboard semiconductor device with low manufacturing costs and low repair costs. The onboard semiconductor device includes a power chip substrate on which a power chip is mounted, a control substrate provided with an electrical part in relation to the power chip, and an outer enclosing case in which the power chip substrate and the control substrate are contained, and is characterized in that the control substrate and the outer enclosing case are removably fixed to each other.

Abstract: An integrated circuit package is constructed by attaching lower dies to a substrate that has bond fingers deposited on its surface. One lower die and its associated bond fingers are located offset from the center of the substrate. The lower dies are electrically coupled to the substrate's bond fingers with lower bond wires. An upper die is stacked on at least one of the lower dies. The upper die is electrically coupled, with bond wires, to the lower die upon which it is mechanically coupled. Each of the lower dies may be coupled to the other lower die with bond wire bridges that span the lower bond wires. The upper die may be electrically coupled, with bond wire bridges, to any or all of the lower dies.

Abstract: A main circuit block and a sub-circuit block are located alongside of each other on a substrate of a semiconductor integrated circuit device. A plurality of bonding pads, which are connected to external leads of the device, are disposed around the main circuit block. A plurality of first wires are disposed extending from the main circuit block into space between the bonding pads. Each wire has a shape connectable to another wire, for example the wire has a tip having a portion perpendicular to the semiconductor substrate, or the wire has a tip having a cross-wire portion which intersect with an extended line of the wire. A plurality of second wires are extended from the sub-circuit block, and each electrically connected to one of the first wires.

Abstract: A semiconductor acceleration sensor includesa non-single-crystal-silicon-based substrate, an insulating beam structure having a movable section and a stationary section, at least one piezoresistor positioned on the beam structure, an insulating supporter positioned on the non-single-crystal-silicon-based substrate for fixing the stationary section of the beam structure and forming a distance between the beam structure and the non-single-crystal-silicon-based substrate, and a thin film transistor (TFT) control circuit positioned on the non-single-crystal-silicon-based substrate and electrically connected to the piezoresistor and the beam structure.

Abstract: A semiconductor device with under bump metallurgy (UBM) and a method for fabricating the semiconductor device are provided, wherein a passivation layer is deposited on a surface of the semiconductor device where a plurality of bond pads are disposed, and formed with a plurality of openings for exposing the bond pads. A first metal layer is deposited over part of each of the bond pads and a portion of the passivation layer around the bond pad; then, a second metal layer is formed over the first metal layer and part of the bond pad uncovered by the first metal layer; subsequently, a third metal layer is formed over the second metal layer to thereby fabricate a UBM structure. Finally, a solder bump is formed on the UBM structure so as to achieve good bondability and electrical connection between the solder bump and UBM structure.

Abstract: A method of making an interactive information package, including an interactive information closure including a radio frequency identification device, contemplates that a microelectronics assembly be provided, and positioned on an associated substrate for positioning adjacent an inside surface of the top wall portion of the closure of the package. In one embodiment, the mounting substrate is provided in the form of a disc-shaped sealing liner for the closure. In an alternate embodiment, the mounting substrate is laminated to an associated sealing liner, with the substrate, and microelectronics assembly positioned thereon, inserted together with the sealing liner into the associated molded closure.

Abstract: An integrated circuit chip with ball-grid array solder balls is packaged as a module without being sealed in protective glue. The IC chip is mounted on an insulating substrate with pads to support the solder balls. The pads are connected to a second set of pads along the periphery of the substrate. Leads are pressed against the second set of pads for external connections. A second IC chip may be pressed against the other side of the substrate to increase the external connections.

Abstract: An intermediate base supports a semiconductor module on a printed circuit board. The intermediate base has an upper face on which the semiconductor component is directly mounted with its component connecting elements facing the upper face. The base has through-holes which are incorporated from a lower face of the base body so that the component conducting elements of the semiconductor component are exposed. The through-holes are then at least partially coated with a metal layer, which also contacts the exposed portions of the component connecting elements. Each of the through-holes has at least a partially annular notch, so that each through-hole extends through a recessed stud, which is used to form an external connection for the module onto the printed circuit board.

Abstract: An electronic device is provided which includes a substrate of insulating resin having at least a pair of interior terminal portions on an upper surface thereof, an electronic element mounted on the terminal portions, having at least a pair of electrode terminals thereof, and a member of insulating resin, bonded on the upper surface of said substrate. The frame includes a cavity to store the electronic element. A cover member of insulating material hermetically seals over the cavity. Electrodes are formed at or in vicinity of positions of the terminals of said electronic element to electrically conduct the interior terminal portions for connection outside the device. Alternatively, roughened surfaces can be formed on metal electrode portions, which are formed on the upper surface of substrate for electrically conducting said interior terminal portions to exterior terminal portions.

Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.

Abstract: A metallurgical interconnection for electronic devices is described, wherein the interconnection has first and second interconnection metals. The first metal is shaped to enlarge the contact area, thus providing maximum mechanical interconnection strength, and to stop nascent cracks, which propagate in the interconnection. Preferred shapes include castellation and corrugation. The castellation may include metal protrusions, which create wall-like obstacles in the interconnection zones of highest thermomechanical stress, whereby propagating cracks are stopped. The surface of the first metal has an affinity to form metallurgical contacts. The second metal is capable of reflowing. The first metal is preferably copper, and the second metal tin or a tin alloy.

Abstract: A semiconductor device includes a semiconductor structure including a semiconductor substrate having an integrated circuit portion, and a plurality of connecting pads connected to the integrated circuit portion. A plurality of distributing lines are formed on the semiconductor structure, connected to the connecting pads, and have connecting pad portions. An encapsulating layer made of a resin is formed on the semiconductor structure and upper surface of the distributing lines. A copper oxide layer is formed on at least a surface of each of the distributing lines except for the connecting pad portion.

Abstract: There is provided a semiconductor device in a package structure that can improve reliability. The semiconductor device comprises a semiconductor chip having an upper electrode and a lower electrode formed thereon; a package base bonded to the lower electrode on the semiconductor chip; and a metallic strap having first and second ends bonded through solders to the upper electrode on the semiconductor chip and a package lead. The first end of the metallic strap is bonded to the upper electrode in such a manner that a gap therebetween gradually becomes wider in a portion close to the semiconductor chip's edge toward said second end of said metallic strap.

Abstract: A three-dimensional stacked semiconductor package includes first and second semiconductor chip assemblies and a conductive bond. The first semiconductor chip assembly includes a first semiconductor chip and a first conductive trace with a first routing line and a first pillar. The second semiconductor chip assembly includes a second semiconductor chip and a second conductive trace with a second routing line and a second pillar. The chips are aligned with one another, and the pillars are disposed outside the peripheries of the chips and aligned with one another. The conductive bond contacts and electrically connects the pillars.

Abstract: A conductive plastic lead frame and method of manufacturing, the same suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment, the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Abstract: A semiconductor device comprises: a semiconductor chip having a first main surface, a second main surface, and a plurality of side surfaces; an extension portion which contacts and surrounds the side surfaces of the semiconductor chip; a base, which is capable of conducting heat generated by the semiconductor chip; an insulating film which is formed on the first face and the first main surface; a plurality of wiring patterns extended from electrode pads to the upper side of the first face of the extension portion; a sealing portion which is formed on the wiring patterns and insulating film; and a plurality of external terminals provided over the wiring patterns in a region including the upper side of the extension portion.

Abstract: A tape carrier in which a plurality of semiconductor elements can be mounted. The tape carrier includes a base tape on which device holes are formed and a plurality of leads provided on the base tape, wherein inner lead portions, which extend from the periphery of the device hole toward the center of the device hole, are of different lengths.

Abstract: A package substrate of, for example, a BGA type or a CSP type, manufactured by carrying out an electrolytic Au plating process without using any plating lead line for formation of bond fingers and solder ball pads, and a method for manufacturing the package substrate.

Abstract: An integrated circuit (100) includes a semiconductor die (102, 103) and a semiconductor package (101) that has a leadframe (20, 40, 60, 80) for mounting the semiconductor die. The leadframe includes a first laminate (20) whose bottom surface (7) is patterned with leads (106, 107, 131, 132) of the integrated circuit. A second laminate (40) has a bottom surface (3) attached to a top surface (5) of the first laminate to electrically coupling the leads to the semiconductor die.

Abstract: In one embodiment, the present invention includes an apparatus having a metal layer with a pad disposed above a substrate; and a cap disposed above the metal layer having a first portion to provide for contact with a probe and a second portion to provide a bonding surface, and the cap is electrically coupled to the pad.

Abstract: A semiconductor device and a manufacturing method for downsizing and densification achieved by reducing the thickness of the semiconductor device without an increase in area. Terminal electrodes are arranged, in plan view, outside a region where semiconductor chips are arranged. A lower semiconductor chip is placed overlapping in height the terminal electrodes, an upper semiconductor chip is placed above the lower semiconductor chip, wires connect the upper and lower semiconductor chips to the terminal electrodes, and an encapsulating resin encapsulates the upper and lower semiconductor chips and wires. The encapsulating resin has its bottom surface coplanar with the bottom surface of the terminal electrodes.

Abstract: A radio frequency power device includes a substrate including a first conductive layer, a second dielectric layer, and a third conductive layer. The first conductive layer is bonded to the second dielectric layer, and the second dielectric layer is bonded to the third conductive layer. The first and third conductive layers are electrically isolated from each other. A semiconductor die is bonded to the first conductive layer of the substrate. A plastic package encloses and protects the semiconductor die. A plurality of leads extend outwardly from the plastic package. The leads have blade-like shapes.

Abstract: A conductive plastic lead frame and method of manufacturing same suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment, the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Abstract: An integrated circuit die and/or package. An apparatus is described having a substrate with a central region and an outer region. A first plurality of electrical connections is spaced apart by a first distance on the outer region of the substrate. A second plurality of electrical connections is spaced apart by a second distance, smaller than the first distance, on the central region of the substrate.

Abstract: An interconnect assembly and methods for making and using the assembly. An exemplary embodiment of an aspect of the invention includes a contact element which includes a base portion adapted to be adhered to a substrate and a beam portion connected to and extending from the base portion. The beam portion is designed to have a geometry which substantially optimizes stress across the beam portion when deflected (e.g. it is triangular in shape) and is adapted to be freestanding. An exemplary embodiment of another aspect of the invention involves a method for forming a contact element. This method includes forming a base portion to adhere to a substrate of an electrical assembly and forming a beam portion connected to the base portion. The beam portion extends from the base portion and is designed to have a geometry which substantially evenly distributes stress across the beam portion when deflected and is adapted to be freestanding.

Abstract: A manufacturing method using a modular substrate-based processing scheme for producing semiconductor devices, provides multiple modular processing units which may be arranged together to form any of various cohesive processing units or individually or sequentially processed through standard semiconductor processing equipment. The cohesive processing units are processed unitarily providing for multiple modular processing units to be processed simultaneously. The modular processing units may be formed of a thick semiconductor substrate or a semiconductor substrate mounted on a further substrate such as a ceramic material. The modular processing units may each contain ribs, grooves, posts or other features to aid in handling and placement of the individual units.

Abstract: A packaged power semiconductor device (24) with voltage isolation between a metal backside (34) and the terminals (38) of the device. A direct-bonded copper (“DBC”) substrate (28) is used to provide electrical isolation and good thermal transfer from the device to a heatsink. A power semiconductor die (26) is soldered or otherwise mounted to a first metal layer (30) of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. The leads and die may be soldered to the DBC substrate in a single operation. In one embodiment, over 3,000 Volts of isolation is achieved. In another embodiment, the packaged power semiconductor device conforms to a TO-247 outline.

Abstract: A semiconductor device is disclosed that includes a semiconductor die, a metal leadframe, and a metal strap. A bottom surface of the semiconductor device is on and electrically coupled to a first portion of the leadframe. A first end portion of the metal strap is on and electrically coupled to a top surface of the semiconductor die. An opposite, second end portion of the metal strap is on and electrically coupled to a second portion of the leadframe within a recess of the second portion of the leadframe.

Abstract: A metallurgical interconnection for electronic devices is described, wherein the interconnection has first and second interconnection metals. The first metal is shaped to enlarge the contact area, thus providing maximum mechanical interconnection strength, and to stop nascent cracks, which propagate in the interconnection. Preferred shapes include castellation and corrugation. The castellation may include metal protrusions, which create wall-like obstacles in the interconnection zones of highest thermomechanical stress, whereby propagating cracks are stopped. The surface of the first metal has an affinity to form metallurgical contacts. The second metal is capable of reflowing. The first metal is preferably copper, and the second metal tin or a tin alloy.

Abstract: Semiconductor devices and methods of forming semiconductor devices are described. In one embodiment, at least one conductive structure is formed within a plurality of semiconductor substrates. At least portions of one of the conductive structures have oppositely facing, exposed outer surfaces. Individual substrates are stacked together in a die stack such that individual conductive structures on each substrate are in electrical contact with the conductive structures on a next adjacent substrate. In a preferred embodiment, the conductive structures comprise multi-layered, conductive pad structures.

Abstract: Parts of pad electrodes formed on an interconnection board so as to correspond to bump electrodes of a semiconductor pellet that neighbor parts superposed with the bump electrodes are caused to extend in substantially the same direction, and ultrasonic vibration is applied in this extension direction so as to make a connection between the pad electrodes and the bump electrodes.

Abstract: A LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. An underfill material is introduced between each lead finger and semiconductor die, extending from the bonding location of the die and the edge of the die, in order to prevent filler particles from lodging between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The seal created by the underfill material reduces point stresses on the active surface of the die usually caused by the filler particles. The decreased flexure in the leads further enhances the locking of the leads in position with respect to the die.

Abstract: A method of connecting a conductive trace and an insulative base to a semiconductor chip includes providing a semiconductor chip, a conductive trace and an insulative base, wherein the chip includes a conductive pad, the conductive trace includes a bumped terminal, the bumped terminal includes a cavity that extends through the insulative base, and the insulative base contacts the conductive trace on a side opposite the chip, then forming a through-hole that extends through the insulative base and exposes the conductive trace and the pad, and then forming a connection joint that contacts and electrically connects the conductive trace and the pad. Preferably, an insulative adhesive that attaches the chip to the conductive trace or an encapsulant that encapsulates the chip fills the cavity and provides compressible mechanical support for the bumped terminal.

Abstract: A main circuit block and a sub-circuit block are located alongside of each other on a substrate of a semiconductor integrated circuit device. A plurality of bonding pads, which are connected to external leads of the device, are disposed around the main circuit block. A plurality of first wires are disposed extending from the main circuit block into space between the bonding pads. Each wire has a shape connectable to another wire, for example the wire has a tip having a portion perpendicular to the semiconductor substrate, or the wire has a tip having a cross-wire portion which intersect with an extended line of the wire. A plurality of second wires are extended from the sub-circuit block, and each electrically connected to one of the first wires.

Abstract: System for providing an open-cavity semiconductor package. The system includes a method for wire bonding a finger sensor die to an external circuit. The finger sensor die includes a sensor array having one or more die contacts that are wire bonded to one or more external contacts of the external circuit so that a usable portion of the sensor array is maximized. The method comprises steps of forming a ball at a first end of a bonding wire, forming an electrically conductive connection between the ball and a selected external contact of the external circuit, extending the bonding wire to a selected die contact so as to form a wire loop having a low loop height, and forming an electrically conductive stitch connection between a second end of the bonding wire and the selected die contact.

Abstract: Aspects of the invention provide microelectronic device assemblies including microelectronic components wire bonded to substrates, and methods of forming such assemblies. In one embodiment of the invention, a microelectronic component includes a plurality of multi-layered bond pads. Each of the multi-layered bond pads includes a bond pad base (which may comprise aluminum), an outer bond layer (which may comprise gold), and an intermediate layer between the bond pad base and the outer bond layer. This microelectronic component may be wire bonded to a substrate, with the outer bond layer and the bonding wire both comprising the same metal (e.g., gold). The bonding wire may be reliably stitch bonded to the outer bond layer of the multi-layered bond pads, facilitating manufacture of low profile microelectronic device assemblies.

Abstract: In order to provide a semiconductor apparatus in which both semiconductor chips and interposers are provided on a carrier tape, electrical properties can be improved using short wiring in a wiring pattern substantially symmetric with respect to the semiconductor chips, production can become easier, and compactness and heat radiation can be improved. Semiconductor chips electrically connected to wiring formed on the carrier tape, and interposers on the carrier tape and surrounding the semiconductor chips, are provided next to each other.

Abstract: To fabricate back side contact pads that are suitable for use in a vertical integrated circuit, vias are made in the face side of a wafer, and dielectric and contact pad metal are deposited into the vias. Then the wafer back side is etched until the metal is exposed. When the etch exposes the insulator at the via bottoms, the insulator is etched slower than the wafer material (e.g. silicon). Therefore, when the dielectric is etched off and the metal is exposed, the dielectric protrudes down from the wafer back side around the exposed metal contact pads, by about 8 &mgr;m in some embodiments. The protruding dielectric portions improve insulation between the wafer and the contact pads when the contact pads are soldered to an underlying circuit. In some embodiments, before the contact pads are soldered, additional dielectric is grown on the wafer back side without covering the contact pads.

Abstract: A semiconductor assembly includes a leadframe with leads having offset portions exposed at an outer surface of a material package to form a grid array. An electrically conductive compound, such as solder, may be disposed or formed on the exposed lead portions to form a grid array such as a ball grid array (“BGA”) or other similar array-type structure of dielectric conductive elements. The leads may have inner bond ends including a contact pad thermocompressively bonded to a bond pad of the semiconductor chip to enable electrical communication therewith and a lead section with increased flexibility to improve the thermocompressive bond. The inner bond ends may also be wirebonded to the bond pads. Components for and methods of forming semiconductor assemblies are included.