Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.

Abstract: There is provided a flexible display having a new wire structure and a new insulating layer structure. A flexible display includes a flexible substrate having a first area and a second area. The second area is curved in a non-zero angle relative to the plane of the first area. The flexible display further includes a plurality of wires that extend over from the first area to the second area of the flexible substrate. Each of the wires is covered by an upper insulating pattern, which is separated from other upper insulating pattern. Each upper insulating pattern covering the wire has substantially the same trace pattern shape of the corresponding wire thereunder. Accordingly, by adopting the above-described wire structure and upper insulating layer structure, crack generation and propagation in the wires and the insulating layers from bending of the flexible display can be minimized.

Abstract: An embodiment includes an apparatus comprising: a first layer, including a first semiconductor switching element, coupled to a first portion of a first bonding material; and a second layer, including a second semiconductor switching element, coupled to a second portion of a second bonding material; wherein (a) the first layer is over the second layer, (b) the first portion is directly connected to the second portion, and (c) first sidewalls of the first portion are unevenly serrated. Other embodiments are described herein.

Abstract: An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.

Abstract: A modification to the standard layout of vias used for vertically-stacked wafer bonding is proposed which has been found to improve the interconnect overlay while avoiding the dishing problems associated with the planarization processes used in the creation of conductive posts within the vias. In particular, the pitch, i.e. the spacing between adjacent posts, is intentionally chosen to be different for each wafer. By using different pitches, there is an increase in the probability of overlap of posts on each wafer, even when one wafer is slightly offset with respect to the other (which is possible when aligning one wafer with another in a standard bonding tool). Advantageously, the use of different pitches allows for the use of relatively small diameter (one micron or less) posts while still creating sufficient overlap for the necessary connections.

Abstract: A process for manufacturing surface-mount semiconductor devices, in particular of the Quad-Flat No-Leads Multi-Row type, comprising providing a metal leadframe, in particular a copper leadframe, which includes a plurality of pads, each of which is designed to receive the body of the device, the pads being separated from adjacent pads by one or more rows of wire-bonding contacting areas, outermost rows from among the one or more rows of wire-bonding contacting areas identifying, together with outermost rows corresponding to the adjacent pads, separation regions.

Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.

Abstract: An object of the present invention is to provide a power module that secures a heat dissipation route and has increased reliability. A power module of the present invention includes a first circuit body having a first semiconductor element and a first conductor portion, a second circuit body having a second semiconductor element and a second conductor portion, a resin sealing material for sealing the first circuit body and the second circuit body, and a warpage suppression portion that is formed along an array direction of the first circuit body and the second circuit body and is formed to have greater rigidity than a sealing portion of the resin sealing material, wherein the warpage suppression portion is formed of the same material as a resin member of the resin sealing material and is formed to be thicker than the sealing portion of the resin sealing material.

Abstract: A process of forming, on a surface of the substrate a plurality of resist layers made of two kinds of dry film resist that differ in main peak wavelength in spectral photosensitivity. An exposure process of selectively exposing and affecting a particular resist layer in accordance with a first pattern upon using a first exposure mask overlaid on the plurality of resist layers. A second exposure process of exposing another resist layer in accordance with a second pattern upon using a second exposure mask overlaid on the plurality of resist layers. Partially uncovering the surface of the substrate by removing unexposed portions of the plurality of resist layers, to form a resist mask having an aperture. Finally, forming a coat layer by plating a portion of the substrate where the surface thereof is uncovered; and a process of removing the resist mask.

Abstract: A bonding pad of a semiconductor chip in a QFP includes, in its exposed portion, a via disposition area comprising: a first segment that connects a corner and a first point; a second segment that connects the corner and a second point; and an arc that connects the first point and the second point and forms a convex shape toward the corner. Further, in a plan view of the bonding pad, at least a part of a via is disposed so as to overlap with the via disposition area.

Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.

Abstract: A three-dimensional memory device includes conductive structures located over a substrate, an alternating stack of insulating layers and electrically conductive layers formed over the conductive structures, and an array of memory structures formed through the alternating stack. Each of the memory structures includes memory elements located at levels of the electrically conductive layers. A contact region can be formed on the alternating stack. Two-stage contact via cavities having a greater width above a top surface of a respective electrically conductive layer and having a narrower width through the alternating stack can be formed in the contact region. Upper insulating spacers and lower insulating spacers are formed such that annular surfaces of the respective electrically conductive layer are physically exposed. Two-stage contact via structures can provide electrical contact between the electrically conductive layers and the conductive structures.

Abstract: Converter output terminals of a converter are located adjacent to each other on a first side and an external terminal for external connection of a composite module is located adjacent to the converter output terminal. AC input terminals of the converter are located on a second side. Each of the distances between the converter output terminals and between the converter output terminal and the external terminal is set to a first formation pitch. Each of the distances between the AC input terminals is set to a second formation pitch. The first formation pitch is set to be equal to the second formation pitch.

Abstract: An integrated circuit chip includes an interconnection stack with a cavity formed therein. The cavity extends through one or more interconnection levels of the stack. A material at least partially fills the cavity. The fill material has a selectivity to polishing and/or to etching different by more than 10% from a selectivity to polishing and/or to etching of a material forming an insulator of the interconnection stack.

Abstract: A radio frequency identifier (RFID) tag is provided for receiving and reflecting electromagnetic energy at select frequency bands of visible and infrared wavelengths. The RFID tag includes an electrically conductive backplane; a dielectric substrate disposed on the backplane; a light guide film (LGF) disposed on the substrate, and metamaterial elements. The LGF has an exposed surface segregated into domains. The metamaterial devices are disposed on a domain. Each device is tuned to respond to a corresponding frequency among the select frequency bands.

Abstract: A semiconductor package device includes a first die, an adhesive layer, and an encapsulant layer. The first die comprises a first electrode at a first surface of the first die and a second electrode at a second surface of the first die opposite to the first surface of the first die. The adhesive layer is disposed on the first surface of the first die. The encapsulant layer encapsulates the first die and the adhesive layer, wherein substantially an entire surface of the second electrode is exposed from the encapsulant layer.

Abstract: Devices, packaging devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes a molding material and a plurality of through-vias disposed within the molding material. A dummy through-via and an integrated circuit die are also disposed within the molding material. An interconnect structure is disposed over the molding material, the plurality of through-vias, the dummy through-via, and the integrated circuit die.

Abstract: An optoelectronic component includes a first lead frame section and a second lead frame section spaced apart from one another, and having an optoelectronic semiconductor chip arranged on the first lead frame section and the second lead frame section, wherein the first lead frame section and the second lead frame section respectively have an upper side, a lower side and a first side flank extending between the upper side and the lower side, a first lateral solder contact surface of the optoelectronic component is formed on the first side flank of the first lead frame section, and the first lateral solder contact surface is formed by a recess arranged on the first side flank of the first lead frame section and extends from the upper side to the lower side of the first lead frame section.

Abstract: The present disclosure relates to a chip including a wafer, a back-end-of-line (BEOL) layer deposited on the wafer, a chip TSV in the wafer containing a conductive material, and a chip cap layer disposed between the chip TSV and the BEOL layer, and configured to reduce via extrusion of conductive material in the chip TSV during operation of the chip. The present disclosure further includes a 3D integrated circuit including a plurality of electrically connected chips, at least one of which is a chip as described above. The disclosure further relates to a 3D integrated circuit with an interposer, a TSV in the interposer containing a conductive material, and an interposer cap layer configured to reduce via extrusion of the conductive material located in the interposer TSV during operation of the circuit. The present disclosure further includes methods of forming such chips and 3D integrated circuits.

Abstract: A semiconductor memory device includes a cell array region formed on a substrate, a word line contact region, and a page buffer region coupled to the cell array region through bit lines, wherein at least one of the bit lines has a curved structure toward the word line contact region. According to an embodiment, a misalignment between a cell plug and a contact plug caused by a natural cell plug bending phenomenon may be reduced to improve operational reliability of a semiconductor memory device.

Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a layer disposed over a substrate. A conductive body extends through the layer. A plurality of bar or pillar structures are spaced apart from one another and laterally surround the conductive body. The plurality of bar or pillar structures are generally concentric around the conductive body.

Abstract: A three-dimensional semiconductor device is provided as follows. A substrate includes a contact region, a dummy region, and a cell array region. A stack structure includes electrodes vertically stacked on the substrate. The electrodes are stacked to have a first stepwise structure on the contact region and a second stepwise structure in the dummy region. Ends of at least two adjacent electrodes in the second stepwise structure have first sidewalls vertically aligned so that horizontal positions of the first sidewalls are substantially the same.

Abstract: A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and an opening. The pad structure may include a first stepped structure and a second stepped structure located between the first cell structure and the second cell structure. The first stepped structure may include first pads electrically connected to the first and second cell structures and stacked on top of each other, and the second stepped structure may include second pads electrically connected to the first and second cell structures and stacked on top of each other. The circuit may be located under the pad structure. The opening may pass through the pad structure to expose the circuit, and may be located between the first stepped structure and the second stepped structure to insulate the first pads and the second pads from each other.

Abstract: A semiconductor device structure includes a first metal layer formed over a substrate and an interconnect structure formed over the first metal layer. The interconnect structure includes an upper portion, a middle portion and a lower portion, the middle portion is connected between the upper portion and the lower portion. The upper portion and the lower portion each have a constant width, and the middle portion has a tapered width which is gradually tapered from the upper portion to the lower portion.

Abstract: Provided herein is a semiconductor device including N stacked groups (where N is a natural number greater than or equal to two) sequentially stacked over a substrate, each stacked group including interlayer insulating films and conductive patterns alternately stacked, and N concave portions each having stepped sidewalls formed in the interlayer insulating films and the conductive patterns of the stacked groups, the N concave portions each having stepped sidewalls being aligned in a first direction.

Abstract: A compact and high-reliability semiconductor device is implemented. The bonding wires situated in the vicinity of a gate, and the bonding wires situated in the vicinity of a vent facing to the gate across the center of a semiconductor chip in a molding step have a loop shape falling inwardly of the semiconductor chip, have a weaker pulling force (tension) than those of other bonding wires, and are loosely stretched with a margin. The bonding wires situated in the vicinity of the gate in the molding step are, for example, a first wire and a fifth wire to be connected with a first electrode pad and a fifth electrode pad, respectively. Whereas, the bonding wires situated in the vicinity of the vent in the molding step are, for example, a third wire and a seventh wire to be connected with a third electrode pad and a seventh electrode pad, respectively.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present disclosure describe integrated circuit (IC) package assemblies and methods of fabricating IC package assemblies. These embodiments include dies embedded in embedding substrates to provide larger pitch interconnects to facilitate coupling to substrates or circuit boards through flip chip techniques. The embedding substrates may contain conductive pathways for coupling die contacts to larger pitch contacts located on the embedding substrate. By embedding the dies in the embedding substrates, dies having smaller pitch contacts can be used in package assemblies with larger pitch components without the need for silicon interposers and without having to utilize more stringent pick and place operations. Other embodiments may be described and/or claimed.

Abstract: Implementations of a clip for a semiconductor package may include: an electrically conductive clip having a first end and a second end and a middle section between the first end and the second end. The first end may be configured to couple to a first die through a bonding material. The second end may be configured to couple to a second die through a bonding material. The middle section may be configured to couple to an emitter structure through a bonding material. The clip may include an integrally formed electrically conductive material and include an M-shape. A middle of the M-shape may be coupled to the emitter structure.

Abstract: The disclosure provides in one embodiment an electrical conductor pathway system for diverting an electric charge. The electrical conductor pathway system includes a substrate having a first surface to be printed on and having one or more grounding points. The electrical conductor pathway system further includes a direct write conductive material pattern printed directly onto the first surface via a direct write printing process. The direct write conductive material pattern forms one or more electrical pathways interconnected with the one or more grounding points. The one or more electrical pathways interconnected with the one or more grounding points divert the electric charge from the first surface to the one or more grounding points.

Abstract: A device for drying and sintering metal-containing ink on a substrate enables homogeneous irradiation of the substrate, has compact construction, and is simple and economical to produce. Optical infrared radiators have a cylindrical radiator tube and a longitudinal axis, and emit radiation having an IR-B radiation component of at least 30% and an IR-C radiation component of at least 5% of total radiator output power. The radiators are arranged in a module with their longitudinal axes running parallel to each other and transverse to the transport direction. They thereby irradiate on the surface of the substrate an irradiation field, which is divided into a drying zone and a sintering zone arranged downstream of the drying zone in the transport direction. The drying zone is exposed to at least 15% less average irradiation density than the sintering zone along a center axis running in the transport direction.

Abstract: A method for manufacturing a semiconductor device includes forming a conductive pattern on a substrate, forming a filling insulation layer covering the conductive pattern, forming a contact hole in the filling insulation layer and adjacent to the conductive pattern, forming an opening in the conductive pattern by removing a portion of the conductive pattern adjacent to the contact hole such that the opening is connected to the contact hole, and forming a contact plug filling the contact hole and the opening. A width of the opening is greater than a width of the contact hole.

Abstract: A pixel comprises three adjacent sub-pixels, formed by respective stacks of semi-conducting layers wherein: each sub-pixel comprises a first active layer, adapted for emitting a light at a first wavelength when an electric current passes through it; another sub-pixel comprises a second active layer, adapted for emitting a light at a second wavelength greater than the first wavelength; another sub-pixel comprises a third active layer, adapted for emitting a light at a third wavelength greater than the first wavelength and different from the second wavelength; at least one from among the second and third active layers being adapted for emitting light when it is excited by the light at the first wavelength emitted by the first active layer of the same sub-pixel. Semi-conducting structure and methods for the fabrication of such a pixel are provided.

Abstract: In an exemplary method, three dimensional printing forms a micro lattice truss structure with a first end formed in contact with a conductive area on a PCB so that the truss structure is adhered to the conductive area due to the three dimensional printing. The truss structure extends outward from the PCB and has a distal end. The truss structure is formed with resiliency so that the truss structure maintains structural integrity during end-to-end compression. The resiliency of the micro lattice truss structure enables the truss structure to return to substantially its uncompressed length when the compression is removed. The truss structure is conductive so that a resilient electrical connection can be formed between the conductive area of the PCB and another spaced apart surface parallel with the PCB when the distal end of the truss structure is in contact with and compressed by the other surface.

Abstract: A substrate includes a first dielectric structure, a first circuit layer, a second dielectric structure and a second circuit layer. The first circuit layer is embedded in the first dielectric structure, and does not protrude from a first surface of the first dielectric structure. The second dielectric structure is disposed on the first surface of the first dielectric structure. The second circuit layer is embedded in the second dielectric structure, and is electrically connected to the first circuit layer. A first surface of the second circuit layer is substantially coplanar with a first surface of the second dielectric structure, and a surface roughness value of a first surface of the first circuit layer is different from a surface roughness value of the first surface of the second circuit layer.

Abstract: According to one embodiment, columnar portions extend through an insulating layer and through a stacked body under the insulating layer. The columnar portions are of an insulating material different from the insulating layer. Contact portions include a first contact portion disposed inside a first terrace portion and a second contact portion disposed inside a second terrace portion. The columnar portions including a first columnar portion disposed inside the first terrace portion and a second columnar portion disposed inside the second terrace portion. A shortest distance between the first contact portion and the first columnar portion, and a shortest distance between the second contact portion and the second columnar portion are substantially equal to each other.

Abstract: Techniques disclosed herein provide a method for substrate patterning that results in lines of non-uniform pitch (mixed pitch). Techniques can also enable advanced patterning options by selectively replacing lines of material in a multi-line layer. A multi-line layer is formed that has alternating lines of three different materials. One or more etch masks are used to selectively remove at least one uncovered line without removing other uncovered lines. Removed material is replaced with a fill material. Selective removal is executed using an etch mask as well as differing etch resistivities of the different lines of materials.

Abstract: The present disclosure provides an optoelectronic device comprising a semiconductor stack comprising a first side having a first length; a first contact layer on the semiconductor stack; and a second contact layer on the semiconductor stack opposite to the first contact layer, wherein the second contact layer is not overlapped with the first contact layer in a vertical direction; and wherein the second contact layer comprises multiple contact regions separated from each other and arranged in a two-dimensional array, wherein a first distance between the two adjacent contact regions is between 0.8% and 8% of the first length.

Abstract: Integrated circuits and methods of forming the same are provided herein. In an embodiment, an integrated circuit includes a semiconductor substrate that has an isolated well. A multilayer metallization stack overlies the semiconductor substrate. The multilayer metallization stack includes a metal layer, a functional via, and a dummy metal feature. The metal layer includes a first line in electrical communication with the isolated well through a contact. The functional via is in electrical communication with the first line and the contact. The dummy metal feature is in electrical communication with the functional via.

Abstract: A semiconductor device includes merged contact plugs. A multi-fin active having N sub-fins is formed in a substrate. A contact plug is formed on the impurity areas. N is an integer between about eight (8) and about one thousand (1000). The N sub-fins include a first sub-fin formed in the outermost portion of the multi-fin active and a second sub-fin formed near the first sub-fin. A straight line perpendicular to a surface of the substrate and passes through a virtual bottom edge of the contact plug is disposed between the first sub-fin and the second sub-fin, or through the second sub-fin. The virtual bottom edge of the contact plug is defined at a cross point of a correlation line extending on a side surface of the contact plug and a horizontal line in contact with a lowermost end of the contact plug and parallel to the surface of the substrate.

Abstract: A through via structure includes a semiconductor substrate, an underlying insulation layer, a conductive via and a sidewall insulation layer. The underlying insulation layer is over the semiconductor substrate. The conductive via is through the semiconductor substrate and the underlying insulation layer. The sidewall insulation layer is between the semiconductor substrate and the conductive via. The sidewall insulation layer includes a protrusion proximal to an interface between the semiconductor substrate and the underlying insulation layer, and protruding outwardly into the semiconductor substrate.

Abstract: A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.

Abstract: An electronic module is presented. The electronic module includes one or more electronic devices and a first bus electrically coupled to at least one of the one or more electronic devices. The first bus includes a first electrically conductive plate, a second electrically conductive plate, and a first electrically insulating plate disposed between the first electrically conductive plate and the second electrically conductive plate, where in a first portion of the first bus, the first electrically insulating plate is disposed such that the first electrically insulating plate is not in direct physical contact with at least one of the first electrically conductive plate and the second electrically conductive plate to form at least one cavity between the first electrically insulating plate and at least one of the first electrically conductive plate and the second electrically conductive plate. An electronic module assembly having low loop inductance is also presented.

Abstract: A method according embodiments of the invention includes providing a wafer of semiconductor devices. The wafer of semiconductor devices includes a semiconductor structure comprising a light emitting layer sandwiched between an n-type region and a p-type region. The wafer of semiconductor devices further includes first and second metal contacts for each semiconductor device. Each first metal contact is in direct contact with the n-type region and each second metal contact is in direct contact with the p-type region. The method further includes forming a structure that seals the semiconductor structure of each semiconductor device. The wafer of semiconductor devices is attached to a wafer of support substrates.

Abstract: A semiconductor chip may include a semiconductor substrate having a front surface and a rear surface which faces away from the front surface. The semiconductor chip may include a fixed metal layer formed over the front surface of the semiconductor substrate, and having first metal lines formed in the fixed metal layer. The semiconductor chip may include a configurable metal layer formed over the fixed metal layer to have one surface which faces the fixed metal layer and the other surface which faces away from the one surface, and having second metal lines formed in the configurable metal layer such that at least one end of the second metal lines disposed on the one surface are respectively connected with the first metal lines and other ends of the second metal lines facing away from the at least one end are disposed at predetermined positions on the other surface.

Abstract: Implementations disclosed herein generally relate to methods of forming silicon oxide films. The methods can include performing silylation on the surface of the substrate having terminal hydroxyl groups. The hydroxyl groups on the surface of the substrate are then regenerated using a plasma and H2O soak in order to perform an additional silylation. Further methods include catalyzing the exposed surfaces using a Lewis acid, directionally inactivating the exposed first and second surfaces and deposition of a silicon containing layer on the sidewall surfaces. Multiple plasma treatments may be performed to deposit a layer having a desired thickness.

Abstract: A conductive layer is formed on the first zone of a carrier. The redistribution layer is formed on the conductive layer on the first zone and the second zone of the carrier. Then an open-test and a short-test are performed to the redistribution layer. Since the conductive layer and the parts of the redistribution layer formed on the conductive layer constitute a closed loop, a load is presented if the redistribution layer is formed correctly. In addition, no load is presented if the redistribution layer is formed correctly since the parts of the redistribution layer formed on the second zone of the carrier constitute an open loop. Therefore, whether the redistribution layer is flawed or not is determined before the dies are boned on the redistribution layer. Thus, no waste of the good die is occurred because of the flawed redistribution layer.

Abstract: A semiconductor device includes a porous dielectric layer formed on an interconnect layer and including a recessed portion, a conductive layer formed in the recessed portion, and a conformal cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the conformal cap layer. Porous dielectric material is protected by back-filled pore fillers or leave-in porogens from process integration such as chemical mechanical polishing (CMP). The pore fillers or porogens are removed after CMP and Cap process to achieve low capacitance. A self-aligned cap protects the conductor metal from exposing the severe conditions during the pore filler or porogen removal process.

Abstract: An optoelectronic device comprises a substrate; a groove on the substrate; a plurality of semiconductor units on the substrate and separated by the groove, wherein each semiconductor unit comprises a first semiconductor layer, a second semiconductor layer, and an active region interposed between the first semiconductor layer and the second semiconductor layer; a connecting part crossing the groove for connecting two of the plurality of semiconductor units, wherein the connecting part comprises one end on the first semiconductor layer and another end on the second semiconductor layer; a first electrode comprising a plurality of first extensions jointly connected to the one end of the connecting part; and a second electrode comprising a plurality of second extensions jointly connected to the another end of the connecting part, wherein an amount of the plurality of first extensions is different from an amount of the plurality of second extensions.

Abstract: A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.