Abstract: A force input sensor can include a strain-sensitive region disposed as a meandering electrical trace onto a structural or functional layer of a display stack. In particular, the meandering electrical trace can include one or more diversions from a linear path, each diversion configured to increase the length of the electrical trace. A diversion can form a loop to increase the inductance of the meandering electrical trace; the inductance of the meandering electrical trace can be correlated to length of the inductive trace which, in turn, can be correlated to strain experienced by the structural or functional layer.

Abstract: A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a connect die that routes electrical signals between a plurality of other semiconductor die.

Abstract: An example integrated circuit (IC) assembly includes: a substrate, and a first IC die stacked on a second IC die, a stack of the first IC die and the second IC die mounted to the substrate. The first IC die includes an active side, a backside, a plurality of through-silicon vias (TSVs) exposed on the backside, an electrostatic discharge (ESD) circuit on the active side, and metallization on the active side. The metallization includes a first plurality of metal layers disposed on the active side and a second plurality of metal layers disposed on the first plurality of metal layers, each of the second plurality of metal layers thicker than each of the first plurality of metal layers. The metallization further includes a U-route that electrically couples a first TSV of the plurality of TSVs to the ESD circuit, the U-route including a conductive path through the second plurality of metal layers.

Abstract: Phase change memory cells, structures, and devices having a phase change material and an electrode forming an ohmic contact therewith are disclosed and described. Such electrodes can have a resistivity of from 10 to 100 mOhm·cm.

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first trench isolation is formed in a substrate. A second trench isolation is formed in the substrate after the step of forming the first trench isolation. The second trench isolation is formed at a side of the first trench isolation, and the second trench isolation is directly connected with the first trench isolation. The semiconductor structure includes the substrate, the first trench isolation, and the second trench isolation. A material of the second trench isolation is different from a material of the first trench isolation. The first trench isolation is disposed at one side of the second trench isolation, and the second trench isolation is directly connected with the first trench isolation.

Abstract: A semiconductor device includes a plurality of electrode structures formed on a substrate; and an upper supporter group and a lower supporter between upper ends and lower ends of the plurality of electrode structures The upper supporter group includes a plurality of supporters, and at least some of the plurality of supporters each have an upper surface and a lower surface. One of the upper surface and the lower surface has a curved profile, and the other surface has a flat profile.

Abstract: A semiconductor device includes a metal column that extends in a stretching direction; a polymer layer that surrounds the metal column from a direction crossing the stretching direction; and a guide that surrounds the polymer layer in the crossing direction so as to be spaced from the metal column with the polymer layer interposed therebetween. A method for manufacturing semiconductor devices includes a step of filling a mixture containing metal particles and polymers in a guide; and a step of subjecting the mixture to a heat treatment so that the polymers agglomerate to the guide to form a polymer layer that makes contact with the guide and the metal particles agglomerate away from the guide with the polymer layer interposed therebetween to form a metal column that stretches in a stretching direction of the guide from the metal particles.

Abstract: A semiconductor device includes a semiconductor substrate comprising a MOS transistor. A MEMS device is integrally constructed above the MOS transistor. The MEMS device includes a bottom electrode in a second topmost metal layer, a diaphragm in a pad metal layer, and a cavity between the bottom electrode and the diaphragm.

Abstract: The invention provides a TFT backplane and manufacturing method thereof, wherein the TFT backplane comprises a substrate (1); a gate (11) and a first metal electrode (21) formed on the substrate (1); a gate insulating layer (31) formed on the substrate (1) and covering the gate (11) and the first metal electrode (21), the gate insulating layer (31) on the first metal electrode (21) having a thickness less than thickness of the gate insulating layer (32) on the gate (11); an etch stop layer (ESL) (5) on the gate insulating layer (31) and a second metal electrode (22) on the ESL (5). Only a portion of the gate insulating layer deposited on the first metal electrode is etched away, and the first metal electrode always protects the gate insulating layer, so that the first metal electrode is not damaged by the etching gas, favorable for the final storage capacitor.

Abstract: Embodiments of methods of forming staircase structures for three-dimensional (3D) memory devices double-sided routing are disclosed. In an example, a first dielectric layer is formed on a substrate, and a first photoresist layer is formed on the first dielectric layer. A recess is patterned through the first dielectric layer to the substrate by cycles of trim-etch the first dielectric layer. Dielectric/sacrificial layer pairs are formed on the first dielectric layer and filling in the recess. A second photoresist layer is formed on the dielectric/sacrificial layer pairs. The dielectric/sacrificial layer pairs are patterned by cycles of trim-etch the dielectric/sacrificial layer pairs. A second dielectric layer is formed on the first dielectric layer and covering the patterned dielectric/sacrificial layer pairs.

Abstract: A light-emitting diode display device includes a light-emitting diode and a substrate. The light-emitting diode includes a central axis, and the substrate includes a first connecting portion and a second connecting portion. The central axis is extended through the first connecting portion. The second connecting portion is disposed outside of the first connecting portion and is spaced apart from the first connecting portion by a distance which is greater than zero, and the first connecting portion and the second connecting portion are respectively electrically connected to the light-emitting diode.

Abstract: Although each drain electrode extension portion which is a connection region between a drain electrode and a pixel electrode does not transmit visible light, making an end side of the drain electrode extension portion coincide with an end side of the pixel electrode can improve an aperture ratio. In addition, making each semiconductor layer with high resistance protrude from the end side of the drain electrode extension portion can restrict an increase in parasitic capacitance and bring the drain electrode extension portion closer to the gate wiring.

Abstract: An oxide semiconductor device includes a substrate, a first patterned oxide semiconductor layer, a source electrode, a drain electrode, and a sidewall spacer. The first patterned oxide semiconductor layer is disposed on the substrate. The source electrode and the drain electrode are disposed on the first patterned oxide semiconductor layer. The sidewall spacer is disposed on a sidewall of the first patterned oxide semiconductor layer. The sidewall spacer may be used to improve the performance of blocking impurities from entering the first patterned oxide semiconductor layer via the sidewall, and the electrical performance and the reliability of the oxide semiconductor device may be enhanced accordingly.

Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.

Abstract: Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.

Abstract: An optoelectronic device comprises a substrate; a groove on the substrate; a plurality of semiconductor units on the substrate and separated by the groove, wherein each semiconductor unit comprises a first semiconductor layer, a second semiconductor layer, and an active region interposed between the first semiconductor layer and the second semiconductor layer; a connecting part crossing the groove for connecting two of the plurality of semiconductor units, wherein the connecting part comprises one end on the first semiconductor layer and another end on the second semiconductor layer; a first electrode comprising a plurality of first extensions jointly connected to the one end of the connecting part; and a second electrode comprising a plurality of second extensions jointly connected to the another end of the connecting part, wherein an amount of the plurality of first extensions is different from an amount of the plurality of second extensions.

Abstract: An electronic package apparatus is formed from a semiconductor substrate having a cavity formed therein. The cavity has a top surface, a bottom surface and a sidewall surface, and a spacer extending from the bottom surface to the top surface. The spacer is formed from a dielectric material and has at least one lateral dimension less than 0.1 cm.

Abstract: A circuit board and a layout structure are provided. The layout structure includes a plurality of chip carrying areas, a plurality of inner layer connection pads and a plurality of outer leading wires. The chip carrying areas respectively carry a plurality of chips. The outer leading wires are disposed between the inner layer connection pads and the chip carrying areas. The layout structure is disposed on at least one circuit board and connects to a plurality of wires of the at least one circuit board through the outer leading wires, and the outer leading wires and the wires of the at least one circuit board are formed by sharing at least one metal layer.

Abstract: A semiconductor device includes a substrate, a plurality of lower electrodes disposed on the substrate and are repeatedly arranged in a first direction and in a second direction that crosses the first direction, and a first electrode support contacting a sidewall of at least one of the lower electrodes. The first electrode support includes a first support region including a first opening and a second support region disposed at a border of the first support region. An outer sidewall of the first electrode support includes a first sidewall extending in the first direction, a second sidewall extending in the second direction, and a connecting sidewall connecting the first and second sidewalls. The second support region includes the connecting sidewall. In a first portion of the second support region, a width of the first portion of the second support region decreases in a direction away from the first support region.

Abstract: A backgrind (BG) tape includes an adhesive material having a thinner tape region with a first thickness having an area sized to accommodate a substrate therein including an active semiconductor top side surface including a plurality of chips each including at least one transistor and at least one metallization level with bond pads connected to nodes of the transistor and bumps on or coupled to the bond pads. The BG tape also includes a thicker tape region along at least a periphery of the BG tape having a second thickness that is greater than the first thickness.

Abstract: A first substrate has a first mesa structure that protrudes from a first bonding-side planar surface. A first metal pad structure is embedded within the first mesa structure. A second substrate has a first recess cavity that is recessed from a second bonding-side planar surface. A second metal pad structure is located at a recessed region of the first recess cavity. The first bonding-side planar surface and the second bonding-side planar surface are brought into physical contact with each other, while the first mesa structure is disposed within a volume of the first recess cavity by self-alignment. A gap is provided between the first metal pad structure and the second metal pad structure within a volume of the first recess cavity. A metal connection pad is formed by selectively growing a third metallic material from the first metal pad structure and the second metal pad structure.

Abstract: Methods of wetting a semiconductor substrate may include forming a controlled atmosphere in a processing chamber housing the semiconductor substrate. The semiconductor substrate may define a plurality of features, which may include vias. The methods may include flowing a wetting agent into the processing chamber. A chamber pressure may be maintained below about 100 kPa. The methods may also include wetting the plurality of features defined in the substrate.

Abstract: A semiconductor device includes a first active region that extends on a substrate in a first direction, a second active region that extends in parallel with the first active region, an element isolation region between the first and second active regions, a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions, a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region, and an upper contact on the lower contact between the first active region and the second active region. A width of the lower contact in the first direction that is on the first active region m narrower than a width of the lower contact in the first direction that is on the element isolation region.

Abstract: A method of forming conductive lines in a circuit is disclosed. The method includes arranging a plurality of signal traces in a first set of signal traces and a second set of signal traces, fabricating, using a first mask, a first conductive line for a first signal trace of the first set of signal traces and fabricating, using a second mask, a second conductive line for a second signal trace of the second set of signal traces. Each signal trace of the first set of signal traces has a first width. Each signal trace of the second set of signal traces has a second width different from the first width. The arranging is based on at least a length of a signal trace of the plurality of signal traces.

Abstract: A silicon-on-insulator substrate which includes a semiconductor substrate, a buried oxide layer, and a semiconductor layer is provided. A hard mask layer is formed over a first region of the silicon-on-insulator substrate. A first silicon-germanium layer is epitaxially grown on the semiconductor layer within a second region of the silicon-on-insulator substrate. The second region is at least a portion of the semiconductor layer not covered by the hard mask layer. A thermal annealing process is performed, such that germanium atoms from the first silicon-germanium layer are migrated to the portion of the semiconductor layer to form a second silicon-germanium layer. The hard mask layer is removed. A layer of semiconductor material is epitaxially grown on top of the semiconductor layer and the second silicon-germanium layer, where the layer of semiconductor material composed of the same material as semiconductor layer.

Abstract: An optoelectronic component and a method for producing an optoelectronic component are disclosed. In an embodiment the component includes a semiconductor chip, a molded body and an electrical through-contact constituting an electrically conductive connection through the molded body. The through-contact and the semiconductor chip are embedded alongside one another and are spaced apart in the molded body. A first contact pad of the through-contact is arranged at an underside of the molded body. A second contact pad of the through-contact is arranged at a top side of the molded body. The second contact pad is electrically conductively connected to the electrical contact of the semiconductor chip. The through-contact is arranged such that a molded body is arranged at least in a section between the first and second contact pads on a straight line between the first and second contact pads.

Abstract: It is an object to particularly improve compositions of interlayer insulation films so as to provide semiconductor devices which exert high elongation percentage, are excellent in adherence and are hard to generate a crack, and methods of manufacturing the devices, and a semiconductor device (1) of the present invention is a semiconductor device provided with a semiconductor element (2) and a redistribution layer (4) electrically connected to the semiconductor element, and is characterized in that a solvent with specific gravity of 0.96 g/cm3 or more at a temperature of 25° C. remains in an amount of 5 ppm or more relative to the entire weight of an interlayer insulation film (6) inside the interlayer insulation film of the redistribution layer. According to the semiconductor device of the present invention, it is possible to exert high elongation percentage, provide excellent adherence, and suppress generation of a crack.

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having a hard masks for sidewall image transfer (SIT) block patterning. The method includes forming a first hard mask on a substrate. Spacers are formed on the first hard mask, and a second hard mask is formed over the spacers. The second hard mask and a portion of the first hard mask are concurrently removed by the same hard mask removal process to expose a surface of the substrate. After concurrently removing the second hard mask and portions of the first hard mask, the heights of the spacers are substantially equal.

Abstract: To achieve a high-reliability germanium photoreceiver. A photoreceiver portion of a germanium photoreceiver comprised of a p type silicon core layer, an i type germanium layer, and an n type silicon layer is covered with a second insulating film and from a coupling hole formed in the second insulating film, a portion of the upper surface of the photoreceiver portion is exposed. The coupling hole has, on the inner wall thereof, a barrier metal film and the barrier metal film has thereon a first-layer wiring made of a tungsten film. Tungsten hardly diffuses from the tungsten film into the i type germanium layer even when a thermal stress is applied, making it possible to prevent the resulting germanium photoreceiver from having diode characteristics deteriorated by the thermal stress.

Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a conductive structure having a top surface, and a pair of sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface, and rails are along the sidewall surfaces. The rails include sacrificial material. The sacrificial material is removed to leave openings. Sealant material is formed to extend within the openings. The sealant material has a lower dielectric constant than the insulative material. Some embodiments include an integrated assembly having a conductive structure with a top surface and a pair of opposing sidewall surfaces extending downwardly from the top surface. Insulative material is over the top surface. Voids are along the sidewall surfaces and are capped by sealant material. The sealant material has a lower dielectric constant than the insulative material.

Abstract: A trench isolation structure is provided. The trench isolation structure includes a substrate. A polygonal trench is disposed in the substrate. An insulating material is disposed in the polygonal trench, and a polygon top-side contact structure is disposed in the polygonal trench and surrounded by the insulating material. The polygon top-side contact structure has the same shape as the polygonal trench from a top view. A method for forming the trench isolation structure is also provided.

Abstract: A semiconductor device includes a low-density substrate, a high-density patch positioned inside a cavity in the low-density substrate, a first semiconductor die, and a second semiconductor die. The first semiconductor dies includes high-density bumps and low-density bumps. The second semiconductor die includes high-density bumps and low-density bumps. The high-density bumps of the first semiconductor die and the high-density bumps of the second semiconductor die are electrically connected to the high-density patch. The low-density bumps of the first semiconductor die and the low-density bumps of the second semiconductor die are electrically connected to the low-density substrate.

Abstract: The application provides a double-sided plastic fan-out package structure having an antenna structure. It includes a redistribution layer (RDL); a semiconductor chip, invertedly mounted on a first surface of the redistribution layer with a front surface facing downward; a first plastic encapsulation material layer, located on the first surface of the redistribution layer, encapsulating the semiconductor chip; a second plastic encapsulation material layer, located on a second surface of the redistribution layer; an antenna structure, located on a surface of the second plastic packaging material layer distant from the redistribution layer; an electrical connection structure, located inside the second plastic encapsulation material layer, and electrically connected to the antenna structure on the lower side of the redistribution layer. This structure can shield an interference signal of the antenna structure, thereby preventing the antenna structure from interfering the semiconductor chip.

Abstract: A semiconductor package including a redistribution substrate, and a semiconductor chip mounted on the redistribution substrate, the semiconductor chip having a conductive pad on one surface thereof may be provided. The redistribution substrate may include a first passivation pattern on the conductive pad, the first passivation pattern exposing a portion of the conductive pad, and a redistribution pattern covering the portion of the conductive pad exposed by the first passivation pattern and surrounding the first passivation pattern.

Abstract: An embedded power module includes a substrate, first and second semiconducting dies, first and second gates, and first and second vias. The first semiconducting die is embedded in the substrate and spaced between opposite first and second surfaces of the substrate. The second semiconducting die is embedded in the substrate, is spaced between the first and second surfaces, and is spaced from the first semiconducting die. The first gate is located on the first surface. The second gate is located on the second surface. The first via is electrically engaged to the first gate and the second semiconducting die, and the second via is electrically engaged to the second gate and the first semiconducting die.

Abstract: A semiconductor device and a fabricating method of semiconductor device are disclosed. The semiconductor device includes: a substrate having a bonding pad on a surface of the substrate; at least two semiconductor components each having a first surface and a second surface opposite the first surface, the semiconductor components stacked on top of each other on the surface of the substrate via a layer of component attach material attached on the second surface of the respective semiconductor component; an integral through via hole extending completely through the semiconductor components and the layers of component attach material and having a substantially uniform diameter along an extending direction of the integral through via hole aligned with the bonding pad on the surface of the substrate, and a continuous conductive material filled in the integral through via hole and in physical and electrical contact with the bonding pad of the substrate.

Abstract: Various self-aligned interconnect structures are disclosed herein. An exemplary interconnect structure includes a first dielectric layer disposed over a substrate; a first conductive feature disposed in the first dielectric layer; an etch stop layer disposed over a top surface of the first dielectric layer and a top surface of the first conductive feature; a second dielectric layer disposed over the first dielectric layer; and a second conductive feature disposed in the second dielectric layer. The top surface of the first conductive feature is lower than the top surface of the first dielectric layer. The etch stop layer includes a portion that extends between the top surface of the first conductive feature and the top surface of the first dielectric layer, on which the second conductive feature may or may not be disposed. In some implementations, the second conductive feature may be a via feature.

Abstract: A method for generating a power distribution network (PDN) is provided. A heterogeneous circuit data is input. A plurality of horizontal power lines and a plurality of vertical power lines are determined according to the heterogeneous circuit data. A PDN model of the heterogeneous circuit is determined according to the horizontal power lines and the vertical power lines. Power consumption value is assigned to a plurality of internal nodes of the PDN model of the heterogeneous circuit. The PDN model of the heterogeneous circuit is adjusted to meet a target voltage drop limitation of the heterogeneous circuit data.

Abstract: A semiconductor structure includes: a semiconductor substrate arranged over a back end of line (BEOL) metallization stack, and including a scribe line opening; a conductive pad having an upper surface that is substantially flush with an upper surface of the semiconductor substrate, the conductive pad including an upper conductive region and a lower conductive region, the upper conductive region being confined to the scribe line opening substantially from the upper surface of the semiconductor substrate to a bottom of the scribe line opening, and the lower conductive region protruding downward from the upper conductive region, through the BEOL metallization stack; a passivation layer arranged over the semiconductor substrate; and an array of pixel sensors arranged in the semiconductor substrate adjacent to the conductive pad.

Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.

Abstract: There is provided a flexible display having a new wire structure and a new insulating layer structure. A flexible display includes a flexible substrate having a first area and a second area. The second area is curved in a non-zero angle relative to the plane of the first area. The flexible display further includes a plurality of wires that extend over from the first area to the second area of the flexible substrate. Each of the wires is covered by an upper insulating pattern, which is separated from other upper insulating pattern. Each upper insulating pattern covering the wire has substantially the same trace pattern shape of the corresponding wire thereunder. Accordingly, by adopting the above-described wire structure and upper insulating layer structure, crack generation and propagation in the wires and the insulating layers from bending of the flexible display can be minimized.

Abstract: An embodiment includes an apparatus comprising: a first layer, including a first semiconductor switching element, coupled to a first portion of a first bonding material; and a second layer, including a second semiconductor switching element, coupled to a second portion of a second bonding material; wherein (a) the first layer is over the second layer, (b) the first portion is directly connected to the second portion, and (c) first sidewalls of the first portion are unevenly serrated. Other embodiments are described herein.

Abstract: An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.

Abstract: A modification to the standard layout of vias used for vertically-stacked wafer bonding is proposed which has been found to improve the interconnect overlay while avoiding the dishing problems associated with the planarization processes used in the creation of conductive posts within the vias. In particular, the pitch, i.e. the spacing between adjacent posts, is intentionally chosen to be different for each wafer. By using different pitches, there is an increase in the probability of overlap of posts on each wafer, even when one wafer is slightly offset with respect to the other (which is possible when aligning one wafer with another in a standard bonding tool). Advantageously, the use of different pitches allows for the use of relatively small diameter (one micron or less) posts while still creating sufficient overlap for the necessary connections.

Abstract: A process for manufacturing surface-mount semiconductor devices, in particular of the Quad-Flat No-Leads Multi-Row type, comprising providing a metal leadframe, in particular a copper leadframe, which includes a plurality of pads, each of which is designed to receive the body of the device, the pads being separated from adjacent pads by one or more rows of wire-bonding contacting areas, outermost rows from among the one or more rows of wire-bonding contacting areas identifying, together with outermost rows corresponding to the adjacent pads, separation regions.

Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.

Abstract: An object of the present invention is to provide a power module that secures a heat dissipation route and has increased reliability. A power module of the present invention includes a first circuit body having a first semiconductor element and a first conductor portion, a second circuit body having a second semiconductor element and a second conductor portion, a resin sealing material for sealing the first circuit body and the second circuit body, and a warpage suppression portion that is formed along an array direction of the first circuit body and the second circuit body and is formed to have greater rigidity than a sealing portion of the resin sealing material, wherein the warpage suppression portion is formed of the same material as a resin member of the resin sealing material and is formed to be thicker than the sealing portion of the resin sealing material.

Abstract: A process of forming, on a surface of the substrate a plurality of resist layers made of two kinds of dry film resist that differ in main peak wavelength in spectral photosensitivity. An exposure process of selectively exposing and affecting a particular resist layer in accordance with a first pattern upon using a first exposure mask overlaid on the plurality of resist layers. A second exposure process of exposing another resist layer in accordance with a second pattern upon using a second exposure mask overlaid on the plurality of resist layers. Partially uncovering the surface of the substrate by removing unexposed portions of the plurality of resist layers, to form a resist mask having an aperture. Finally, forming a coat layer by plating a portion of the substrate where the surface thereof is uncovered; and a process of removing the resist mask.

Abstract: A bonding pad of a semiconductor chip in a QFP includes, in its exposed portion, a via disposition area comprising: a first segment that connects a corner and a first point; a second segment that connects the corner and a second point; and an arc that connects the first point and the second point and forms a convex shape toward the corner. Further, in a plan view of the bonding pad, at least a part of a via is disposed so as to overlap with the via disposition area.

Abstract: A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.