Abstract: A slim type touch panel is provided. The slim type touch panel includes an upper substrate, a first sensor electrode layer disposed at a lower part of the upper substrate, an insulating film disposed at a lower part of the first sensor electrode layer, and a second sensor electrode layer disposed at a lower part of the insulating film, or includes a first sensor electrode cover sheet in which a sensor electrode layer is patterned, a first adhesive layer disposed at a lower part of the first sensor electrode cover sheet, and a film layer disposed at a lower part of the first adhesive layer and comprising a second sensor electrode layer.

Abstract: An electrical component is formed with a directed self assembly portion having a random electrical characteristic, such as resistance or capacitance. The random pattern can be produced by using a directed self assembly polymer with guide structures 2 including randomness inducing features. The electrical components with the random electrical characteristics may be used in electrical circuits relying upon random variation in electrical characteristics, such as physically unclonable function circuitry. The electrical components may be resistors and/or capacitors.

Abstract: A wiring board includes: an insulating layer; a pad including: an upper surface; a lower surface opposite to the upper surface; and a side surface between the upper surface and the lower surface, wherein the side surface and the lower surface of the pad are embedded in the insulating layer; and a metal post formed on the upper surface of the pad and including: an upper surface; a lower surface opposite to the upper surface; and a side surface between the upper surface and the lower surface, wherein a narrowed portion is formed in the side surface of the metal post.

Abstract: A semiconductor device package comprising a circuit chip and a wafer level chip scale package is designed for reducing capacitive interactions which exist between electrically conducting portions of the circuit chip and under-bump metallization areas of the package. Such design is beneficial in particular for under-bump metallization areas which are dedicated to transferring signals having frequencies above 30 GHz.

Abstract: A semiconductor device includes a dielectric structure which has an opening exposing a surface of a substrate; and a conductive structure which is formed in the opening, wherein the conductive structure comprises: a first conductive pattern recessed in the opening; a second conductive pattern covering a top surface and sidewalls of the first conductive pattern; an air gap defined between sidewalls of the opening and the second conductive pattern; and a third conductive pattern capping the second conductive pattern and the air gap.

Abstract: A wiring board includes: an insulating layer; and a wiring layer including: an upper surface; a lower surface opposite to the upper surface; and a side surface between the upper surface and the lower surface, wherein the upper surface of the wiring layer is exposed from the insulating layer, and the side surface and the lower surface of the wiring layer are embedded in the insulating layer. A recess portion is formed in an outer edge portion of the upper surface of the wiring layer, and the recess portion is filled with the insulating layer.

Abstract: Embodiments of mechanisms of a semiconductor device package and package on package (PoP) structure are provided. The semiconductor device package includes a substrate and a metal pad formed on the substrate. The semiconductor device package further includes a conductive element formed on the metal pad, and the metal pad electrically contacts the conductive element, and at least a portion of the conductive element is embedded in a molding compound, and the conductive element has a recess configured to provide an additional bonding interfacial area.

Abstract: A method of making an electronic device includes forming an electrically conductive pattern on a substrate, forming a cover layer on the substrate and the electrically conductive pattern, and forming openings in the cover layer and being aligned with the electrically conductive pattern. The method also includes positioning an IC on the cover layer so that bond pads of the IC are aligned with the openings, and heating under pressure the cover layer to both mechanically secure and electrically interconnect the IC.

Abstract: An array substrate and manufacturing method thereof, a display device are provided. The array substrate includes a display region and a non-display region; the non-display region includes a first laminated structure and a second laminated structure that are separately disposed on a base substrate, a gap between the first laminated structure and the second laminated structure constitutes a connecting hole; the first laminated structure includes a first via hole provided for exposing a first metal layer, the second laminated structure includes a second via hole provided for exposing a second metal layer, the first via hole and the second via hole are connected to a connecting hole via breaches on corresponding walls, and the first metal layer and the second metal are electrically connected with a conductive film.

Abstract: A stretchable wire assembly includes a metal wire coupled between two elastic substrates. The two elastic substrates are selectively coupled together, and the metal wire is attached to one or both elastic substrates at select locations. The form of the metal wire is such that when the elastic substrates are in a relaxed, or non-stretched, state the metal wire forms a tortuous path, such as a waveform, along the coupled elastic substrates. The tortuous path of the metal wire provides slack such that as the elastic substrates are stretched the slack is taken up. Once released, the elastic substrates move from the stretched position to the relaxed, non-stretched position, and slack is reintroduced into the metal wire in the form of the original tortuous path.

Abstract: A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.

Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die.

Abstract: A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors. For example, a two turn inductor and a three turn inductor may share masks for interconnects and coils, while only masks necessary for connections between the interconnects and coils may need to be newly developed.

Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes forming, on a film to be processed, a plurality of first core material patterns and a plurality of second core material patterns. Each of the second core material patterns is drawn from an end portion of the corresponding first core material pattern. The manufacturing method includes forming an opening pattern having one or a plurality of openings in the second core material pattern so that a first distance and a second distance are less than a predetermined distance. The first distance is a distance between an edge of the second core material pattern at a side of an adjacent first core material pattern and the opening pattern. The second distance is a distance between an edge of the second core material pattern at a side of an adjacent second core material pattern and the opening pattern.

Abstract: A semiconductor device includes a semiconductor substrate, and a redistribution layer (RDL) over the semiconductor substrate and configured to receive a bump. The semiconductor device further includes a polymeric material over the RDL, and the polymeric material includes an opening to expose a portion of the RDL. In the semiconductor device, a barrier is covering a joint between the polymeric material and the RDL.

Abstract: Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts.

Abstract: A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.

Abstract: In some embodiments, an interconnect structure includes a base layer, a plurality of dielectric layers and a conductive structure. The base layer includes a conductive region. The plurality of dielectric layers are formed over the base layer. The plurality of dielectric layers includes a first dielectric layer and an etch stop layer under the first dielectric layer. The conductive structure includes a plug. The plug includes a central region and one or more footing regions. The footing regions are formed around the central region and formed at least partially in the first etch stop layer. A total width of the central region and one or more footing regions at a bottom level of the plurality of dielectric layers is at least about 5% more than a width of the central region at the bottom level of the plurality of dielectric layers.

Abstract: A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.

Abstract: A semiconductor chip includes a plurality of stacked conductive layers. The plurality of stacked conductive layers includes a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer is disposed on a first side of the second conductive layer. The third conductive layer is disposed on a second side of the second conductive layer. The third conductive layer is disposed on a side of the second conductive layer. The second conductive layer has a thickness which is thicker than those of the first conductive layer and the third conductive layer.

Abstract: A semiconductor device includes a semiconductor substrate including a plurality of active areas, a bit line crossing the plurality of active areas, a direct contact connecting a first active area of the plurality of active areas with the bit line, an insulating spacer covering a side wall of the bit line and extending at a level lower than a level of an upper surface of the semiconductor substrate, a contact pad connected with a side wall of a second active area of the plurality of active areas, which neighbors the first active area, a first insulating pattern defining a contact hole exposing the insulating spacer and the contact pad, and a buried contact connected with the contact pad and filling the contact hole.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.

Abstract: A semiconductor device with thin redistribution layers is disclosed and may include forming a first redistribution layer on a dummy substrate, electrically coupling a semiconductor die to the first redistribution layer, and forming a first encapsulant layer on the redistribution layer and around the semiconductor die. The dummy substrate may be removed thereby exposing a second surface of the first redistribution layer. A dummy film may be temporarily affixed to the exposed second surface of the redistribution layer and a second encapsulant layer may be formed on the exposed top surface of the semiconductor die, a top surface and side edges of the first encapsulant layer, and side edges of the first redistribution layer. The dummy film may be removed to again expose the second surface of the first redistribution layer, and a second redistribution layer may be formed on the first redistribution layer and on the second encapsulant layer.

Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.

Abstract: Microelectronic components and methods forming such microelectronic components are disclosed herein. The microelectronic components may include a plurality of electrically conductive vias in the form of wire bonds extending from a bonding surface of a substrate, such as surfaces of electrically conductive elements at a surface of the substrate.

Abstract: A semiconductor chip at least includes a row of first electrode pad group, which includes at least one first independent electrode pad and multiple first common electrode pads. The interval between the first independent electrode pad and an electrode pad adjacent thereto is defined as “first pitch”, and the interval between adjacent electrode pads making up the multiple first common electrode pads is defined as “second pitch”. The first pitch is determined to be larger than the second pitch.

Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Abstract: An integrated circuit (IC) memory device includes a first conductive layer. The IC memory device also includes a second conductive layer over the first conductive layer. The IC memory device further includes a first-type pin box electrically coupled with the first conductive layer. The IC memory device additionally includes a second-type pin box, different from the first-type pin box, electrically coupled with the second conductive layer.

Abstract: The present disclosure provides a contact window structure. In the contact window structure, a first insulating layer, having a first opening, is positioned on a first metal layer, wherein the first opening exposes a part of the first metal layer. A second metal layer covers the first opening and contacts with the first metal layer via the first opening. A second insulating layer, having a second opening, is positioned on the first insulating layer, wherein the second opening exposes a part of the second layer and the first insulating layer. The projection area of the second opening on the first metal layer covers the projection area of the first opening on the first metal layer. A pixel structure containing the contact window structure and a manufacturing method thereof are also provided herein.

Abstract: An aluminum (Al) layer is formed over a semiconductor substrate. A selective portion of the Al layer is removed to form openings. The Al layer is anodized to obtain an alumina dielectric layer with a plurality of pores. The openings are filled with a conductive interconnect material. The pores are widened to form air gaps and a top etch stop layer is formed over the alumina dielectric layer.

Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.

Abstract: Provided is semiconductor package, including a semiconductor chip; an upper structure over the semiconductor chip, the upper structure having a first thermal expansion coefficient; and a lower structure under the semiconductor chip, the lower structure having a second thermal expansion coefficient of less than or equal to the first thermal expansion coefficient.

Abstract: A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers.

Abstract: A chip package includes a chip, an isolation layer, and a redistribution layer. The chip has a substrate, an electrical pad, and a protection layer. The substrate has a first surface and a second surface. The substrate has a through hole, and protection layer has a concave hole, such that the electrical pad is exposed through the concave hole and the through hole. The isolation layer is located on the second surface, the sidewall of the through hole, and the sidewall of the concave hole. The redistribution layer includes a connection portion and a passive element portion. The connection portion is located on isolation layer and in electrical contact with the electrical pad. The passive element portion is located on isolation layer that is on second surface, and an end of passive element portion is connected to connection portion that is on the second surface.

Abstract: A display may have an array of pixels. Each pixel may have a light-emitting diode that emits light under control of a drive transistor. The organic light-emitting diodes may have a common cathode layer, a common electron layer, individual red, green, and blue emissive layers, a common hole layer, and individual anodes. The hole layer may have a hole injection layer stacked with a hole transport layer. Pixel circuits for controlling the diodes may be formed from a layer of thin-film transistor circuitry on a substrate. A planarization layer may cover the thin-film transistor layer. Lateral leakage current between adjacent diodes can be blocked by shorting the common hole layer to a metal line such as a bias electrode that is separate from the anodes. The metal line may be laterally interposed between adjacent pixels and may be formed on the planarization layer or embedded within the planarization layer.

Abstract: A wiring substrate includes a core layer including a plate-like body and linear conductors, a first wiring layer formed on a first surface of the plate-like body, and an insulating layer formed on the first surface. A gap between the adjacent linear conductors is smaller than a diameter of each linear conductor. The linear conductors include a first linear conductor disposed in a position overlapping with the first wiring layer and conducting to the first wiring layer and a second linear conductor disposed in a position not overlapping with the first wiring layer. An end surface of the first linear conductor on the side of the first surface is approximately flush with the first surface. An end surface of the second linear conductor on the side of the first surface is in a position more depressed than the first surface to form a hole. The insulating layer is filled in the hole.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A dielectric layer is deposited over a substrate and a hard mask (HM) layer is deposited over the dielectric layer. A line-like opening is formed in the HM layer and a line-end opening are then formed in the HM layer to connect to the line-like opening at the end of the line-like opening. The dielectric layer is etched through the line-like opening and the line-end opening to form a dielectric trench and a conductive line is formed in the dielectric trench.

Abstract: A semiconductor apparatus disclosed in this disclosure includes a first channel formed in a first area and including a first power supply pad, a first clock pad, a first command address pad, a first data input/output pad and a first memory cell array; a second channel formed in a second area and including a second power supply pad, a second clock pad, a second command address pad, a second data input/output pad and a second memory cell array, the first and second channels being independently controllable from each other; and mesh structure lines straddling the first area and second area and connected to the first and second power supply pads.

Abstract: A semiconductor module includes first and second semiconductor elements connected to pins, respectively; a first pin wiring substrate having first and second metal films bonded to the pin on the upper and lower surfaces; a first DCB substrate having third and fourth metal films on the upper and lower surfaces, the third metal film being bonded to the lower surface of the first semiconductor element; a second DCB substrate having fifth and sixth metal films respectively provided on the lower and upper surfaces, the fifth metal film being bonded to the upper surface of the second semiconductor element; a second pin wiring substrate having seventh and eighth metal films bonded to the pin, on the upper and lower surfaces; a connection member connected to the second and fifth metal films; a first cooler connected to the fourth metal film; and a second cooler connected to the sixth metal film.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate having a trench, a stacked strip structure formed in the trench, and at least a conductive structure. The stacked strip structure includes a plurality of interlaced conductive strips and insulating strips. Each of the conductive strips has a horizontal conductive segment and two vertical conductive segments connected to the corresponding horizontal conductive segment. Each of the insulating strips has a horizontal insulating segment and two vertical insulating segments. The conductive structure is electrically connected to at least one of the conductive strips. The stacked strip structure has a horizontal stacked portion corresponding to the horizontal conductive segments and two vertical stacked portions corresponding to the vertical conductive segments, wherein a width of the vertical stacked portions is larger than a thickness of the horizontal stacked portion.

Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.

Abstract: A system and method for bonding semiconductor devices is provided. An embodiment comprises halting the flow of a eutectic bonding material by providing additional material of one of the reactants in a grid pattern, such that, as the eutectic material flows into the additional material, the additional material will change the composition of the flowing eutectic material and solidify the material, thereby stopping the flow. Other embodiments provide for additional layouts to put the additional material into the path of the flowing eutectic material.

Abstract: Organic light-emitting diode (OLED) displays and methods of manufacturing OLD displays are disclosed. In one aspect, an OLED display includes a substrate having an emission area and a non-emission area, a pixel electrode formed in the emission area, and an intermediate layer formed over the pixel electrode and including an organic emission layer. The display also includes an opposite electrode formed in the emission and non-emission areas and at least partially covering the intermediate layer. The display further includes a black matrix formed over the opposite electrode and including a first light-blocking portion formed in the non-emission area and a second light-blocking portion formed in the emission area and having light transmittance greater than that of the first light-blocking portion.

Abstract: In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.

Abstract: A system, method, and computer program product are provided for producing a high bandwidth bottom package of a die-on-package structure. The method includes the steps of receiving a bottom package comprising a substrate material having a top layer and an integrated circuit die that is coupled to the top layer of the substrate material. A first set of pads is formed on the top layer of the substrate material and a layer of dielectric material is applied on a top surface of the bottom package to cover the integrated circuit die and the first set of pads.

Abstract: A semiconductor device includes a plurality of sets of external drive terminals in a marginal region along one long side of a rectangular semiconductor substrate, a plurality of sets of ESD protection circuits arranged in the marginal region and coupled to corresponding sets of the drive terminals, and a plurality of output circuits coupled to corresponding sets of the drive terminals. Each set of drive terminals in a plurality of n columns along a Y direction is laid out in a staggered arrangement with drive terminals in adjacent columns shifted relative to each other. Each output circuit includes n output units associated with n drive terminals of each set and arranged in one column in an X direction. By the arrangement, the drive terminals can be arranged at a narrower pitch, and the total width for n output units can be compacted into that of one output circuit.

Abstract: A method of forming a semiconductor device includes forming a plurality of word lines separated by air gaps with contact pad structures connected to the word lines, and forming a dummy structure directly opposite an air gap between neighboring word lines. Subsequently, the contact pad structures are cut into individual contact pads by a contact pad cut that intersects the dummy structure.

Abstract: Wide and narrow mandrels that are used to form sidewall spacers for patterning are formed in a sacrificial layer with openings in wide mandrels near sides of the wide mandrels. Sidewall spacers are formed on the sides of mandrels and the sacrificial layer is removed. The sidewall spacers are then used for patterning of underlying layers.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A first dielectric layer is deposited on the substrate. A patterned photoresist layer is formed on the first dielectric layer. The patterned photoresist layer is trimmed. The first dielectric layer is etched through the trimmed patterned photoresist layer to form a dielectric feature. A sacrificing energy decomposable layer (SEDL) is deposited on the dielectric feature and etched to form a SEDL spacer on sides of the dielectric feature. A second dielectric layer is deposited on the SEDL spacer and etched to form a dielectric spacer. The SEDL spacer is decomposed to form a trench.

Abstract: The present invention provides an array substrate, a display panel and a display device, which can be used for solving the problem of an existing array substrate that ESD occurs between a data line and a repair line to cause short-circuiting of the data line and the repair line so as to pull down the voltage of the data line. The array substrate includes a plurality of main signal lines, at least one main repair line arranged to be crossed with and insulated from the main signal lines at the peripheral area of the array substrate, and a redundant repair line, and the redundant repair line is arranged to be insulated from the main repair line; wherein the redundant repair line includes at least one redundant repair part, and the resistance of each redundant repair part is smaller than the resistance of each main repair line.