Abstract: A metal layer structure is disclosed. The metal layer structure includes a substrate, a first dielectric layer on a surface of the substrate, and at least one first conductor and at least one second conductor on the first dielectric layer. The second conductor has at least one thin portion.

Abstract: Methods of fabricating a semiconductor device are provided. Methods of forming a finer pattern of a semiconductor device using a buffer layer for retarding, or preventing, bridge formation between patterns in the formation of a finer pattern below resolution limits of a photolithography process by double patterning are also provided. A first hard mask layer and/or a second hard mask layer may be formed on a layer of a substrate to be etched. A first etch mask pattern of a first pitch may be formed on the second hard mask layer. After a buffer layer is formed on the overall surface of the substrate, a second etch mask pattern of a second pitch may be formed thereon in a region between the first etch mask pattern. The buffer layer may be anisotropically etched using the second etch mask pattern as an etch mask, forming a buffer layer pattern.

Abstract: A semiconductor device includes a semiconductor chip, electrodes pads, first and second insulating layers, first and second conductive patterns and external terminals. The electrode pads are formed on a first area of a main surface of the semiconductor chip. The first insulating layer is formed on the first and second areas of the semiconductor chip and exposes the electrode pads. The first conductive pattern transfers a signal and is formed on the first insulating layer. A second insulating layer is formed on the first conductive pattern and the first insulating layer. The second conductive pattern is formed on the second insulating layer and provides a ground potential. The external terminals are formed on the first and second patterns at the second area.

Abstract: A semiconductor package having improved adhesiveness between the chip paddle and the package body and having improved ground-bonding of the chip paddle. A plurality of through-holes are formed in the chip paddle for increasing the bonding strength of encapsulation material in the package body. A plurality of tabs are formed in the chip paddle may also be used alone or in conjunction with the through-holes to further increase the bonding strength of the encapsulation material in the package body. The tabs provide additional area for the bonding site to ground wires from the semiconductor chip by increasing the length of the chip paddle.

Abstract: A method for manufacturing an electronic component includes: cutting a wiring substrate along a line intersecting with an outline of a reinforcing member, the wiring substrate including a base substrate, a wiring pattern provided to a first surface of the base substrate, and the reinforcing member provided to a second surface of the base substrate; and attaching a reinforcing sticker to the base substrate after cutting the wiring substrate so as to cover at least a part of a crack produced in the base substrate in cutting the wiring substrate.

Abstract: Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. A first opening, a second opening, and a third opening are formed in a substrate such that the first opening, the second opening, and the third opening are in communication with each other. A portion of the first opening, the second opening, and the third opening are filled with a conductive material. Semiconductor devices, including the vias of the present invention, are also disclosed. Semiconductor components and assemblies resulting therefrom, and an electronic system, including the vias of the present invention, are further disclosed.

Abstract: A filet F is added to a portion constituting a corner portion C equal to or smaller than 90° in a crossing portion X of wiring patterns 58b, 58c and 58d, and a wiring pattern 58 is formed. Since the filet F is added, the wiring patterns are not made thin and are not disconnected in the crossing portion X. Further, since there is no stress concentrated to the crossing portion X, disconnection is not caused in the wiring patterns and no air bubbles are left between the crossing portion X of the wiring patterns and an interlayer resin insulating layer so that reliability of a printed wiring board is improved.

Abstract: A semiconductor device having a silicon layer, a transistor having an electrical connection region in the silicon layer; and a conductive plug formed on and in electrical contact with the electrical connection region, the plug having side walls that taper inward away from the silicon layer.

Abstract: A semiconductor device capable of preventing an electrical short between contacts and their adjacent contact pads and a method of manufacturing the same are provided. A first interlayer insulating layer is formed on the semiconductor substrate including the active region. Contact pads pass through the first interlayer insulating layer and contact with the active region. Contacts are formed on the contact pads and are connected to a conductive layer disposed above the contacts. The contact pads have a height lower than a top surface of the first interlayer insulating layer such that the contact pads have smaller thickness than the first interlayer insulating layer.

Abstract: A wafer structure including a semiconductor substrate, a number of UBM layers and a number of bumps is provided. The semiconductor substrate has an active surface, a number of bonding pads and a passivation layer. The bonding pads are positioned on the active surface of the semiconductor substrate. The passivation layer covers the active surface of the semiconductor substrate and exposes the bonding pads. The UBM layers are respectively arranged on the bonding pads, and each UBM layer includes an adhesive layer, a super-lattice barrier layer and a wetting layer. The adhesion layer is disposed on bonding pads. The super-lattice barrier layer is disposed on the adhesion layer and includes a number of alternately stacked sub-barrier layers and sub-wetting layers. The wetting layer is disposed on the super-lattice barrier layer, and the bump is disposed on the wetting layer.

Abstract: An integrated circuit chip includes a buffer layer, an underlying layer, a dielectric layer, a hole, and barrier layer. The buffer layer is over the underlying layer. The dielectric layer is over the buffer layer. The hole is formed in and extending through the dielectric layer and the buffer layer, and opens to the underlying layer. The hole includes a buffer layer portion at the buffer layer and a dielectric layer portion at the dielectric layer. At least part of the buffer layer portion of the hole has a larger cross-section area than a smallest cross-section area of the dielectric layer portion of the hole. The conformal barrier layer covers surfaces of the dielectric layer and the buffer layer in the hole. The hole is a via hole or a contact hole that is later filled with a conductive material to form a conductive via or a conductive contact.

Abstract: In a semiconductor device having a WCSP type construction package, to increase inductance without increasing further an area conventionally occupied by a coil. A pseudo-post part 27 comprising a magnetic body is extended in a direction perpendicular to a main surface 12a of a semiconductor chip 12, on a second insulating layer 21 of a WCSP 10. A first conductive part 15a and a second conductive part 15b constructed as square frames are respectively provided so as to surround the pseudo-post part, on respective top surfaces of a second insulation layer and a third insulating layer 22 which are separated parallel to each other, in an extension direction of the pseudo-post part. A coil 100 being a substantially spiral shape conductive path is formed from, the first conductive part, the second conductive part, and a connection part 26 which electrically connects the one ends of the first and second conductive parts.

Abstract: A semiconductor device comprises: a plurality of first wiring lines formed in a first layer with a first wiring width and a first wiring space; a plurality of second wiring lines formed in a second layer different from the above-described first layer with a second wiring width and a second wiring space larger than the above-described first wiring width and first wiring space; and a contact plug connecting the first wiring line and second wiring line. The above-described contact plug is formed over a plurality of adjacent ones of the above-described first wiring lines and has a pattern connecting the plurality of adjacent ones of the above-described first wiring lines and one of the above-described second wiring lines.

Abstract: A semiconductor device includes: a semiconductor substrate that has an integrated circuit; a plurality of electrodes that is formed on the semiconductor substrate, the plurality of the electrodes being electrically coupled to the integrated circuit; a passivation film that is formed on the semiconductor substrate, the passivation film having an opening on at least a part of one of the plurality of electrodes; a resin protrusion that is disposed on the passivation film; and a plurality of wiring lines that extend to a surface of the resin protrusion, each of the plurality of wiring lines extending from one of the plurality of the electrodes, a first portion of each of the plurality of wiring lines being positioned at an uppermost edge of the resin protrusion, a second portion of each of the plurality of wiring lines being positioned between one of the plurality of electrodes and the uppermost edge of the resin protrusion, a width of the first portion of each of the plurality of wiring lines being narrower than

Abstract: An efficient chip stacking structure is described that includes a leadframe having two surfaces to each of which can be attached stacks of chips. A chip stack can be formed by placing a chip active surface on a back surface of another chip. Electrical connections between chips and leads on the leadframe are facilitated by bonding pads on chip active surfaces and by via that extend from the bonding pads through the chips to the back surfaces.

Abstract: A metal layer structure of a semiconductor memory device is disclosed. The metal layer structure includes: a first metal layer to be connected to a contact plug; and a plurality of a second metal layers that are formed in parallel at a second spaced distance around the first metal layer, wherein a spaced distance of the second metal layers nearest the first metal layer maintains the second spaced distance which is wider than a first spaced distance of the second metal layers around the contact plug, and the spaced distance of the second metal layer next to the first metal layer maintains a third spaced distance, which is narrower than the second spaced distance, and the spaced distance between adjacent second metal layers gradually decreases to eventually be equal to the first spaced distance, for the second metal layers farthest from the first metal layer.

Abstract: An interconnection is provided with a dummy interconnection connected to an interconnection body, and the dummy interconnection is provided with a stress concentration portion in which tensile stress higher than that of the interconnection body is generated. In proximity to the stress concentration portion, an insulating film formed by high-density plasma CVD is provided, and the tensile stress is generated in the stress concentration portion by the insulating film. With this structure, the occurrence of a void can be prevented at any position in the interconnection body.

Abstract: A memory card comprising a leadframe having a plurality of contacts, at least one die pad, and a plurality of conductive traces extending from respective ones of the contacts toward the die pad. Also included in the leadframe are at least two bumpers. Attached to the die pad is a semiconductor die which is electrically connected to at least one of the traces. A body defining at least two corner regions at least partially encapsulates the leadframe and the semiconductor die such that the contacts are exposed in a bottom surface defined by the body, and the bumpers are located at respective ones of the corner regions thereof.

Abstract: A method includes forming a barrier layer on a substrate surface including at least one contact opening; forming an interconnect in the contact opening; and reducing the electrical conductivity of the barrier layer. A method including forming a barrier layer on a substrate surface including a dielectric layer and a contact opening, depositing a conductive material in the contact opening, removing the conductive material sufficient to expose the barrier layer on the substrate surface, and reducing the electrical conductivity of the barrier layer. An apparatus including a circuit substrate including at least one active layer including at least one contact point, a dielectric layer on the at least one active layer, a barrier layer on a surface of the dielectric layer, a portion of the barrier layer having been transformed from a first electrical conductivity to a second different and reduced electrical conductivity, and an interconnect coupled to the at least one contact point.

Abstract: The present invention relates to an electronic device incorporating a heat distributor. It applies more particularly to devices of the plastic package type, with one or more levels of components. According to the invention, the electronic device, for example of the package type, is provided for its external connection with pads distributed over a connection surface. It includes a thermally conducting plate lying parallel to said connection surface and having a nonuniform structure making it possible, when the device is exposed to a given external temperature, to supply a controlled amount of heat to each external connection pad according to its position on the connection surface. If the device is a package comprising a support of the printed circuit type, the conducting plate will advantageously form an internal layer of said support.

Abstract: A method of manufacturing a film printed circuit board is provided. A film substrate consisting of a polyimide substrate, an alloy layer and a first copper layer is provided. A first lithographic and etching process is performed to pattern the copper layer and the alloy layer and a plurality of conductive line structures is formed on the polyimide substrate. A second copper layer is formed over the polyimide substrate and the conductive line structures. A second lithographic and etching process is performed to pattern the second copper layer.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a first floating gate formed on a main surface of the semiconductor substrate, a second floating gate formed on the main surface of the semiconductor substrate, a first control gate formed on the first floating gate, a second control gate formed on the second floating gate, an interlayer insulating film, and a gap formed in the interlayer insulating film in at least a portion located between the first and second floating gates. Accordingly, a nonvolatile semiconductor memory device for which variations in threshold voltage of a memory cell can be suppressed and an appropriate read operation can be carried out, as well as a method of manufacturing the nonvolatile semiconductor memory device are provided. Further, a capacitance formed between interconnect lines can be reduced and the drive speed can be improved.

Abstract: There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of a semiconductor device. A semiconductor chip includes a power transistor formation region to form a power transistor, a logic circuit formation region to form a logic circuit, and an analog circuit formation region to form an analog circuit. A pad is formed in the power transistor formation region. The pad and a lead are connected through a clip whose cross-section is larger than that of a wire. On the other hand, a bonding pad is connected through the wire 29.

Abstract: The semiconductor device fabrication method according the present invention having, forming an interlayer dielectric film containing carbon above a semiconductor substrate, forming a protective film on that portion of the interlayer dielectric film, which is close to the surface and in which the carbon concentration is low, forming a trench by selectively removing a desired region of the interlayer dielectric film and protective film, such that the region extends from the surface of the protective film to the bottom surface of the interlayer dielectric film, supplying carbon to the interface between the interlayer dielectric film and protective film, and forming a conductive layer by burying a conductive material in the trench.

Abstract: An anisotropically conductive member has an insulating base material, and conductive paths composed of a conductive material which pass in a mutually insulated state through the insulating base material in a thickness direction thereof and which are provided in such a way that a first end of each conductive path is exposed on a first side of the insulating base material and a second end of each conductive path is exposed on a second side of the insulating base material. The conductive paths have a density of at least 2 million paths/mm2 and the insulating base material is a structure composed of an anodized aluminum film having micropores therein.

Abstract: A semiconductor structure and methods for forming the same. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

Abstract: A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect near the via.

Abstract: A metal interconnect structure includes a plurality of first plugs adjacent to each other, a first metal line extending in a first direction and contacting each first plug to form a first section with a tapered second section in between, and a second plug adjacent to the second section, both in a second direction normal to the first direction.

Abstract: A semiconductor device capable of reducing electrical leakage generated when a contact hole is misaligned and a manufacturing method thereof is disclosed. The semiconductor device includes three conductive layers with various and different portions overlapping each other. The conductive layers are separated by insulating layers and connected by contact holes formed in the insulating layers between the overlapping potions. Thus, electric leakage, caused by misalignment when forming the contact hole to electrically connect the conductive layers to each other, can be prevented.

Abstract: A semiconductor integrated circuit, including an input/output cell including signal terminals, wherein the signal terminal of the input/output cell is connected to an internal circuit via an interconnect wiring. The signal terminal of the I/O cell includes a plurality of (e.g., four) conductive layers. Each pair of adjacent ones of the plurality of conductive layers are connected together by a via. One of the plurality of conductive layers to which a via of the largest diameter is connected (e.g., the fourth conductive layer) is formed with a width such that only one of the largest-diameter via can be accommodated. Therefore, it is possible to suppress the migration of atoms from the interconnect wiring to the input terminal of the I/O cell, and to suppress the open failure of the via formed on the interconnect wiring.

Abstract: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component, at least two leads, and at least two bond wires. Each of the leads may have a reduced-thickness inner length adjacent terminals of the microelectronic component and a body having an outer surface spaced farther from the microelectronic component than a bond surface of the inner length. Each of the bond wires couples the microelectronic component to one of the leads and has a maximum height outwardly from the microelectronic component that is no greater than the height of the outer surface of the lead.

Abstract: In a film substrate (FB) including a film base material (1) and conductor wiring (23) that is formed on the film base material (1), the conductor wiring (23) is arranged such that the conductor wiring thickness of an external connection portion on the film substrate to which another panel or substrate is connected is thicker than the conductor wiring thickness of conductor wiring portions (bent portions) (25) at other positions.

Abstract: To provide a technique for manufacturing a wiring line having a low resistance and a high heat resistance so as to make an active matrix type display device larger and finer. The wiring line is constructed of a laminated structure of a refractory metal, a low resistance metal and a refractory metal, and the wiring line is further protected with an anodized film. As a result, it is possible to form the wiring line having the low resistance and the high heat resistance and to form a contact with an upper line easily.

Abstract: A semiconductor chip including a substrate, a metal interconnection structure and a circuit region is provided. The substrate has at least one dielectric ring on a substrate surface of the substrate. The metal interconnection structure is disposed on the substrate surface and has at least one guard ring, wherein the guard ring comprises a plurality of individual segments, and the individual segments are individually and electrically coupled to the ground contacts. The circuit region disposed on the substrate. A projection of the dielectric ring on the substrate surface surrounds a projection of the circuit region on the substrate surface, and the projection of the guard ring on the substrate surface surrounds that of the dielectric ring and that of the circuit region on the substrate surface.

Abstract: A circuit board includes at least one trace having at least one heat spreader disposed thereon, the heater spreader being formed of a solidified paste, such as a paste that includes a mixture of binder particles and filler particles, or a solder paste. As an example, the heater spreader may be configured to increase a cross-sectional area of a portion of the trace, thereby improving heat flow along that portion of the trace. Alternatively, the heater spreader may be configured to increase the surface area of the trace, thereby increasing heat dissipation from the circuit board. As another example, the heat spreader may be disposed between the trace and a semiconductor device and thereby function as a heat sink for the device.

Abstract: In the BGA package and its manufacturing method, a bonding pad is etched from the exposed surface to a part of the insulation layer-coated region so as to form a solder contact side having a dish configuration, which is planar at a bottom center and slanted at a periphery. With this bent structure of the dish configuration, the bonding pad provides an increased bonding area for the solder, so that the BGA package substrate is enhanced in reliability.

Abstract: The present invention provides a printed circuit board having an area of non-resist portion, where each non-resist portion expands gradually toward the back end of a land array in the dipping direction A. Thus the area of solder deposition also expands in the region of the land array, thereby excessive solder does not remain up to the back end of the land array, and resultantly the amount of solder buildup at the backside in the dipping direction A can be reduced. Further, the present invention makes it unnecessary to dispose a dummy land for the prevention of solder buildup at the backmost portion of the land array, and thus the space used for a dummy land can be utilized effectively.

Abstract: A device is disclosed with at least one electrically insulating layer on which at least one conductor structure made of electrically conductive material is placed. In at least one embodiment, the conductor structure on the side facing the insulating layer has at least one elevation that is accommodated in at least one recess in the insulating layer.

Abstract: A structure for improving the electrostatic discharge robustness of an integrated circuit having an electrostatic discharge (ESD) device and a receiver network connected to a pad by interconnects. The interconnect between the pad and the ESD device has a high-k material placed adjacent to at least one surface of the interconnect and extending over the thermal diffusion distance of the interconnect. The high-k material improves the critical current density of the interconnect by increasing the heat capacity and thermal conductivity of the interconnect. The high-k material can be placed on the sides, top and/or bottom of the interconnect. In multiple wire interconnects, the high-k material is placed between the wires of the interconnect. A low-k material is placed beyond the high-k material to reduce the capacitance of the interconnect. The combination of low-k and high-k materials provides an interconnect structure with improved ESD robustness and low capacitance that is well suited for an ESD device.

Abstract: A display device includes a display panel, and the circuit substrate is separately formed and positioned different from the array substrate of the display panel and connected to the display panel. The circuit substrate includes an insulating substrate, a conductive layer, an insulating layer to cover a part of the conductive layer, a plating layer applied to a portion of the conductive layer which is exposed from the insulating layer due to misalignment between the conductive layer and the insulating layer, and a misalignment detection pattern for detecting the misalignment between the conductive layer and the insulating layer. The misalignment detection pattern has a pattern covered by the insulating layer in a manner to prevent adherence of a plating material to the conductive layer, if the misalignment between the conductive layer and the insulating layer is smaller than a predetermined misalignment tolerance.

Abstract: An apparatus comprising an insulating substrate having first and second surfaces and a plurality of metal-filled vias extending from the first to the second surface. The first and second surfaces have contact pads, each one comprising a connector stack to at least one of the vias. The stack comprises a seed metal layer in contact with the via metal capable of providing an adhesive and conductive layer for electroplating on its surface, a first electroplated support layer secured to the seed metal layer, a second electroplated support layer, and at least one reflow metal bonding layer on the second support layer. The electrolytic plating process produces support layers substantially pure (at least 99.0%), free of unwanted additives such as phosphorus or boron, and exhibiting closely controlled grain sizes. Reflow metal connectors provide attachment to chip contact pads and external parts.

Abstract: A circuit board includes a film substrate, a plurality of wiring layers arranged in order on the film substrate, and bumps formed on the wiring layers, respectively. Each of the bumps is provided across a longitudinal direction of a corresponding one of the wiring layers so as to extend over regions on both sides of the wiring layer above the insulating substrate, and a cross sectional shape of the bump taken in the width direction of the wiring layer is such that a central portion is higher than portions on both sides of the central portion. Accordingly, the bumps formed on the wiring layers can be held with strength sufficient for practical use against the force applied in the lateral direction.

Abstract: Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the length of the inductor (5).

Abstract: A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window to define the sidewalls of the contact window.

Abstract: Methods of forming a microelectronic device and associated structures are described. Those methods may comprise forming a die-side conductive interconnect on a substrate, wherein the die-side conductive interconnect comprises a columnar portion and a base portion, and wherein a diameter of the base portion is greater than a diameter of the columnar portion.

Abstract: A semiconductor device has a plurality of bumps in a same row for staggered probing. The bumps in a same row are disposed on a chip and include a plurality of regular bumps and a plurality of irregular bumps. The regular bumps and the irregular bumps are interspersed in a same pitch. Along a defined line, the widths of the irregular bumps are narrower than the ones of the regular bumps for fine pitch applications. Additionally, the irregular bumps have a plurality of integral probed portions far away the line, top surfaces of which are expanded such that probed points can be defined on the probed portions for staggered probing.

Abstract: Disclosed are tapered dielectric and conductor structures which provide controlled impedance interconnection while signal conductor lines transition from finer pitches to coarser pitches thereby obviating electrical discontinuities generally associated with changes of circuit contact pitch. Also disclosed are methods for the construction of the devices and applications therefore.

Abstract: Provided are a semiconductor package in which bonding pads of a semiconductor chip are electrically connected to interconnection portions by wire-bonding, and a method of manufacturing the semiconductor package. The semiconductor package includes: a substrate; an interconnection portion that is disposed on the substrate and comprises conductive patterns having a first thickness and conductive patterns having a second thickness that is smaller than the first thickness; at least one semiconductor chip that is mounted on the substrate and comprises a plurality of bonding pads; and a plurality of wires electrically connecting the conductive patterns and the bonding pads.

Abstract: A semiconductor device is provided. The semiconductor device includes a region of closely packed lines and a region including an isolated line, separated by a region of carbon doped silicon oxide. As the surface of the semiconductor device is etched, the etching rate varies depending on the material being etched. Accordingly, the cross-sectional area of the isolated line must be adjusted to compensate for the slowed etching process in that region. The close packed lines may have a height, a, and a width, b thus having a cross-sectional area of a*b. However, the isolated line may have a height D*a, and a width, E*b, where D*E=1. Singular or multiple etching processes may used and the line widths adjusted accordingly.

Abstract: A solid-state imaging device comprises a housing in which a base and ribs forming a rectangular frame are formed in one piece by a resin; a plurality of metal lead pieces embedded in the housing, each of which has an internal terminal portion facing an internal space of the housing and an external terminal portion exposed at an outer portion of the housing; an imaging element arranged on the base in the internal space of the housing; connecting members connecting electrodes of the imaging element to the internal terminal portions of the metal lead pieces; and a transparent plate fastened to an upper face of the ribs. The upper face of the ribs is provided with a lower step portion that is lowered along an external periphery, and the transparent plate is fastened to the upper face of the ribs by an adhesive filled at least into the lower step portion.