Manufacture Or Treatment Of Semiconductor Device (epo) Patents (Class 257/E21.002)

  • Patent number: 8933521
    Abstract: A device including at least two spintronic devices and a method of making the same. A magnetic connector extends between the two spintronic devices to conduct a magnetization between the two. The magnetic connector may further be disposed to conduct current to switch a magnetization of one of the two spintronic devices.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: January 13, 2015
    Assignee: Intel Corporation
    Inventors: Dmitri E. Nikonov, Ian A. Young
  • Patent number: 8932893
    Abstract: A method of fabricating a microelectromechanical (MEMS) device includes bonding a transducer wafer to a substrate wafer along a bond interface. An unpatterned transducer layer included within the transducer wafer is patterned. A release etch process is then performed during which a sacrificial layer is exposed to a selected release etchant to remove at a least a portion of the sacrificial layer through the openings in the patterned transducer layer. A release etch stop layer is formed between the sacrificial layer and the bond interface prior to exposing the sacrificial layer to the release etchant. The release etch stop layer prevents the ingress of the selected release etchant into the region of the MEMS device containing the bond interface during the release etch process.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: January 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Matthieu Lagouge
  • Patent number: 8921962
    Abstract: A magnetostrictive-piezoelectric multiferroic single- or multi-domain nanomagnet whose magnetization can be rotated through application of an electric field across the piezoelectric layer has a structure that can include either a shape-anisotropic mangnetostrictive nanomagnet with no magnetocrystalline anisotropy or a circular nanomagnet with biaxial magnetocrystalline anisotropy with dimensions of nominal diameter and thickness. This structure can be used to write and store binary bits encoded in the magnetization orientation, thereby functioning as a memory element, or perform both Boolean and non-Boolean computation, or be integrated with existing magnetic tunneling junction (MTJ) technology to perform a read operation by adding a barrier layer for the MTJ having a high coercivity to serve as the hard magnetic layer of the MTJ, and electrical contact layers of a soft material with small Young's modulus.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: December 30, 2014
    Assignee: Virginia Commonwealth University
    Inventors: Jayasimha Atulasimha, Supriyo Bandyopadhyay
  • Patent number: 8921213
    Abstract: An object of the present invention is to amplify the current which varies by a factor of several orders of magnitude with a constant gain without using a complicated circuit. In order to solve the problem, with a semiconductor device includes a first semiconductor region of a first conductivity, a second semiconductor region which is an opposite conductivity opposite to the first conductivity and is in contact with the first semiconductor region and a third semiconductor region which is the first conductivity and is in contact with the second semiconductor region at the second surface, a fourth semiconductor region in contact with the second semiconductor region is provided so as to be separated from the third semiconductor region and enclose the third semiconductor region and an impurity concentration of the fourth semiconductor region is larger than that of the second semiconductor region.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: December 30, 2014
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Yutaka Hayashi, Yasushi Nagamune, Toshitaka Ota
  • Patent number: 8921145
    Abstract: A micro-electro-mechanical systems (MEMS) device and method for forming a MEMS device is provided. A proof mass is suspended a distance above a surface of a substrate by a fulcrum. A pair of sensing plates are positioned on the substrate on opposing sides of the fulcrum. Metal bumps are associated with each sensing plate and positioned near a respective distal end of the proof mass. Each metal bump extends from the surface of the substrate and generally inhibits charge-induced stiction associated with the proof mass. Oxide bumps are associated with each of the pair of sensing plates and positioned between the respective sensing plate and the fulcrum. Each oxide bump extends from the first surface of the substrate a greater distance than the metal bumps and acts as a shock absorber by preventing the distal ends of the proof mass from contacting the metal bumps during shock loading.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Pao Shu, Kelvin Tai, Calvin Hung, Benior Chen
  • Patent number: 8916847
    Abstract: A variable resistance memory device includes a plurality of first conductive lines extended in a first direction, a plurality of second conductive lines arranged over or under the first conductive lines and extended in a second direction crossing the first direction, an insulating layer disposed between the first conductive lines and the second conductive lines and having a trench extended in the second direction and defined by a first side wall and a second sidewall facing each other and a bottom surface connecting the first sidewall and the second sidewall, and a variable resistance material layer formed on the first and second sidewalls and the bottom surface of the trench, wherein the first and second sidewalls of the trench overlap two adjacent second conductive lines, respectively.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: December 23, 2014
    Assignee: SK Hynix Inc.
    Inventors: Hyun-Min Lee, Jung-Taik Cheong
  • Patent number: 8912556
    Abstract: A light emitting device and a method of manufacturing the same are disclosed. The light emitting device includes a buffer layer formed on a substrate, a nitride semiconductor layer including a first semiconductor layer, an active layer, and a second semiconductor layer, which are sequentially stacked on the buffer layer, a portion of the first semiconductor layer being exposed to the outside by performing mesa etching from the second semiconductor layer to the portion of the first semiconductor layer, and at least one nanocone formed on the second semiconductor layer.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: December 16, 2014
    Assignees: LG Electronics Inc., LG Innotek Co., Ltd.
    Inventors: Jong Wook Kim, Hyun Kyong Cho, Gyu Chul Yi, Sung Jin An, Jin Kyoung Yoo, Young Joon Hong
  • Patent number: 8907285
    Abstract: A pyroelectric detector includes a pyroelectric detection element, a support member, a fixing part and a first reducing gas barrier layer. A first side of the support member faces a cavity and the pyroelectric detection element is mounted and supported on a second side opposite from the first side. An opening part communicated with the cavity is formed on a periphery of the support member in plan view from the second side of the support member. The fixing part supports the support member. The first reducing gas barrier layer covers a first surface of the support member on the first side, a side surface of the support member facing the opening part, and a part of a second surface of the support member on the second side and the pyroelectric detection element exposed as viewed from the second side of the support member.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: December 9, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Takafumi Noda, Jun Takizawa
  • Patent number: 8907434
    Abstract: A MEMS inertial sensor and a method for manufacturing the same are provided. The method includes: depositing a first carbon layer on a semiconductor substrate; patterning the first carbon layer to form a fixed anchor bolt, an inertial anchor bolt and a bottom sealing ring; forming a contact plug in the fixed anchor bolt and a contact plug in the inertial anchor bolt; forming a first fixed electrode, an inertial electrode and a connection electrode on the first carbon layer, where the first fixed electrode and the inertial electrode constitute a capacitor; forming a second carbon layer on the first fixed electrode and the inertial electrode; and forming a sealing cap layer on the second carbon layer and the top sealing ring. Under an inertial force, only the inertial electrode may move, the fixed electrode will almost not move or vibrate, which improves the accuracy of the MEMS inertial sensor.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: December 9, 2014
    Assignee: Lexvu Opto Microelectronics Technology (Shanghai) Ltd.
    Inventors: Zhiwei Wang, Deming Tang, Lei Zhang, Jianhong Mao, Fengqin Han
  • Patent number: 8906706
    Abstract: A method of fabricating workpieces includes one or more layers on a substrate that are masked with an ion implantation mask comprising two or more layers. The mask layers include a first mask layer closer to the substrate, and a second mask layer on the first mask layer. The method also comprises ion implanting one or more of the layers on the substrate. Ion implantation may form portions with altered physical properties from the layers under the mask. The portions may form a plurality of non-magnetic regions corresponding to apertures in the mask.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: December 9, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Kanaiyalal C. Patel, Kurt A. Rubin
  • Patent number: 8900902
    Abstract: Provided is a producing of a surface-emitting laser capable of aligning a center axis of a surface relief structure with that of a current confinement structure with high precision to reduce a surface damage during the producing. The producing of the laser having the relief provided on a laminated semiconductor layer and a mesa structure, the process comprising the steps of: forming, on the layer, one of a first dielectric film and a first resist film having a first pattern for defining the mesa and a second pattern for defining the relief and then forming the other one of the films; forming a second resist film to cover the second pattern and expose the first pattern; and forming the mesa by removing the layer under the first pattern using the second resist film.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: December 2, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tatsuro Uchida
  • Patent number: 8901555
    Abstract: A light sensing device is disclosed. The light sensing device includes a first light sensor and a second light sensor. The first light sensor formed on a substrate includes a first metal oxide semiconductor layer for absorbing a first light having a first waveband. The second light sensor formed on the substrate includes a second metal oxide semiconductor layer and an organic light-sensitive layer on the second metal oxide semiconductor layer for absorbing a second light having a second waveband.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: December 2, 2014
    Assignee: E Ink Holdings Inc.
    Inventors: Chia-Chun Yeh, Henry Wang, Wei-Chou Lan, Ted-Hong Shinn
  • Patent number: 8900906
    Abstract: In one embodiment, a method of forming a semiconductor device includes providing a substrate, forming a sacrificial layer above the substrate layer, forming a first trench in the sacrificial layer, forming a first sidewall layer with a thickness of less than about 50 nm on a first sidewall of the first trench using atomic layer deposition (ALD), and removing the sacrificial layer.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: December 2, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Gary Yama, Fabian Purkl, Matthieu Liger, Matthias Illing
  • Patent number: 8895342
    Abstract: Inverted metamorphic multijunction solar cells having a heterojunction middle subcell and a graded interlayer, and methods of making same, are disclosed herein. The present disclosure provides a method of manufacturing a solar cell using an MOCVD process, wherein the graded interlayer is composed of (InxGa1-x)yAl1-yAs, and is formed in the MOCVD reactor so that it is compositionally graded to lattice match the middle second subcell on one side and the lower third subcell on the other side, with the values for x and y computed and the composition of the graded interlayer determined so that as the layer is grown in the MOCVD reactor, the band gap of the graded interlayer remains constant at 1.5 eV throughout the thickness of the graded interlayer.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: November 25, 2014
    Assignee: Emcore Solar Power, Inc.
    Inventors: Mark A. Stan, Arthur Cornfeld
  • Patent number: 8889017
    Abstract: The present invention relates to a method for producing silicon waveguides on non-SOI substrate (non-silicon-on-insulator substrate), and particularly relates to a method for producing silicon waveguides on silicon substrate with a laser. This method includes the following steps: (1) forming a ridge structure with high aspect ratio on a non-SOI substrate; (2) melting and reshaping the ridge structure by laser illumination for forming a structure having broad upper part and narrow lower part; and (3) oxidizing the structure having broad upper part and narrow lower part to form a silicon waveguide.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: November 18, 2014
    Assignee: National Taiwan University
    Inventors: Ching-Fuh Lin, Shih-Che Hung, Shu-Jia Syu
  • Patent number: 8878314
    Abstract: A MEMS device structure including a lateral electrical via encased in a cap layer and a method for manufacturing the same. The MEMS device structure includes a cap layer positioned on a MEMS device layer. The cap layer covers a MEMS device and one or more MEMS device layer electrodes in the MEMS device layer. The cap layer includes at least one cap layer electrode accessible from the surface of the cap layer. An electrical via is encased in the cap layer extending across a lateral distance from the cap layer electrode to the one or more MEMS device layer electrodes. An isolating layer is positioned around the electrical via to electrically isolate the electrical via from the cap layer.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: November 4, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Andrew B. Graham, Gary Yama, Gary O'Brien
  • Patent number: 8878313
    Abstract: A pressure sensor has a sensor body at least partly formed with an electrically insulating material, particularly a ceramic material, defining a cavity facing on which is a diaphragm provided with an electric detector element, configured for detecting a bending of the diaphragm. The sensor body supports a circuit arrangement, including, a plurality of circuit components, among which is an integrated circuit, for treating a signal generated by the detection element. The circuit arrangement includes tracks made of electrically conductive material directly deposited on a surface of the sensor body made of electrically insulating material. The integrated circuit is made up of a die made of semiconductor material directly bonded onto the surface of the sensor body and the die is connected to respective tracks by means of wire bonding, i.e. by means of thin connecting wires made of electrically conductive material.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: November 4, 2014
    Assignee: Metallux SA
    Inventor: Luca Salmaso
  • Patent number: 8872339
    Abstract: A structure includes a substrate, a first supporting member over the substrate, a second supporting member over the substrate, and a layer of material over the substrate and covering the first supporting member and the second supporting member. The first supporting member has a first width, and the second supporting member has a second width. The first supporting member and the second supporting member are separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region ranges from 5 to 30 times the second width.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chu Liu, Yi-Shien Mor, Kuei Shun Chen, Yu Lun Liu, Han-Hsun Chang, Shiao-Chian Yeh
  • Patent number: 8866237
    Abstract: An embedded micro-electro-mechanical system (MEMS) (100) comprising a semiconductor chip (101) embedded in an insulating board (120), the chip having a cavity (102) including a radiation sensor MEMS (105), the opening (104) of the cavity at the chip surface covered by a plate (110) transmissive to the radiation (150) sensed by the MEMS. The plate surface remote from the cavity having a bare central area, to be exposed to the radiation sensed by the MEMS in the cavity, and a peripheral area covered by a metal film (111) touching the plate surface and a layer (112) of adhesive stacked on the metal film.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: October 21, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Christopher D. Manack, Frank Stepniak, Sreenivasan K. Koduri
  • Patent number: 8865554
    Abstract: A method for fabricating a nonvolatile memory device includes forming a structure having a plurality of first interlayer insulating layers and a plurality of sacrificial layers alternately stacked over a substrate, forming main channel holes configured to penetrate the structure, sequentially forming a preliminary charge trap layer, a tunnel insulating layer, and a channel layer on the inner walls of the main channel holes, forming a trench configured to penetrate the plurality of sacrificial layers on both sides of each of the main channel holes, and forming insulating oxide layers by oxidizing the preliminary charge trap layer on inner sides of the first interlayer insulating layers. In accordance with this technology, since the charge trap layer is separated for each memory cell, the spread of charges may be prevented and the reliability of a nonvolatile memory device may be improved.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: October 21, 2014
    Assignee: SK Hynix Inc.
    Inventor: Hyun-Sik Doo
  • Patent number: 8866243
    Abstract: For the present ferromagnetic tunnel junction structure, employed is a means characterized by using an MgO barrier and using a Co2FeAl full-Heusler alloy for any of the ferromagnetic layers therein. The ferromagnetic tunnel junction structure is characterized in that Co2FeAl includes especially a B2 structure and one of the ferromagnetic layers is formed on a Cr buffer layer. The magnetoresistive element is characterized in that the ferromagnetic tunnel junction structure therein is any of the above-mentioned ferromagnetic tunnel junction structure. Accordingly, a large TMR, especially a TMR over 100% at room temperature can be attained, using Co2FeAl having a smallest ? though not a half-metal.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: October 21, 2014
    Assignee: National Institute for Materials Science
    Inventors: Koichiro Inomata, Wenhong Wang, Hiroaki Sukegawa
  • Patent number: 8860157
    Abstract: An apparatus and associated method for a non-volatile memory cell with a phonon-blocking insulating layer. In accordance with various embodiments, a magnetic stack has a tunnel junction, ferromagnetic free layer, pinned layer, and an insulating layer that is constructed of an electrically and thermally insulative material that blocks phonons while allowing electrical transmission through at least one conductive feature.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 14, 2014
    Assignee: Seagate Technology LLC
    Inventors: Yuankai Zheng, Xiaohua Lou, Wei Tian, Zheng Gao, Haiwen Xi
  • Patent number: 8853521
    Abstract: The present disclosure presents a partially-transparent (see-through) three-dimensional thin film solar cell (3-D TFSC) substrate. The substrate includes a plurality of unit cells. Each unit cell structure has the shape of a truncated pyramid, and its parameters may be varied to allow a desired portion of sunlight to pass through.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: October 7, 2014
    Assignee: Solexel, Inc.
    Inventors: Mehrdad Moslehi, David Xuan-Qi Wang
  • Patent number: 8853801
    Abstract: A device includes a substrate, a routing conductive line over the substrate, a dielectric layer over the routing conductive line, and an etch stop layer over the dielectric layer. A Micro-Electro-Mechanical System (MEMS) device has a portion over the etch stop layer. A contact plug penetrates through the etch stop layer and the dielectric layer. The contact plug connects the portion of the MEMS device to the routing conductive line. An escort ring is disposed over the etch stop layer and under the MEMS device, wherein the escort ring encircles the contact plug.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Ying Tsai, Jung-Huei Peng, Hsin-Ting Huang, Yao-Te Huang, Lung Yuan Pan, Hung-Hua Lin
  • Patent number: 8853730
    Abstract: A light emitting device comprises a substrate including a top surface that is flat, a light emitting diode on the substrate, a lead frame formed on the flat top surface of the substrate. The lead frame includes a circuit with a predetermined pattern to electrically connect to the light emitting diode. A dam part is formed on the substrate and is adjacent to the light emitting diode. A first member is formed on the light emitting diode, the first member including a fluorescent substance to convert a light emission spectrum of light from the light emitting diode. A second member is surrounded by the dam part and is formed on the substrate adjacent to the first member, and a lens covers the first member, the second member and the light emitting diode.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: October 7, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Bo Geun Park
  • Patent number: 8836056
    Abstract: Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: September 16, 2014
    Assignee: Intel Corporation
    Inventors: Kaan Oguz, Mark L. Doczy, Brian Doyle, Uday Shah, David L. Kencke, Roksana Golizadeh Mojarad, Robert S. Chau
  • Patent number: 8836079
    Abstract: Metal-on-Metal (MoM) capacitors having laterally displaced layers and related systems and methods are disclosed. In one embodiment, a MoM capacitor includes a plurality of vertically stacked layers that are laterally displaced relative to one another. Lateral displacement of the layers minimizes cumulative surface process variations making a more reliable and uniform capacitor.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: September 16, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Bin Yang
  • Patent number: 8836061
    Abstract: A spin transfer torque magnetic random access memory (STTMRAM) magnetic tunnel junction (MTJ) stack includes layers to which when electric current is applied cause switching of the direction of magnetization of at least one of the layer. The STTMRAM MTJ stack includes a reference layer (RL) with a direction of magnetization that is fixed upon manufacturing of the STTMRAM MTJ stack, a junction layer (JL) formed on top of the RL, a free layer (FL) formed on top of the JL. The FL has a direction of magnetization that is switchable relative to that of the RL upon the flow of electric current through the spin transfer torque magnetic random access memory (STTMRAM) magnetic tunnel junction (MTJ) stack. The STTMRAM MTJ stack further includes a spin confinement layer (SCL) formed on top of the FL, the SCL made of ruthenium.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: September 16, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Yuchen Zhou, Yiming Huai, Zihui Wang, Dong Ha Jung
  • Patent number: 8828773
    Abstract: A method of forming a microphone forms a backplate, and a flexible diaphragm on at least a portion of a wet etch removable sacrificial layer. The method adds a wet etch resistant material, where a portion of the wet etch resistant material is positioned between the diaphragm and the backplate to support the diaphragm. Some of the wet etch resistant material is not positioned between the diaphragm and backplate. The method then removes the sacrificial material before removing any of the wet etch resistant material added during the prior noted act of adding. The wet etch resistant material then is removed substantially in its entirety after removing at least part of the sacrificial material.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: September 9, 2014
    Assignee: Invensense, Inc.
    Inventor: Jason W. Weigold
  • Patent number: 8826529
    Abstract: A device includes a substrate (308) and a metallic layer (336) formed over the substrate (308) with a deposition process for which the metallic layer (336) is characterizable as having a pre-determinable as-deposited defect density. As a result of a fabrication process, the defect density of the metallic layer (336) is reduced relative to the pre-determinable as-deposited defect density of the same layer (336) or another layer having like composition and which is formed under like deposition conditions. In a related method, a substrate (308) is provided and a removable layer (330) is formed over the substrate (308). A metallic layer (336) is formed over the removable layer (330) and is patterned and etched to define a structure over the removable layer (330). The removable layer (330) is removed, and the metallic layer (336) is heated for a time beyond that necessary for bonding of a hermetic sealing cap (340) thereover.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: September 9, 2014
    Assignee: General Electric Company
    Inventors: Andrew Joseph Detor, Reed Corderman, Christopher Keimel, Marco Aimi
  • Patent number: 8823117
    Abstract: The present disclosure provides for magnetic devices and methods of fabricating such a device. In one embodiment, a magnetic device includes a first elliptical pillar of first material layers; a second elliptical pillar concentrically disposed over the first elliptical pillar, the second elliptical pillar includes second material layers. The second elliptical pillar is smaller than the first elliptical pillar in size.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chewn Yu, Tien-Wei Chiang, Kai-Wen Cheng
  • Patent number: 8822978
    Abstract: An electronic structure comprising: (a) a first metal layer; (b) a second metal layer; (c) and at least one insulator layer located between the first metal layer and the second metal layer, wherein at least one of the metal layers comprises an amorphous multi-component metallic film. In certain embodiments, the construct is a metal-insulator-metal (MIM) diode.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: September 2, 2014
    Assignee: The State of Oregon Acting by and through...
    Inventors: E. William Cowell, III, John F. Wager, Brady J. Gibbons, Douglas A. Keszler
  • Patent number: 8815623
    Abstract: A differential pressure sensor comprises a membrane arranged over a cavity on a semiconductor substrate. A lid layer is arranged at the top side of the device and comprises an access opening for providing access to the top side of the membrane. A channel extends laterally from the cavity and intersects with a bore. The bore is formed by laser drilling from the bottom side of the substrate and provides access to the bottom side of the membrane. The bore extends all through the substrate and optionally into the lid layer.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: August 26, 2014
    Assignee: Sensirion AG
    Inventors: Johannes Bühler, Felix Mayer, Matthias Streiff, René Hummel, Robert Sunier
  • Patent number: 8817559
    Abstract: Such a device is disclosed that includes: redundancy circuits for replacing defective memory cells included in a memory cell array; an electrical fuse circuit that stores addresses of the defective memory cells; a data determination circuit that generates a determination signal by determining whether test data read from the memory cell array is correct or incorrect; and an analysis circuit that supplies, in a first operation mode, the electrical fuse circuit with an address signal supplied when the determination signal is activated, and supplies, in a second operation mode, the electrical fuse circuit with an address signal supplied when a data mask signal supplied from outside is activated irrespective of the determination signal.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: August 26, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Akira Ide, Shinji Furumi
  • Patent number: 8809095
    Abstract: A micromechanical component having a substrate, a micromechanical functional layer situated above the substrate, and an encapsulation layer situated above the functional layer, and a method for producing the micromechanical component are provided, the encapsulation layer having at least one trench, and a bridging of the trench by at least one electrically insulating connection link is provided.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: August 19, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Volker Schmitz, Axel Grosse
  • Patent number: 8803264
    Abstract: The invention provides a novel class of room-temperature, single-phase, magnetoelectric multiferroic (PbFe0.67W0.33O3)x (PbZr0.53Ti0.47O3)1-x (0.2?x?0.8) (PFWx?PZT1-x) thin films that exhibit high dielectric constants, high polarization, weak saturation magnetization, broad dielectric temperature peak, high-frequency dispersion, low dielectric loss and low leakage current. These properties render them to be suitable candidates for room-temperature multiferroic devices. Methods of preparation are also provided.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: August 12, 2014
    Assignee: University of Puerto Rico
    Inventors: Ram S Katiyar, Ashok Kumar, James F Scott
  • Patent number: 8803323
    Abstract: A device includes a first package component and the second package component. The first package component includes a first plurality of connectors at a top surface of the first package component, and a second plurality of connectors at the top surface. The second package component is over and bonded to the first plurality of connectors, wherein the second plurality of connectors is not bonded to the second package component. A solder resist is on the top surface of the first package component. A trench is disposed in the solder resist, wherein a portion of the trench spaces the second plurality of connectors apart from the first plurality of connectors.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jiun Yi Wu, Tsung-Ding Wang
  • Patent number: 8785914
    Abstract: A piezoelectric nanowire structure includes a base substrate, a plurality of piezoelectric nanowires disposed on the base substrate, and a piezoelectric organic material layer disposed on the base substrate and covering the plurality of piezoelectric nanowires.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: July 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Duk-Hyun Choi, Jae-Young Choi
  • Patent number: 8785924
    Abstract: Disclosed are a high-sensitivity transparent gas sensor and a method for manufacturing the same. The transparent gas sensor includes a transparent substrate, a transparent electrode formed on the transparent substrate and a transparent gas-sensing layer formed on the transparent electrode. The transparent gas-sensing layer has a nanocolumnar structure having nanocolumns formed on the transparent electrode and gas diffusion pores formed between the nanocolumns.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: July 22, 2014
    Assignee: Korea Institute of Science and Technology
    Inventors: Ho Won Jang, Seok Jin Yoon, Jin Sang Kim, Chong Yun Kang, Ji Won Choi, Hi Gyu Moon
  • Patent number: 8779531
    Abstract: A microelectromechanical system (MEMS) assembly includes at least one emission source; a top wafer having a plurality of side walls and a generally horizontal portion, the horizontal portion having a thickness between a first side and a directly opposed second side, at least one window in the horizontal portion extending between the first and second sides and a transmission membrane across the at least one window; and a bottom wafer having a first portion with a first substantially planar surface, an intermediate surface directly opposed to the first substantially planar surface, a second portion with a second substantially planar surface, the at least one emission source provided on the second substantially planar surface; where the top wafer bonds to the bottom wafer at the intermediate surface and encloses a cavity within the top wafer and the bottom wafer.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: July 15, 2014
    Assignee: UTC Fire & Security Corporation
    Inventors: Joseph V. Mantese, Antonio M. Vincitore
  • Patent number: 8765565
    Abstract: According to one embodiment, a nonvolatile memory device includes a selection element layer and a nanomaterial aggregate layer. The selection element layer includes silicon. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer includes a plurality of micro conductive bodies and fine particles dispersed in a plurality of gaps between the micro conductive bodies. At least a surface of the fine particle is made of an insulating material other than silicon oxide.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: July 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Aoyama, Kazuhiko Yamamoto, Satoshi Ishikawa, Shigeto Oshino
  • Patent number: 8754491
    Abstract: An apparatus is provided for bidirectional writing. A stack includes a reference layer on a tunnel barrier, the tunnel barrier on a free layer, and the free layer on a metal spacer. The apparatus includes an insulating magnet. A Peltier material is thermally coupled to the insulating magnet and the stack. When the Peltier/insulating magnet interface is cooled, the insulating magnet is configured to transfer a spin torque to rotate a magnetization of the free layer in a first direction. When the Peltier/insulating magnet interface is heated, the insulating magnet is configured to transfer the spin torque to rotate the magnetization of the free layer in a second direction.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: David W. Abraham, Niladri N. Mojumder
  • Patent number: 8742517
    Abstract: A capacitive sensor is configured for collapsed mode, e.g. for measuring sound or pressure, wherein the moveable element is partitioned into smaller sections. The capacitive sensor provides increased signal to noise ratio.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: June 3, 2014
    Assignee: NXP, B.V.
    Inventors: Geert Langereis, Twan Van Lippen, Reinout Woltjer
  • Patent number: 8735258
    Abstract: Methods of fabricating a semiconductor device including a metal gate transistor and a resistor are provided. A method includes providing a substrate including a transistor device region and an isolation region, forming a dummy gate over the transistor device region and a resistor over the isolation region, and implanting the resistor with a dopant. The method further includes wet etching the dummy gate to remove the dummy gate, and then forming a metal gate over the transistor device region to replace the dummy gate.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hung Ko, Jyh-Huei Chen, Shyh-Wei Wang
  • Patent number: 8735216
    Abstract: Some embodiments include methods for fabricating memory cell constructions. A memory cell may be formed to have a programmable material directly against a material having a different coefficient of expansion than the programmable material. A retaining shell may be formed adjacent the programmable material. The memory cell may be thermally processed to increase a temperature of the memory cell to at least about 300° C., causing thermally-induced stress within the memory cell. The retaining shell may provide a stress which substantially balances the thermally-induced stress. Some embodiments include memory cell constructions. The constructions may include programmable material directly against silicon nitride that has an internal stress of less than or equal to about 200 megapascals. The constructions may also include a retaining shell silicon nitride that has an internal stress of at least about 500 megapascals.
    Type: Grant
    Filed: February 9, 2013
    Date of Patent: May 27, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Jian Li
  • Patent number: 8735976
    Abstract: A Thin Film Transistor-Liquid Crystal Display (TFT-LCD) array substrate is presented which includes a gate line, a data line, and a pixel electrode. The pixel electrode is disposed in a pixel region defined by the intersection between the gate line and the data line. In the pixel region, a partition groove for forming a pixel electrode pattern is provided at the periphery of the pixel electrode.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: May 27, 2014
    Assignee: Beijing Boe Optoelectronics Technology Co., Ltd.
    Inventors: Hongxi Xiao, Jae Yun Jung, Zuhong Liu, Taek Ho Hong, Jeong Hun Rhee
  • Patent number: 8728861
    Abstract: A method is provided for fabricating a thin film transistor. A plurality of layers is deposited on a substrate. The plurality of layers includes a conductive gate contact layer, a gate insulator layer, an undoped channel layer, an etch-stop layer, and a conductive contact layer. The etch-stop layer is positioned between the conductive contact layer and the undoped channel layer. A portion of the conductive contact layer is selectively removed while removal of a portion of the undoped channel layer is prevented by the etch-stop layer during the selective removal. A portion of the etch-stop layer is selectively removed and an exposed portion of the etch-stop layer is converted from a conductor to an insulator by oxidizing the exposed portion of the etch-stop layer in air. A portion of remaining layers of the plurality of layers is selectively removed to form the thin film transistor.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: May 20, 2014
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Burhan Bayraktaroglu, Kevin Leedy
  • Patent number: 8723280
    Abstract: A micro-electro-mechanical systems (MEMS) device and method for forming a MEMS device is provided. A proof mass is suspended a distance above a surface of a substrate by a fulcrum. A pair of sensing plates are positioned on the substrate on opposing sides of the fulcrum. Metal bumps are associated with each sensing plate and positioned near a respective distal end of the proof mass. Each metal bump extends from the surface of the substrate and generally inhibits charge-induced stiction associated with the proof mass. Oxide bumps are associated with each of the pair of sensing plates and positioned between the respective sensing plate and the fulcrum. Each oxide bump extends from the first surface of the substrate a greater distance than the metal bumps and acts as a shock absorber by preventing the distal ends of the proof mass from contacting the metal bumps during shock loading.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: May 13, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Pao Shu, Wen-Chuan Tai, Chia-Ming Hung, Hsiang-Fu Chen
  • Publication number: 20140124669
    Abstract: A Ge waveguide photo-detector fabricated on a silicon-on-insulator substrate is provided. It comprises a Ge waveguide detector end-coupled to a light-signal-carrying silicon waveguide, both disposed on a silicon-on-insulator (SOI) substrate. An electrical field is established along the direction of light propagation inside the Ge waveguide detector by doping the two opposite ends of the Ge detector with P or N type dopants. In result the height and width of the Si waveguide is decoupled from the speed of the Ge detector.
    Type: Application
    Filed: November 6, 2012
    Publication date: May 8, 2014
    Applicant: LAXENSE INC.
    Inventors: Dawei Zheng, Ningning Feng, Xiaochen Sun
  • Patent number: 8716147
    Abstract: Provided are a manufacturing method of a semiconductor device and a substrate processing apparatus.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: May 6, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Takaaki Noda, Masami Miyamoto, Ryuji Yamamoto