Abstract: Disclosed is a method for manufacturing a magnetic storage device comprising a TMR element, which comprises a step for forming an insulting film on an interlayer insulating film provided with a wiring layer, an opening formation step for forming an opening in the insulating film so that the wiring layer is exposed therefrom, a metal layer formation step for forming a metal layer on the insulating layer so that the opening is filled therewith, a CMP step for polishing and removing the metal layer on the insulating layer by a CMP method and forming the metal layer remaining in the opening into a lower electrode, and a step for forming a TMR element on the lower electrode.

Abstract: Disclosed is a method of fabricating a thin film solar cell. A separation process (‘P4’ process) of insulating a thin film solar cell from the outside is integrally performed with a transparent electrode patterning process (‘P1’ process) and a metallic electrode patterning process (‘P3’ process). This may reduce the fabrication costs and enhance spatial efficiency as the ‘P4’ process and equipment for the ‘P4’ process are not required.

Abstract: A method of forming a FinFET device. The method may include providing a substrate having a single crystalline region, heating the substrate to a substrate temperature effective for dynamically removing implant damage during ion implantation, implanting ions into the substrate while the substrate is maintained at the substrate temperature, and patterning the single crystalline region so as to form a single crystalline fin.

Abstract: A high-frequency capacitive micromachined ultrasonic transducer (CMUT) has a silicon membrane and an overlying metal silicide layer that together form a conductive structure which can vibrate over a cavity. The CMUT also has a metal structure that touches a group of conductive structures. The metal structure has an opening that extends completely through the metal structure to expose the conductive structure.

Abstract: A high-frequency capacitive micromachined ultrasonic transducer (CMUT) has a silicon membrane and an overlying metal silicide layer that together form a conductive structure which can vibrate over a cavity. The CMUT also has a metal structure that touches a group of conductive structures. The metal structure has an opening that extends completely through the metal structure to expose the conductive structure.

Abstract: According to an embodiment of the disclosure, a thermal electric cooler is provided that includes a plurality of segments and a plurality of couplers. The segments are coupled in series to form a ladder-configuration string of P-channel chips and N-channel chips. Each segment comprises at least two substrings coupled in parallel. Each substring comprises at least one of the chips. Each of the couplers is configured to couple one of the P-channel chips to one of the N-channel chips.

Abstract: A method of fabricating workpieces includes one or more layers on a substrate that are masked with an ion implantation mask comprising two or more layers. The mask layers include a first mask layer closer to the substrate, and a second mask layer on the first mask layer. The method also comprises ion implanting one or more of the layers on the substrate. Ion implantation may form portions with altered physical properties from the layers under the mask. The portions may form a plurality of non-magnetic regions corresponding to apertures in the mask.

Abstract: In one embodiment, a method of forming a semiconductor device includes providing a substrate, forming a sacrificial layer above the substrate layer, forming a first trench in the sacrificial layer, forming a first sidewall layer with a thickness of less than about 50 nm on a first sidewall of the first trench using atomic layer deposition (ALD), and removing the sacrificial layer.

Abstract: A method for attaching a first carrier device to a second carrier device includes forming at least one first bond layer and/or solder layer on a first exterior of the first carrier device, a partial surface being framed by the at least one first bond layer and/or solder layer, and placing the first carrier device on the second carrier device and fixedly bonding or soldering the first carrier device to the second carrier device. The at least one first bond layer and/or solder layer includes a first cover area which is larger than a first contact area.

Abstract: System and methods for silicon on insulator MEMS pressure sensors are provided. In one embodiment, a method comprises: applying a doping source to a silicon-on-insulator (SOI) silicon wafer having a sensor layer and an insulating layer comprising SiO2 material; doping the silicon wafer with Boron atoms from the doping source while controlling an injection energy of the doping to achieve a top-heavy ion penetration profile; and applying a heat source to diffuse the Boron atoms throughout the sensor layer of the SOI silicon wafer.

Abstract: An HF vapor etch etches high aspect ratio openings to form MEMS devices and other tightly-packed semiconductor devices with 0.2 ?m air gaps between structures. The HF vapor etch etches oxide plugs and gaps with void portions and oxide liner portions and further etches oxide layers that are buried beneath silicon and other structures and is ideally suited to release cantilevers and other MEMS devices. The HF vapor etches at room temperature and atmospheric pressure in one embodiment. A process sequence is provided that forms MEMS devices including cantilevers and lateral, in-plane electrodes that are stationary and vibration resistant.

Abstract: A z-axis fluxgate magnetometer is formed in a semiconductor wafer fabrication sequence, which significantly reduces the size and cost of the fluxgate magnetometer. The semiconductor wafer fabrication sequence forms a vertical magnetic core structure, a first wire structure wound around the magnetic core structure, and a second wire structure wound around the magnetic core structure.

Abstract: An optical bench on substrate includes a substrate and a trench formed inside the substrate and having a sloping side. A reflector layer is formed over the sloping side. An optical component is mounted over the substrate. The reflector layer is configured to reflect an electromagnetic wave to or from the optical component.

Abstract: An embedded micro-electro-mechanical system (MEMS) (100) comprising a semiconductor chip (101) embedded in an insulating board (120), the chip having a cavity (102) including a radiation sensor MEMS (105), the opening (104) of the cavity at the chip surface covered by a plate (110) transmissive to the radiation (150) sensed by the MEMS. The plate surface remote from the cavity having a bare central area, to be exposed to the radiation sensed by the MEMS in the cavity, and a peripheral area covered by a metal film (111) touching the plate surface and a layer (112) of adhesive stacked on the metal film.

Abstract: One aspect of the invention pertains to an integrated circuit package with an embedded power stage. The integrated circuit package includes a first field effect transistor (FET) and a second FET that are electrically coupled with one another. The FETs are embedded in a dielectric substrate that is formed from multiple dielectric layers. The dielectric layers are laminated together with one or more foil layers that help form an electrical interconnect for the package. Various embodiments relate to method of forming the above package.

Abstract: A method for patterning self-aligned vias in a dielectric. The method includes forming a first trench partially through a hard mask, where the trench corresponds to a desired wiring path in the dielectric. The trench should be formed on a sub-lithographic scale. Then, form a second trench, also of a sub-lithographic scale, that intersects the first trench. The intersection forms a pattern extending through the depth of the hard mask, and corresponds to a via hole in the dielectric. The via hole is etched into the dielectric through the hard mask. Then the first trench is extended through the hard mask and the exposed area is etched to form the wiring path, which intersects the via hole. Conductive material is deposited to form a sub-lithographic via and wiring. This method may be used to form multiple vias of sub-lithographic proportions and with a sub-lithographic pitch.

Abstract: Provided is a method of manufacturing an electromechanical transducer having a reduced variation in a breakdown strength caused by a variation in flatness of an insulating layer. In the method of manufacturing the electromechanical transducer, a first insulating layer is formed on a first substrate, a barrier wall is formed by removing a part of the first insulating layer, and a second insulating layer is formed on a region of the first substrate after the part of the first insulating layer has been removed. Next, a gap is formed by bonding a second substrate on the barrier wall, and a vibration film that is opposed to the second insulating layer via the gap is formed from the second substrate. In the forming of the barrier wall, a height on a gap side in a direction vertical to the first substrate becomes lower than a height of a center portion.

Abstract: An assembly (20) includes a MEMS die (22) having a pressure transducer device (40) formed on a substrate (44) and a cap layer (38). A packaging process (74) entails forming the device (40) on the substrate, creating an aperture (70) through a back side (58) of the substrate (44) underlying a diaphragm (46) of the device (40), and coupling a cap layer (38) to the front side of the substrate (44) overlying the device (40). A trench (54) is produced extending through both the cap layer (38) and the substrate (44), and surrounds a cantilevered platform (48) at which the diaphragm (46) resides. The die (22) is suspended above a substrate (26) so that a clearance space (60) is formed between the platform (48) and the substrate (26). The diaphragm (46) is exposed to an external environment (68) via the aperture (70) and the space (60), and an external port.

Abstract: A method for fabricating a semiconductor laser includes: sequentially forming a cladding layer of a first conductivity type, an active layer, a cladding layer of a second conductivity type, and a contact layer of the second conductivity type on a semiconductor substrate; forming a promotion film which contacts the contact layer only in a window region proximate an end plane of the semiconductor laser and absorbs group-III atoms from the contact layer to promote generation of group-III vacancies; implanting ions into the contact layer in the window region to damage the contact layer in the window region; and after forming the promotion film and implanting the ions, heat treating so that the group-III vacancies are diffused and the active layer is disordered in the window region and forms a window structure.

Abstract: A magnetic tunnel junction (MTJ) storage element and method of forming the MTJ are disclosed. The magnetic tunnel junction (MTJ) storage element includes a pinned layer, a barrier layer, a free layer and a composite hardmask or top electrode. The composite hardmask/top electrode architecture is configured to provide a non-uniform current path through the MTJ storage element and is formed from electrodes having different resistance characteristics coupled in parallel. An optional tuning layer interposed between the free layer and the top electrode helps to reduce the damping constant of the free layer.

Abstract: The micro-mechanical device includes a substrate with an internal cavity, a first surface, and an opposing second surface. A first trench is formed from the first surface of the substrate into the internal cavity. The first trench at least partially defines flexures. A second trench is formed from the second surface of the substrate into the internal cavity and at least partially defines a suspended mass. The suspended mass is connected by the flexures to the substrate.

Abstract: A device having an integrated noise shield is disclosed. The device includes a plurality of vertical shielding structures substantially surrounding a semiconductor device. The device further includes an opening above the semiconductor device substantially filled with a conductive fluid, wherein the plurality of vertical shielding structures and the conductive fluid shield the semiconductor device from ambient radiation. In some embodiments, the device further includes a conductive bottom shield below the semiconductor device shielding the semiconductor device from ambient radiation. In some embodiments, the opening is configured to allow a biological sample to be introduced into the semiconductor device. In some embodiments, the vertical shielding structures comprise a plurality of vias, wherein each of the plurality of vias connects more than one conductive layers together.

Abstract: A structure includes a substrate, a first supporting member over the substrate, a second supporting member over the substrate, and a layer of material over the substrate and covering the first supporting member and the second supporting member. The first supporting member has a first width, and the second supporting member has a second width. The first supporting member and the second supporting member are separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region ranges from 5 to 30 times the second width.

Abstract: Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a protective material over a bottom surface and edges of the workpiece. A top surface of the workpiece is processed. The protective material protects the edges and the bottom surface of the workpiece during the processing of the top surface of the workpiece.

Abstract: A method for making a lighting apparatus includes providing a substrate and disposing a light-emitting diode overlying the substrate. The light-emitting diode has a top surface oriented away from the substrate and a plurality of side surfaces. A light-conversion material is provided that includes a substantially transparent base material and a wave-shifting material dispersed in the base material. The concentration of the wave-shifting material can be at least 30%. In an embodiment, the concentration of the wave-shifting material can be approximately 50% or 70%. A predetermined amount of the light-conversion material is deposited on the top surface of the light-emitting diode while the side surfaces are maintained substantially free of the light-conversion material.

Abstract: In certain desirable embodiments, the present invention relates to the use of 15N isotopes into GaAsN, InAsN or GaSbN films for ion beam analysis. A semiconductor-nitride assembly for growing and analyzing crystal growth in a group III-V semiconductor sample that includes: a substrate; a buffer layer deposited on the substrate, a nitrogen gas injector to incorporate enriched nitrogen gas and the nitrogen gas injector includes a concentration of enriched nitrogen gas, a thin film consisting of at least one group III element containing compound where at least one group III element is covalently bonded with the nitrogen in the presence of the same or different group V element of the buffer layer, and a proton beam to analyze the incorporation of the nitrogen gas in the thin film layer is described.

Abstract: A method for integrating an IC and a MEMS component includes the following steps: S1) providing a SOI base (20) having a first area (21) and a second area (22); S2) fabricating an IC on the first area through a standard semiconductor process, and simultaneously forming a metal conductive layer (26) and a medium insulation layer (25c) extending to the second area; S3) partly removing the medium insulation layer and then further partly removing the silicon component layer so as to form a backplate diagram; S4) depositing a sacrificial layer (32) above the SOI base; S5) forming a Poly Sil-xGex film (33) on the sacrificial layer; S6) forming a back cavity (34); and S7) eroding the sacrificial layer to form a chamber (36) in communication with the back cavity. Besides, a chip (10) fabricated by the above method is also disclosed.

Abstract: Embodiments related to pressure sensitive structures are described and depicted.

Abstract: Systems and methods for conductive pillars are provided. In one embodiment, a system comprises an electrical board comprising an electrical device, and a packaged die, the packaged die bonded to the electrical board. The packaged die comprises a substrate layer, the substrate layer comprising a recessed area, a conductive trace, wherein a portion of the conductive trace is formed in the recessed area, and an epitaxial device layer bonded to the substrate layer. The device layer comprises a MEMS device, and an epitaxial conductive pillar, wherein a first side of the epitaxial conductive pillar is electrically connected to the conductive trace and the second side of the epitaxial conductive pillar is electrically connected to the electrical board, wherein the epitaxial conductive pillar extends through the epitaxial device layer to electrically couple the conductive trace to an interface surface on the epitaxial device layer.

Abstract: Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. To improve the copper plating, a seed layer formed in the through-wafer vias can be modified to increase water affinity, rinsed to remove contaminants, and activated to facilitate copper deposition. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.

Abstract: A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

Abstract: A photonic device and methods of formation that provide an area providing reduced optical coupling between a substrate and an inner core of the photonic device are described. The area is formed using holes in the inner core and an outer cladding. The holes may be filled with materials which provide a photonic crystal. Thus, the photonic device may function as a waveguide and as a photonic crystal.

Abstract: An integrated circuit includes a first and a second field effect transistor structure. The first field effect transistor structure includes a first gate electrode structure and a first field electrode structure. The second field effect transistor structure includes a second gate electrode structure and a second field electrode structure. The first and the second gate electrode structures are electrically separated from each other. The first and the second field electrode structures are separated from each other.

Abstract: A light source for a photonic integrated circuit may comprise a reflection coupling layer formed on a substrate in which an optical waveguide is provided, at least one side of the reflection coupling layer being optically connected to the optical waveguide; an optical mode alignment layer provided on the reflection coupling layer; and/or an upper structure provided on the optical mode alignment layer and including an active layer for generating light and a reflection layer provided on the active layer. A light source for a photonic integrated circuit may comprise a lower reflection layer; an optical waveguide optically connected to the lower reflection layer; an optical mode alignment layer on the lower reflection layer; an active layer on the optical mode alignment layer; and/or an upper reflection layer on the active layer.

Abstract: System and method for reducing substrate warpage in a thermal process. An embodiment comprises pre-heating a substrate in a loadlock chamber before performing the thermal process of the substrate. After the thermal process, the substrate is cooled down in a loadlock chamber. The pre-heat and cool-down process reduces the warpage of the substrate caused by the differences in coefficients of thermal expansion (CTEs) of the materials that make up the substrate.

Abstract: A method for manufacturing a pixel structure is provided. A thin film transistor is formed on a substrate and an insulating layer is formed to cover the substrate and the thin film transistor. The insulating layer is patterned by a half-tone mask to form a protruding pattern, a sunken pattern connecting the protruding pattern, and a contact window inside the sunken pattern. A transparent conductive layer is formed to cover the protruding pattern and the sunken pattern, and filled in the contact window. A passivation layer is formed to cover the transparent conductive layer. A pixel electrode pattern is formed from the transparent conductive layer by removing a part of the passivation layer located on the protruding pattern, a part of the transparent conductive layer on the protruding pattern, and a part of the passivation layer located within the contact window. A pixel structure manufactured by the method is provided.

Abstract: A nanopiezoelectric generator is provided. The nanopiezoelectric generator includes a first electrode; a second electrode; at least one nanostructure that is interposed between the first electrode and the second electrode, and includes a piezoelectric material and first carriers; and a concentration adjusting unit that adjusts a concentration of the first carriers in the at least one nanostructure.

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming at least one fixed electrode on a substrate. The method further includes forming a Micro-Electro-Mechanical System (MEMS) beam with a varying width dimension, as viewed from a top of the MEMS beam, over the at least one fixed electrode.

Abstract: A magnetic shift register includes a first supporting layer, a second supporting layer, a first pinning material layer, and at least one magnetic memory track. The first supporting layer has trenches on a first surface extending along a first direction. The second supporting layer is filled in the trenches, wherein the first support layer and the second support layer have at least a portion substantially equal in height. The first pinning material layer is disposed between the first supporting layer and the second supporting layer, wherein a plurality of end surfaces of the first pinning material layer are exposed on the first surface. The magnetic memory track extending along a second direction on the first surface is disposed over the first support layer, the first pinning material layer, and the second support layer, wherein the second direction is not the same or perpendicular to the first direction.

Abstract: A micro-electro-mechanical system (MEMS), methods of forming the MEMS and design structures are provided. The method comprises forming a coplanar waveguide (CPW) comprising a signal electrode and a pair of electrodes on a substrate. The method comprises forming a first sacrificial material over the CPW, and a wiring layer over the first sacrificial material and above the CPW. The method comprises forming a second sacrificial material layer over the wiring layer, and forming insulator material about the first sacrificial material and the second sacrificial material. The method comprises forming at least one vent hole in the insulator material to expose portions of the second sacrificial material, and removing the first and second sacrificial material through the vent hole to form a cavity structure about the wiring layer and which exposes the signal line and pair of electrodes below the wiring layer. The vent hole is sealed with sealing material.

Abstract: A microelectromechanical system (MEMS) assembly includes at least one emission source; a top wafer having a plurality of side walls and a generally horizontal portion, the horizontal portion having a thickness between a first side and a directly opposed second side, at least one window in the horizontal portion extending between the first and second sides and a transmission membrane across the at least one window; and a bottom wafer having a first portion with a first substantially planar surface, an intermediate surface directly opposed to the first substantially planar surface, a second portion with a second substantially planar surface, the at least one emission source provided on the second substantially planar surface; where the top wafer bonds to the bottom wafer at the intermediate surface and encloses a cavity within the top wafer and the bottom wafer.

Abstract: Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed on a piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam formed above the piezoelectric substrate and at a location in which, upon actuation, the MEMS beam shorts the piezoelectric filter structure by contacting at least one of the plurality of electrodes.

Abstract: Disclosed are an optical waveguide platform with integrated active transmission device and monitoring photodiode. The optical waveguide platform with hybrid integrated optical transmission device and optical active device includes an optical waveguide region formed by stacking a lower cladding layer, a core layer and an upper cladding layer on a substrate; a trench region formed by etching a portion of the optical waveguide region; and a spot expanding region formed on the core layer in the optical waveguide region, in which the optical transmission device is mounted in the trench region and the optical active device is flip-chip bonded to the spot expanding region. The monitoring photodiode is flip-chip bonded to the spot expanding region of the core layer of the optical waveguide, thereby monitoring output light including an optical coupling loss that occurs during flip-chip bonding.

Abstract: A method of fabricating a semiconductor laser device by forming a semiconductor structure at least part of which is in the form of a mesa structure having a flat top. The steps include depositing a passivation layer over the mesa structure, forming a contact opening in the passivation layer on the flat top of the mesa structure; and depositing a metal contact portion, with the deposited metal contact portion contacting the semiconductor structure via the contact opening. The contact opening formed through the passivation layer has a smaller area than the flat top of the mesa structure to allow for wider tolerances in alignment accuracy. The metal contact portion comprises a platinum layer between one or more gold layers to provide an effective barrier against Au diffusion into the semiconductor material.

Abstract: In an embodiment, a method of fabricating a fluid ejection device includes forming a resistor on the front side of a substrate, depositing a dielectric film on the resistor to protect the resistor from chemical exposure during a slot formation process, and forming a slot in the substrate that extends from the back side to the front side of the substrate.

Abstract: A sensor element array and method of fabricating the same are provided. The sensor element array is disposed on a substrate and includes a first patterned conductive layer, a channel layer, a first insulation layer, a second patterned conductive layer, a second insulation layer, and a third patterned conductive layer. The first patterned conductive layer includes a sensing line, a first power line, a source/drain pattern and a branch pattern. The channel layer includes a first channel and a second channel. Margins of the first insulation layer and the second patterned conductive layer are substantially overlapped. The second patterned conductive layer includes a selecting line, a gate pattern, and a gate connecting pattern. The second insulation layer has a first connecting opening for exposing the gate connecting pattern. The third patterned conductive layer includes a sensing electrode electrically connected to the gate connecting pattern.

Abstract: A semiconductor device includes a substrate including a cavity and a first material layer over at least a portion of sidewalls of the cavity. The semiconductor device includes an oxide layer over the substrate and at least a portion of the sidewalls of the cavity such that the oxide layer lifts off a top portion of the first material layer toward a center of the cavity.

Abstract: Carbon transistor devices having channels formed from carbon nanostructures, such as carbon nanotubes or graphene, and having charged monolayers to reduce parasitic resistance in un-gated regions of the channels, and methods for fabricating carbon transistor devices having charged monolayers to reduce parasitic resistance. For example, a carbon field effect transistor includes a channel comprising a carbon nanostructure formed on an insulating layer, a gate structure formed on the channel, a monolayer of DNA conformally covering the gate structure and a portion of the channel adjacent the gate structure, an insulating spacer conformally formed on the monolayer of DNA, and source and drain contacts connected by the channel.

Abstract: The present invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a III-V semiconductor layer; an aluminum oxide layer formed on the III-V semiconductor layer; and a lanthanide oxide layer formed on the aluminum oxide layer. The method of manufacturing a semiconductor device includes: forming an aluminum oxide layer between a III-V semiconductor layer and a lanthanide oxide layer so as to prevent an inter-reaction of atoms between the III-V semiconductor layer and the lanthanide oxide layer.

Abstract: A device includes a passive photonic layer located over a substrate and including at least one passive photonic element configured to propagate an optical signal therein. An electronic layer located between said substrate and said passive photonic layer includes at least one electronic device configured to propagate an electrical signal therein. An active photonic layer located over said passive photonic layer includes an active photonic device optically coupled to said passive photonic element and configured to convert between said electrical signal and said optical signal.