Abstract: A temperature compensated bulk acoustic wave (BAW) resonator device has low trim sensitivity for providing an accurate resonant frequency. The BAW resonator device includes a first electrode deposited on a substrate, a piezoelectric layer deposited on the first electrode, a second electrode deposited on the piezoelectric layer, and a mirror pair deposited on the second electrode. At least one of the first electrode and the second electrode includes an electrode layer, and a temperature compensating layer configured to compensate for a temperature coefficient of at least the piezoelectric layer.

Abstract: A method and system provide a magnetic junction usable in a magnetic device. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, a free layer, at least one insulating layer, and at least one magnetic insertion layer adjoining the at least one insulating layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The at least one insulating layer is adjacent to at least one of the free layer and the pinned layer. The at least one magnetic insertion layer adjoins the at least one insulating layer. In some aspects, the insulating layer(s) include at least one of magnesium oxide, aluminum oxide, tantalum oxide, ruthenium oxide, titanium oxide, and nickel oxide The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

Abstract: A micro electro mechanical system (MEMS) structure is disclosed. The MEMS structure includes a backplate electrode and a 3D diaphragm electrode. The 3D diaphragm electrode has a composite structure so that a dielectric is disposed between two metal layers. The 3D diaphragm electrode is adjacent to the backplate electrode to form a variable capacitor together.

Abstract: MEMS devices (40) using etched cavities (42) are desirably formed using multiple etching steps. Preliminary cavities (20) formed by locally anisotropic etching to nearly the final depth have irregular (46) sidewalls (44) and steep and/or inconsistent sidewall (44) to bottom (54) intersection angles (48). This leads to less than desired cavity diaphragm (26) burst strengths. Final cavities (42) with smooth sidewalls (50), smaller and consistent sidewall (50) to bottom (54) intersection angles (58), and having more than doubled cavity diaphragm (26) burst strengths are obtained by treating the preliminary cavities (20) with TMAH etchant, preferably relatively dilute TMAH etchant. In a preferred embodiment, a cleaning step is performed between the etching step and the TMAH treatment step to remove any anisotropic etching by-products present on the preliminary cavities' (20) initial sidewalls (44).

Abstract: The invention relates to a method for production of at least one thermoelectric apparatus with the steps of: preparation of a first wafer (1) which is formed from a thermoelectric material of a first conductivity type; preparation of a second wafer which is formed from a thermoelectric material of a second conductivity type; structuring of the first wafer (1) so that a group of first thermoelectric structures (7) is produced; structuring of the second wafer so that a group of second thermoelectric structures is produced; and linking of the first to the second wafer in such a manner that the first and the second thermoelectric structures are electrically connected together and thus form the thermoelectric apparatus. According to the invention, before the structuring of the first wafer (1), a first contact material (3) is deposited on the first wafer (1) and/or before the structuring of the second wafer, a second contact material is deposited onto the second wafer.

Abstract: A method and structure for adding mass with stress isolation to MEMS. The structure has a thickness of silicon material coupled to at least one flexible element. The thickness of silicon material can be configured to move in one or more spatial directions about the flexible element(s) according to a specific embodiment. The apparatus also includes a plurality of recessed regions formed in respective spatial regions of the thickness of silicon material. Additionally, the apparatus includes a glue material within each of the recessed regions and a plug material formed overlying each of the recessed regions.

Abstract: A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k dielectric layer, and an aluminum-containing metal line over and electrically coupled to the copper-containing via. The aluminum-containing metal line is in the second low-k dielectric layer.

Abstract: A pressure sensor includes a first housing having a cavity. The pressure sensor further includes a pressure sensing device attached to a bottom of the cavity. The pressure sensor further includes a layer of gel over the pressure sensing device. The pressure sensor further includes a baffle in contact with the gel to reduce movement of the gel.

Abstract: In a manufacturing method of a semiconductor device, a substrate including single crystalline silicon is prepared, a reformed layer that continuously extends is formed in the substrate, and the reformed layer is removed by etching. The forming the reformed layer includes polycrystallizing a portion of the single crystalline silicon by irradiating the substrate with a pulsed laser beam while moving a focal point of the laser beam in the substrate.

Abstract: A method for manufacturing a MEMS device is disclosed. Moreover a MEMS device and a module including a MEMS device are disclosed. An embodiment includes a method for manufacturing MEMS devices includes forming a MEMS stack on a first main surface of a substrate, forming a polymer layer on a second main surface of the substrate and forming a first opening in the polymer layer and the substrate such that the first opening abuts the MEMS stack.

Abstract: A magnetic junction is described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The magnetic junction may also include an additional nonmagnetic spacer layer and an additional pinned layer opposing the nonmagnetic spacer layer and the pinned layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer is configured to be switchable using a write current passed through the magnetic junction. The free layer is also configured to be thermally stable in a quiescent state and have a reduced thermal stability due to heating from the write current being passed through the magnetic junction. In some aspects, the free layer includes at least one of a pinning layer(s) interleaved with ferromagnetic layer(s), two sets of interleaved ferromagnetic layers having different Curie temperatures, and a ferrimagnet having a saturation magnetization that increases with temperature between ferromagnetic layers.

Abstract: A simple and cost-effective form of implementing a semiconductor component having a micromechanical microphone structure, including an acoustically active diaphragm as a deflectable electrode of a microphone capacitor, a stationary, acoustically permeable counterelement as a counter electrode of the microphone capacitor, and means for applying a charging voltage between the deflectable electrode and the counter electrode of the microphone capacitor. In order to not impair the functionality of this semiconductor component, even during overload situations in which contact occurs between the diaphragm and the counter electrode, the deflectable electrode and the counter electrode of the microphone capacitor are counter-doped, at least in places, so that they form a diode in the event of contact. In addition, the polarity of the charging voltage between the deflectable electrode and the counter electrode is such that the diode is switched in the blocking direction.

Abstract: An organic thin film solar cell comprises: positive and negative electrode layers; and an organic thin film layer disposed between the positive and negative electrode layers, the organic thin film layer including: a mixture of at least a first organic compound having a light-absorbing dye moiety and an electron-accepting second organic compound, in which the organic thin film layer further includes inorganic nanoparticles.

Abstract: In one embodiment, a load frame and an integrated circuit device are aligned, with a base frame carried on a substrate, along a first alignment axis defined by a first alignment post extending from the base frame to the load frame, in a direction transverse to the substrate, and a first biasing device carried on the base frame is actuated to engage and bias the load frame toward the base frame aligned with the load frame, and to bias the integrated circuit toward the substrate. A latch latches the load and base frames together, aligned with and biased towards each other with the integrated circuit device and the substrate aligned with, and biased toward each other. Other aspects and features are also described.

Abstract: A device and a method of forming the same are disclosed. The device comprises a substrate and a thin film. The substrate is characterized by a first coefficient of thermal expansion. The thin film is attached to a surface of the substrate, and is characterized by a second coefficient of thermal expansion. The thin film includes first and second layers in states of compression, and a third layer in a state of tension, the third layer being positioned between the first and second layers. The thin film is in a net state of tension within a temperature range.

Abstract: Mirror-polished CZ wafer and FZ wafer are prepared. A first impurity region which will be a first isolation region is formed in a surface layer of a first main surface of the CZ wafer. The first main surface of the CZ wafer and a first main surface of the FZ wafer are bonded to each other by an inter-molecular bond. A second impurity region which will be a second isolation region is formed in a surface layer of a second main surface of the FZ wafer. A heat treatment is performed to diffuse the first impurity region and the second impurity region such that the first impurity region and the second impurity region are continuous, thereby forming a through silicon isolation region.

Abstract: The fabrication of a semiconductor fixed structure defining a volume, for example of a MEMS micro electro-mechanical system includes, determining thicknesses beforehand depending on the functional distances associated with elements. At least one element is formed on a substrate by thermal oxidation of the substrate so as to form an oxide layer followed by selective etching of the oxide layer so as to define the volume in an etched portion by baring the underlying substrate so as to define the element in an unetched portion, and later oxidation of the substrate so as to form an oxide layer, in order to obtain the elements at the functional distances.

Abstract: Spin transfer torque memory (STTM) devices with topographically smooth electrodes and methods of fabricating STTM devices with topographically smooth electrodes are described. For example, a material layer stack for a magnetic tunneling junction includes a topographically smooth bottom electrode, a topographically smooth dielectric layer disposed above the bottom electrode, and a free magnetic layer disposed above the topographically smooth dielectric layer.

Abstract: After a TEOS oxide film is formed on the surface of a semiconductor device, a PSG film and an SiN film, which have air permeability, are formed on the surface of the TEOS oxide film. Thereafter, a Poly-Si film is formed thereon. A sacrifice layer is removed by a gaseous HF that passes through the PSG film, the SiN film, and the Poly-Si film, and then, the uppermost layer is covered with a Poly-Si/SiC film. A chip scale package having a thin-film hollow-seal structure can be realized on the semiconductor element.

Abstract: Methods are provided for fine tuning substrate resistivity. The method includes measuring a resistivity of a substrate after an annealing process, and fine tuning a subsequent annealing process to achieve a target resistivity of the substrate. The fine tuning is based on the measured resistivity.

Abstract: A microelectronic device including a substrate, at least a semi-conductor element, an anti metal ion layer, a non-doping oxide layer and a MEMS structure is provided. The substrate has a CMOS circuit region and a MEMS region. The semi-conductor element is configured within the CMOS circuit region of the substrate. The anti metal ion layer is disposed within the CMOS circuit region of the substrate and covers the semi-conductor element. The non-doping oxide layer is disposed on the substrate within the MEMS region. The MEMS structure is partially suspended above the non-doping oxide layer. The present invention also provides a MEMS package structure and a fabricating method thereof.

Abstract: Non-planar semiconductor FET based sensors are provided that have an enhanced sensing area to volume ratio which results in faster response times than existing planar FET based sensors. The FET based sensors of the present disclosure include a V-shaped gate dielectric portion located in a V-shaped opening formed in a semiconductor substrate. In some embodiments, the FET based sensors of the present disclosure also include a self-aligned source region and a self-aligned drain region located in the semiconductor substrate and on opposing sides of the V-shaped opening. In other embodiments, the FET based sensors include a self-aligned source region and a self-aligned drain region located in the semiconductor substrate and on opposing sides of a gate dielectric material portion that is present on an uppermost surface of the semiconductor substrate.

Abstract: An improved PMA STT MTJ storage element, and a method for forming it, are described. By inserting a suitable oxide layer between the storage and cap layers, improved PMA properties are obtained, increasing the potential for a larger Eb/kT thermal factor as well as a larger MR. Another important advantage is better compatibility with high processing temperatures, potentially facilitating integration with CMOS.

Abstract: A MEMS device includes a silicon substrate and a structural dielectric layer. The silicon substrate has a cavity. The structural dielectric layer is disposed on the silicon substrate. The structural dielectric layer has a space above the cavity of the silicon substrate and holds a plurality of structure elements within the space, including: a conductive backplate, over the silicon substrate, having a plurality of venting holes and a plurality of protrusion structures on top of the conductive backplate; and a diaphragm, located above the conductive backplate by a distance, wherein a chamber is formed between the diaphragm and the conductive backplate, and is connected to the cavity of the silicon substrate through the venting holes. A first side of the diaphragm is exposed by the chamber and faces to the protrusion structures of the conductive backplate and a second side of the diaphragm is exposed to an environment space.

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes layering metal and insulator materials on a sacrificial material formed on a substrate. The method further includes masking the layered metal and insulator materials. The method further includes forming an opening in the masking which overlaps with the sacrificial material. The method further includes etching the layered metal and insulator materials in a single etching process to form the beam structure, such that edges of the layered metal and insulator material are aligned. The method further includes forming a cavity about the beam structure through a venting.

Abstract: A method for manufacturing a semiconductor device has a step of forming a first substrate; a step of facing a first main electrode to the first metal foil, and electrically connecting the first main electrode and the first metal foil; a step of facing a second main electrode to the second metal foil, and electrically connecting the second main electrode and the second metal foil; a step of forming a second substrate; and steps of facing a surface side of the second substrate to a surface side of the first substrate; electrically connecting the third metal foil and a third main electrode provided on a main surface of the first semiconductor element; and electrically connecting the fourth metal foil and a fourth main electrode provided on a main surface of the second semiconductor element.

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary method of fabricating a semiconductor device on a doped region of semiconductor material having a first conductivity type involves forming a first region having a second conductivity type within the doped region, forming a body region having the first conductivity type overlying the first region, and forming a drift region having the second conductivity type within the doped region, wherein at least a portion of the drift region abuts at least a portion of the first region. In one embodiment, the dopant concentration of the first region is less than the dopant concentration of the body region and different from the dopant concentration of the drift region.

Abstract: A high power semiconductor device for operation at powers greater than 5 watts for wireless applications comprises a semiconductor substrate including an active area of the high power semiconductor device, contact regions formed on the semiconductor substrate providing contacts to the active area of the high power semiconductor device, a dielectric layer formed over a part of the semiconductor substrate, a lead for providing an external connection to the high power semiconductor device and an impedance matching network formed on the semiconductor substrate between the active area of the high power semiconductor device and the lead. The impedance matching network includes conductor lines formed on the dielectric layer. The conductor lines are coupled to the contact regions for providing high power connections to the contact regions of the active area, and have a predetermined inductance for impedance matching.

Abstract: Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit.

Abstract: Test dies having metrology test structures and methods of manufacture are disclosed. The method includes forming one or more metrology test structures in a test die that are identical to one or more structures formed in an adjacent product chip.

Abstract: A micro-electrochemical sensor contains magnetic compounds inserted within a substrate that exert a magnetic force of attraction on paramagnetic beads held in contact with an electrode. The magnetic compounds can be contained within a fluid that is introduced into a void in the substrate. The electrode can be spaced apart from the magnetic compounds by a dielectric multi-layer membrane. During the fabrication process, different layers within the membrane-electrode structure can be tuned to have compressive or tensile stress so as to maintain structural integrity of the membrane, which is thin compared with the size of the void beneath it. During a process of forming the structure of the sensor, the tensile stress in a TiW adhesion layer can be adjusted to offset a composite net compressive stress associated with the dielectric layers of the membrane. The membrane can also be used in forming both the electrode and the void.

Abstract: Embodiments of the invention describe apparatuses, systems, and methods of thermal management for photonic integrated circuits (PICs). Embodiments include a first device and a second device comprising including waveguides, wherein the first and second devices have different thermal operating conditions. A first region is adjacent to a waveguide of the first device, wherein its optical mode is to be substantially confined by the first region, and wherein the first region has a first thermal conductivity to dissipate heat based on the thermal operating condition of the first device. A second region is adjacent to a waveguide of the second device, wherein its optical mode is to be substantially confined by the second region, and wherein the second region has a second thermal conductivity to dissipate heat based on the thermal operating condition of the second device. In some embodiments, thermal cross talk is reduced without significantly affecting optical performance.

Abstract: A method for forming a photoresist layer on a semiconductor device is disclosed. An exemplary includes providing a wafer. The method further includes spinning the wafer during a first cycle at a first speed, while a pre-wet material is dispensed over the wafer and spinning the wafer during the first cycle at a second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer during a second cycle at the first speed, while the pre-wet material continues to be dispensed over the wafer and spinning the wafer during the second cycle at the second speed, while the pre-wet material continues to be dispensed over the wafer. The method further includes spinning the wafer at a third speed, while a photoresist material is dispensed over the wafer including the pre-wet material.

Abstract: A vapor deposition method of the present invention includes the steps of (i) preparing a mask unit including a shadow mask (81) and a vapor deposition source (85) fixed in position relative to each other, (ii) while moving at least one of the mask unit and the film formation substrate (200) relative to the other, depositing a vapor deposition flow, emitted from the vapor deposition source (85), onto a vapor deposition region (210), and (iii) adjusting the position of a second shutter (111) so that the second shutter (111) blocks a vapor deposition flow traveling toward the vapor deposition unnecessary region (210).

Abstract: A magnetic memory is described. The magnetic memory includes magnetic junctions and at least one spin-orbit interaction (SO) active layer. Each of the magnetic junctions includes a data storage layer that is magnetic. The SO active layer(s) are adjacent to the data storage layer of the magnetic junction. The at SO active layer(s) are configured to exert a SO torque on the data storage layer due to a current passing through the at least one SO active layer in a direction substantially perpendicular to a direction between the at least one SO active layer and the data storage layer of a magnetic junction of the plurality of magnetic junctions closest to the at least one SO active layer. The data storage layer is configured to be switchable using at least the SO torque.

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity. The method for forming the cavity further includes forming at least one first vent hole of a first dimension which is sized to avoid or minimize material deposition on a beam structure during sealing processes. The method for forming the cavity further includes forming at least one second vent hole of a second dimension, larger than the first dimension.

Abstract: A monolithic multi-channel resistive memory includes at least one first bank associated with a first channel and tuned according to first device attributes and/or first circuit attributes. The memory also includes at least one second bank associated with a second channel and tuned according to second device attributes and/or second circuit attributes.

Abstract: A system and a method for forming a packaged MEMS device are disclosed. In one embodiment a packaged MEMS device includes a MEMS device having a first main surface with a first area along a first direction and a second direction, a membrane disposed on the first main surface of the MEMS device and a backplate adjacent to the membrane. The packaged MEMS device further includes an encapsulation material that encapsulates the MEMS device and that defines a back volume, the back volume having a second area along the first direction and the second direction, wherein the first area is smaller than the second area.

Abstract: A method of manufacturing a memory device includes forming a first dielectric layer over a substrate, forming a charge storage element over the first dielectric layer and forming an inter-gate dielectric over the charge storage element. The method also includes depositing a silicon control gate layer over the inter-gate dielectric using a reactant that contains chlorine.

Abstract: A micro-electro-mechanical systems (MEMS) device and method for forming a MEMS device is provided. A proof mass is suspended a distance above a surface of a substrate by a fulcrum. A pair of sensing plates are positioned on the substrate on opposing sides of the fulcrum. Metal bumps are associated with each sensing plate and positioned near a respective distal end of the proof mass. Each metal bump extends from the surface of the substrate and generally inhibits charge-induced stiction associated with the proof mass. Oxide bumps are associated with each of the pair of sensing plates and positioned between the respective sensing plate and the fulcrum. Each oxide bump extends from the first surface of the substrate a greater distance than the metal bumps and acts as a shock absorber by preventing the distal ends of the proof mass from contacting the metal bumps during shock loading.

Abstract: A system and method are disclosed for processing semiconductors. An embodiment comprises a reaction chamber for processing wafers and having walls tapering at an angle that is greater than 0 degrees and less than about 35 degrees from a first end optionally having a diameter of 341 to 380 millimeters to a second end optionally having a diameter of 300 to 340 millimeters at a second end, with gas flow from the first end to the second end, and having at least one deposition injector near the first end of the reaction chamber and having a plurality of injector openings that disperse injection material across a cross section of the reaction chamber for forming a deposition layer.

Abstract: A method for forming a sensor includes forming a base-region barrier in contact with a base substrate. The base-region barrier includes a monocrystalline semiconductor having a same dopant conductivity as the base substrate. An emitter and a collector are formed in contact with and on opposite sides of the base-region barrier to form a bipolar junction transistor. The collector, the emitter and the base-region barrier are planarized to form a level surface opposite the base substrate such that when the level surface is exposed to charge, the charge is measured during operation of the bipolar junction transistor.

Abstract: A component having a robust, but acoustically sensitive microphone structure is provided and a simple and cost-effective method for its production. This microphone structure includes an acoustically active diaphragm, which functions as deflectable electrode of a microphone capacitor, a stationary, acoustically permeable counter element, which functions as counter electrode of the microphone capacitor, and an arrangement for detecting and analyzing the capacitance changes of the microphone capacitor. The diaphragm is realized in a diaphragm layer above the semiconductor substrate of the component and covers a sound opening in the substrate rear. The counter element is developed in a further layer above the diaphragm. This further layer generally extends across the entire component surface and compensates level differences, so that the entire component surface is largely planar according to this additional layer.

Abstract: A nonvolatile resistive memory element has a novel variable resistance layer that is passivated with non-metallic dopant atoms, such as nitrogen, either during or after deposition of the switching layer. The presence of the non-metallic dopant atoms in the variable resistance layer enables the switching layer to operate with reduced switching current while maintaining improved data retention properties.

Abstract: A semiconductor device includes a substrate having a main surface and a rear surface, a transistor formed over a side of the main surface, an insulator layer formed over a side of the main surface, an inductor formed over the insulator layer and a side of the main surface, a tape overlapping the inductor and formed over a side of the main surface, and a bonding pad formed over the insulating layer and a side of the main surface. The tape is selectively formed over an area without the bonding pad.

Abstract: A process for manufacturing a micromechanical structure envisages: forming a buried cavity within a body of semiconductor material, separated from a top surface of the body by a first surface layer; and forming an access duct for fluid communication between the buried cavity and an external environment. The method envisages: forming an etching mask on the top surface at a first access area; forming a second surface layer on the top surface and on the etching mask; carrying out an etch such as to remove, in a position corresponding to the first access area, a portion of the second surface layer, and an underlying portion of the first surface layer not covered by the etching mask until the buried cavity is reached, thus forming both the first access duct and a filter element, set between the first access duct and the same buried cavity.

Abstract: A method of fabricating a fringe field switching (FFS)-liquid crystal display (LCD) device may have the following advantage. An inferior connection between the drain electrode and the pixel electrode may be prevented by preventing formation of a copper compound on the drain electrode, by performing a back channel etching after patterning a pixel electrode, and by performing a wet strip rather than a dry strip. This may result in a direct contact between copper and ITO, thereby reducing the number of mask processes.

Abstract: MEMS devices, packaged MEMS devices, and methods of manufacture thereof are disclosed. In one embodiment, a microelectromechanical system (MEMS) device includes a first MEMS functional structure and a second MEMS functional structure. An interior region of the second MEMS functional structure has a pressure that is different than a pressure of an interior region of the first MEMS functional structure.

Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor mass element configured to move in response to an applied acceleration. The mass element is defined by trenches etched into the semiconductor substrate and a cavity below the mass element. The semiconductor device includes a sensing element configured to sense movement of the mass element.

Abstract: A tunneling magnetoresistance sensor including a substrate, an insulating layer, a tunneling magnetoresistance component and an electrode array is provided. The insulating layer is disposed on the substrate. The tunneling magnetoresistance component is embedded in the insulating layer. The electrode array is formed in a single metal layer and disposed in the insulating layer either below or above the TMR component. The electrode array includes a number of separate electrodes. The electrodes are electrically connected to the tunneling magnetoresistance component to form a current-in-plane tunneling conduction mode. The tunneling magnetoresistance sensor in this configuration can be manufactured with a reduced cost and maintain the high performance at the same time.