Abstract: A lateral passive device is disclosed including a dual annular electrode. The annular electrodes form an anode and a cathode. The annular electrodes allow anode and cathode series resistances to be optimized to the lowest values at a fixed device area. In addition, the parasitic capacitance to a bottom plate (substrate) is greatly reduced. In one embodiment, a device includes a first annular electrode surrounding a second annular electrode formed on a substrate, and the second annular electrode surrounds an insulator region. A related method is also disclosed.

Abstract: A lateral DMOS device and a fabrication method therefor that may include forming a second conductive type well in a first conductive type semiconductor substrate and forming a Schottky contact in contact with the second conductive type well in a Schottky diode region, thereby preventing breakdown of the device due to high voltage.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type having a top surface and a bottom surface, a semiconductor layer of a first conductivity type formed on the top surface of the semiconductor substrate, and having an active region and an edge termination region surrounding the active region, a first semiconductor region of a second conductivity type formed in the edge termination region adjacent to an edge of the active region, a second semiconductor region of a second conductivity type buried in the edge termination region in a sheet shape or a mesh shape substantially in parallel with a surface of the semiconductor layer, a first electrode formed on the active region of the semiconductor layer and a part of the first semiconductor region, and a second electrode formed on the bottom surface of the semiconductor substrate.

Abstract: The performance of a sensor in a semiconductor device can be improved. A plurality of oscillators forming an ultrasonic sensor are arranged on a main surface of a semiconductor chip. A negative-type photosensitive insulating film which protects the oscillators is deposited on an uppermost layer of the semiconductor chip. At the time of exposure for forming an opening in the photosensitive insulating film, the semiconductor chip is divided into a plurality of exposure areas and exposed, and then, the exposure areas are jointed so that the entire area is exposed. At this time, a stitching exposure area is arranged so that a center of the stitching exposure area in a width direction in the joint portion of the adjacent exposure areas is positioned at a center of a line which connects centers of oscillators located above and below the stitching exposure area.

Abstract: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in polysilicon with a stripe shape below the gate pad electrode.

Abstract: The present invention is to provide a semiconductor laser with a feedback grating comprised of InP and AlGaInAs without InAsP put therebetween, and to provide a method for manufacturing the DFB-LD having such grating. The LD includes an n-type InP substrate, an AlInAsP intermediate layer, an AlGaInAs lower SCH layer, an active layer, and a p-type layer for upper cladding in this order from the InP substrate. The InP substrate, the AlInAsP intermediate layer, and the AlGaInAs lower SCH layer constitute the feedback grating. The AlInAsP intermediate layer lowers a series resistance along these semiconductor stacks.

Abstract: A silicon on insulator (SOI) device and methods for fabricating such a device are provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor.

Abstract: Various on-chip capacitors and methods of making the same are disclosed. In one aspect, a method of manufacturing a capacitor is provided that includes forming a first conductor structure on a semiconductor chip and forming a passivation structure on the first conductor structure. An under bump metallization structure is formed on the passivation structure. The under bump metallization structure overlaps at least a portion of the first conductor structure to provide a capacitor.

Abstract: A capacitance arrangement comprising at least one parallel-plate capacitor comprising a first electrode means, a dielectric layer and a second electrode means partly overlapping each other. A misalignment limit is given. Said first electrode means comprises a first and a second electrode arranged symmetrically with respect to a longitudinal axis, said first and second electrodes have a respective first edge, which face each other, are linear and parallel such that a gap is defined there between. Said second electrode means comprises a third electrode with a first section and a second section disposed on opposite sides of said gap interconnected by means of an intermediate section, which is delimited by a function depending on a first parameter and a second parameter. One of said two parameters is adapted to be selected hence allowing calculation of the other parameter to determine the shape and size of the second electrode means.

Abstract: A semiconductor sensor device is formed using MEMS technology by placing a thin layer of single-crystal silicon, which includes semiconductor devices, over a cavity, which has been formed in a semiconductor material. The thin layer of single-crystal silicon can be formed by forming the semiconductor devices in the top surface of a single-crystal silicon wafer, thinning the silicon wafer to a desired thickness, and then dicing the thinned wafer to form silicon layers of a desired size. The MEMS device can be used to implement a pressure sensor, microphone, temperature sensor, and a joystick.

Abstract: A multiple function thin-film resistor-capacitor array is used for an optical fiber receiving module. A dielectric thin film with desired pattern and thickness is form on surface of a silicon substrate by semiconductor manufacture process. Resistors of different resistances and capacitors of different capacitances or the combination thereof, and circuit connection therebetween can be provided by controlling the thickness and shape of thin film. The thickness of the thin-film resistor-capacitor array is adjusted by grinding to provide a substrate of a photodiode. The photodiode can be die bonded to the resistor-capacitor array with desired optical position.

Abstract: A semiconductor device with having a MOS varactor and methods of fabricating the same are disclosed. The MOS varactor includes a metal gate electrode, an active semiconductor plate interposed between the metal gate electrode and the semiconductor substrate, and a capacitor dielectric layer interposed between the metal gate electrode and the active semiconductor plate. Further, a lower insulating layer insulates the MOS varactor from the semiconductor substrate. According to the present invention, a metal gate electrode is used to reduce poly depletion, thereby increasing a tuning range of the varactor, and to manufacture a reliable metal resistor without the need of an additional photomask.

Abstract: To reduce a reverse leakage current in a Schottky barrier diode with achieving a lower forward voltage Vf and a smaller capacitance than in the related art, a Schottky barrier diode includes a semiconductor layer of a first conductivity type, a first electrode which is a metal layer forming a Schottky contact with a main surface of the semiconductor layer, a second electrode forming an ohmic contact with an opposite main surface of the semiconductor layer, a buried layer of a second conductivity type formed within the semiconductor layer so as not to be in contact with the first electrode, where the second conductivity type has a different charge carrier from the first conductivity type, and a guard ring of the second conductivity type formed within the semiconductor layer so as to be in contact with the first electrode and also to surround the buried layer without contacting with the buried layer.

Abstract: By forming a first portion of a substrate contact in an SOI device on the basis of a trench capacitor process, the overall manufacturing process for patterning contact elements may be enhanced since the contacts may only have to extend down to the level of the semiconductor layer. Since the lower portion of the substrate contact may be formed concurrently with the fabrication of trench capacitors, complex patterning steps may be avoided which may otherwise have to be introduced when the substrate contacts are to be formed separately from contact elements connecting to the device level.

Abstract: A transistor and fabricating method thereof includes sequentially forming a gate oxide layer and a poly gate over an active area of a semiconductor substrate, forming a drift region in the active area adjacent to the poly gate, and then forming a source/drain by simultaneously implanting impurity ions of various types into the drift region at a lower depth profile than that of the drift region.

Abstract: An improved solution for performing switching, routing, power limiting, and/or the like in a circuit, such as a radio frequency (RF) circuit, is provided. A semiconductor device that includes at least two electrodes, each of which forms a capacitor, such as a voltage-controlled variable capacitor, with a semiconductor channel of the device is used to perform the desired functionality in the RF circuit. The device includes electrodes that can provide high power RF functionality without the use of ohmic contacts or requiring annealing.

Abstract: An active matrix pixel device including a plurality of polycrystalline silicon islands supported by a substrate, one of the polycrystalline silicon islands providing a channel and doped source/drain regions of a thin film transistor, a PIN diode which includes a p-type doped region, and an n-type doped region separated by an amorphous silicon intrinsic region. The amorphous silicon intrinsic region overlies and contacts at least a part of one of the polycrystalline silicon islands which provides one of the p-type or n-type doped regions of the PIN diode. The doped source/drain regions and said one of the p-type or n-type doped regions of the PIN diode are provided by the same polycrystalline silicon island and a vertical n-i-p stack is used by using a doped region of a polysilicon thin film transistor (TFT) for the n-type doped region.

Abstract: A surge protection device with small-area buried regions (38, 60) to minimize the device capacitance. The doped regions (38, 60) are formed either in a semiconductor substrate (34), or in an epitaxial layer (82), and then an epitaxial layer (40, 84) is formed thereover to bury the doped regions (38, 60). The small features of the buried regions (38, 60) are maintained as such by minimizing high temperature and long duration processing of the chip. An emitter (42, 86) is formed in the epitaxial layer (40, 84).

Abstract: Provided is a method of manufacturing a semiconductor device having a switching device capable of preventing a snake current. First, a transition metal oxide layer and a leakage control layer are alternately stacked on a substrate 1 to 20 times to form a varistor layer. The transition metal oxide layer is formed to contain an excessive transition metal compared to its stable state. The leakage control layer may be formed of one selected from the group consisting of a Mg layer, a Ta layer, an Al layer, a Zr layer, a Hf layer, a polysilicon layer, a conductive carbon group layer, and a Nb layer.

Abstract: A method of manufacturing high temperature thermistors. A polycrystalline thermistor body is formed from a material selected from a list consisting of bulk polycrystalline Si with intrinsic conductivity and bulk polycrystalline Ge with intrinsic conductivity. At least one ohmic contact is formed on at least one surface of the polycrystalline thermistor body.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Various embodiments may include or exclude a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: Disclosed are a LED package, a method of fabricating the same, and a backlight unit having the same. The light emitting diode package comprises a light emitting diode, a printed circuit board provided with a circuit pattern used for driving the light emitting diode and a through hole formed in an area where the light emitting diode is mounted, and a heat sink provided in the through hole and contacted with a bottom surface of the light emitting diode.

Abstract: Capacitive decoupling circuits and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip with a first power rail for a first no-load bias level and a ground rail. A first voltage divider is electrically coupled between the first power rail and the ground rail and has a midpoint node. A first pair of capacitors is electrically coupled between the first power rail, the midpoint node and the ground rail to provide capacitive decoupling for power delivered to the first power rail. A second power rail has a second no-load bias less than the first no-load bias. A second pair of capacitors is electrically coupled between the ground rail and the second power rail to provide capacitive decoupling for power delivered to the second power rail.

Abstract: A high temperature NTC thermistor includes a polycrystalline thermistor body, selected from a list consisting of polycrystalline Si with intrinsic conductivity and polycrystalline Ge with intrinsic conductivity. At least one ohmic contact is disposed on at least one surface of the polycrystalline thermistor body.

Abstract: Methods and apparatus are provided for ESD protection of integrated passive devices (IPDs). The apparatus comprises one or more IPDs having terminals or other elements potentially exposed to ESD transients coupled by charge leakage resistances having resistance values much larger than the ordinary impedance of the IPDs at the operating frequency of interest. When the IPD is built on a semi-insulating substrate, various elements of the IPD are coupled to the substrate by spaced-apart connections so that the substrate itself provides the high value resistances coupling the elements, but this is not essential. When applied to an IPD RF coupler, the ESD tolerance increased by over 70%. The invented arrangement can also be applied to active devices and integrated circuits and to IPDs with conductive or insulating substrates.

Abstract: A low parasitic capacitance Schottky diode including a lightly doped polycrystalline silicon island that is formed on a shallow trench isolation (STI) pad such that the polycrystalline silicon island is entirely isolated from an underlying silicon substrate by the STI pad. The resulting structure reduces leakage and capacitive coupling to the substrate. Silicide contact structures are attached to lightly-doped and heavily-doped regions of the polycrystalline silicon island to form the Schottky junction and Ohmic contact, respectively, and are connected by metal structures to other components formed on the silicon substrate. The STI pad, polycrystalline silicon island, and silicide/metal contacts are formed using a standard CMOS process flow to minimize cost. A bolometer detector is provided by measuring current through the diode in reverse bias. An array of such detectors comprises an infrared or optical image sensor.

Abstract: A liquid crystal display device and a fabricating method thereof for simplifying a process and improving an aperture ratio are disclosed, including forming a first mask pattern group including a gate line, a gate electrode and a common line; forming a second mask pattern group including a semiconductor pattern and a source/drain pattern having a data line, a source electrode and a drain electrode overlapped thereon on the gate insulating film using a second mask; and forming a third mask pattern group including and a pixel electrode making an interface with the protective film in the pixel hole to be connected to the drain electrode, thereby forming a horizontal electric field with the common electrode, using a third mask.

Abstract: Pt/n?GaN Schottky barrier diodes are disclosed that are particularly suited to serve as ultra-violet sensors operating at wavelengths below 200 nm. The Pt/n?GaN Schottky barrier diodes have very large active areas, up to 1 cm2, which exhibit extremely low leakage current at low reverse biases. Very large area Pt/n?GaN Schottky diodes of sizes 0.25 cm2 and 1 cm2 have been fabricated from n?/n+ GaN epitaxial layers grown by vapor phase epitaxy on single crystal c-plane sapphire, which showed leakage currents of 14 pA and 2.7 nA, respectively for the 0.25 cm2 and 1 cm2 diodes both configured at a 0.5V reverse bias.

Abstract: A rectifying contact to an n-type oxide material and/or a substantially insulating oxide material includes a p-type oxide material. The p-type oxide material includes a copper species and a metal species, each of which are present in an amount ranging from about 10 atomic % to about 90 atomic % of total metal in the p-type oxide material. The metal species is selected from tin, zinc, and combinations thereof.

Abstract: Regio-regular polythiophenes used in diodes which are not light emitting or photovoltaic. High quality, processable thin film polymer films can be made. The thin film can have a thickness of about 50 nm to about one micron, and the conductive thin film can be applied by spin casting, drop casting, screening, ink-jetting, transfer or roll coating. The polythiophenes can be homopolymers or copolymers. The regio-regular poly(3-substitutedthiophene) can be derivatized so that the 3-substituent is an alkyl, aryl, or alkyl/aryl moiety with a heteroatom substitution in either the ?- or beta-position of the 3-substituent.

Abstract: A method of manufacturing high temperature thermistors from an ingot. The high temperature thermistors can be comprised of germanium or silicon. The high temperature thermistors have at least one ohmic contact.

Abstract: A light emitting diode (LED) and a method for fabricating the same, capable of improving brightness by forming a InGaN layer having a low concentration of indium, and whose lattice constant is similar to that of an active layer of the LED, is provided. The LED includes: a buffer layer disposed on a sapphire substrate; a GaN layer disposed on the buffer layer; a doped GaN layer disposed on the GaN layer; a GaN layer having indium disposed on the GaN layer; an active layer disposed on the GaN layer having indium; and a P-type GaN disposed on the active layer. Here, an empirical formula of the GaN layer having indium is given by In(x)Ga(1-x)N and a range of x is given by 0<x<2, and a thickness of the GaN layer having indium is 50-200 ?.

Abstract: According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a layer of silicon nitride on the first interconnect layer. The layer of silicon nitride is deposited in a deposition process using an ammonia-to-silane ratio of at least 12.5. The method further includes depositing a layer of MIM capacitor metal on the layer of silicon nitride. The method further includes etching the layer of MIM capacitor metal to form an upper electrode of the MIM capacitor. According to this exemplary embodiment, the method further includes etching the layer of silicon nitride to form a MIM capacitor dielectric segment and etching the first interconnect metal layer to form a lower electrode of the MIM capacitor. The MIM capacitor has a capacitance density of at least 2.0 fF/um2.

Abstract: Disclosed is a silicon-on-insulator-based Schottky barrier diode with a low forward voltage that can be manufactured according to standard SOI process flow. An active silicon island is formed using an SOI wafer. One area of the island is heavily-doped with an n-type or p-type dopant, one area is lightly-doped with the same dopant, and an isolation structure is formed on the top surface above a junction between the two areas. A metal silicide region contacts the lightly-doped side of the island forming a Schottky barrier. Another discrete metal silicide region contacts the heavily-doped area of the island forming an electrode to the Schottky barrier (i.e., a Schottky barrier contact). The two metal silicide regions are isolated from each other by the isolation structure. Contacts to each of the discrete metal silicide regions allow a forward and/or a reverse bias to be applied to the Schottky barrier.

Abstract: A novel, low-temperature metal deposition method which is suitable for depositing a metal film on a substrate, such as in the fabrication of metal-insulator-metal (MIM) capacitors, is disclosed. The method includes depositing a metal film on a substrate using a deposition temperature of less than typically about 270 degrees C. The resulting metal film is characterized by enhanced thickness uniformity and reduced grain agglomeration which otherwise tends to reduce the operational integrity of a capacitor or other device of which the metal film is a part. Furthermore, the metal film is characterized by intrinsic breakdown voltage (Vbd) improvement.