Abstract: A semiconductor device includes a transistor cell array in the semiconductor body of a first conductivity type. The semiconductor device further includes a first trench in the transistor cell array between transistor cells. The first trench extends into the semiconductor body from a first side and includes a pn junction diode electrically coupled to the semiconductor body at a sidewall.

Abstract: An improved diode energy converter for chemical kinetic electron energy transfer is formed using nanostructures and includes identifiable regions associated with chemical reactions isolated chemically from other regions in the converter, a region associated with an area that forms energy barriers of the desired height, a region associated with tailoring the boundary between semiconductor material and metal materials so that the junction does not tear apart, and a region associated with removing heat from the semiconductor.

Abstract: A two terminal device which can be used for the rectification of the current. Internally it has a regenerative coupling between MOS gates of opposite type and probe regions. This regenerative coupling allows to achieve performance better than that of ideal diode.

Abstract: A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.

Abstract: An electrical device includes a first layer, a second layer and an intrinsic layer. The first layer is of a first conductivity type, wherein the second layer is of a second conductivity type opposite to the first conductivity type. The intrinsic layer is arranged between the first and the second layer and has a reduced thickness at at least one portion. An area of the at least one portion is less than 50% of an active area in which the first and second layer face each other.

Abstract: High voltage diodes are disclosed. A semiconductor device is provided having a P well region; an N well region adjacent to the P well region and forming a p-n junction with the P well region; a P+ region forming an anode at the upper surface of the semiconductor substrate in the P well region; an N+ region forming a cathode at the upper surface of the semiconductor substrate in the N well region; and an isolation structure formed over the upper surface of the semiconductor substrate between the anode and the cathode and electrically isolating the anode and cathode including a first dielectric layer overlying a portion of the upper surface of the semiconductor substrate, and a second dielectric layer overlying a portion of the first dielectric layer and a portion of the upper surface of the semiconductor substrate. Methods for forming the devices are disclosed.

Abstract: A CMOS image sensor includes a substrate including silicon, a silicon germanium (SiGe) epitaxial layer formed over the substrate, the SiGe epitaxial layer formed through epitaxial growth and doped with a predetermined concentration level of impurities, an undoped silicon epitaxial layer formed over the SiGe epitaxial layer by epitaxial growth, and a photodiode region formed from a top surface of the undoped silicon epitaxial layer to a predetermined depth in the SiGe epitaxial layer.

Abstract: A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry.

Abstract: A semiconductor light emitting device made of nitride III-V compound semiconductors including an active layer made of a first nitride III-V compound semiconductor containing In and Ga, such as InGaN; an intermediate layer made of a second nitride III-V compound semiconductor containing In and Ga and different from the first nitride III-V compound semiconductor, such as InGaN; and a cap layer made of a third nitride III-V compound semiconductor containing Al and Ga, such as p-type AlGaN, which are deposited in sequential contact.

Abstract: According to one embodiment, a solid-state imaging device includes an imaging region including unit pixels which are two-dimensionally arranged on a semiconductor layer and each of which includes a photoelectric conversion unit and a signal scanning circuit unit. The unit pixel includes a transfer gate provided on the semiconductor layer, a photogate provided on the semiconductor layer, a first semiconductor layer of a first conductivity type, which is provided in the semiconductor layer below the photogate, and a second semiconductor layer of the first conductivity type, which is adjacent to the first semiconductor layer and provided in the semiconductor layer between the transfer gate and the photogate.

Abstract: The present invention relates to an apparatus combining bypass diode and wire. According to the present invention, the bypass diode can connect with the wire directly. It is not necessary to reserve an extra region on the substrate of the solar cell as the wire soldering area. Thereby, the required area of the ceramic substrate is reduced, and hence lowering the manufacturing cost of the solar cell substantially.

Abstract: Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P+ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P+-doped substrate contact in the bulk silicon layer of the SOI substrate.

Abstract: A well-through type diode element/component manufacturing method which has a pair (pairs) of first and said second electrodes of a diode element/component built on same plane by a process of metallization after a mode of well-through type to penetrate a PN junction depletion region/barrier region, and leads electrons of one of the electrodes to flow through the Depletion/Barrier region without hindrance; the present invention directly conduct the operations of insulation protecting, metallization and the process of elongate welding ball etc., it can independently complete a novel technique of Chip-Scale Package (CSP); it has the features of: grains being exactly the article produced, no need of connecting lines, low energy consumption, low cost and light, thin and small etc.

Abstract: A transistor power switch device comprising an array of vertical transistor elements for carrying current between the first and second faces of a semiconductor body and a vertical avalanche diode electrically in parallel with the array of vertical transistors. The array of transistor elements includes at the first face an array of source regions of a first semiconductor type, at least one p region of a second semiconductor type opposite to the first type interposed between the source regions and the second face, at least one control electrode for switchably controlling flow of the current through the p region, and a conductive layer contacting the source regions and insulated from the control electrode.

Abstract: An insulating layer containing a silicon peroxide radical is used as an insulating layer in contact with an oxide semiconductor layer for forming a channel. Oxygen is released from the insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the insulating layer and the oxide semiconductor layer can be reduced. Accordingly, a semiconductor device where reliability is high and variation in electric characteristics is small can be manufactured.

Abstract: A bipolar diode is provided having a drift layer of a first conductivity type on a cathode side and an anode layer of a second conductivity type on an anode side. The anode layer includes a diffused anode contact layer and a double diffused anode buffer layer. The anode contact layer is arranged up to a depth of at most 5 ?m, and the anode buffer layer is arranged up to a depth of 18 to 25 ?m. The anode buffer layer has a doping concentration between 8.0*1015 and 2.0*1016 cm?3 in a depth of 5 ?m and between 1.0*1014 up to 5.0*1014 cm?3 in a depth of 15 ?m (Split C and D), resulting in good softness of the device and low leakage current. Split A and B show anode layer doping concentrations of known diodes, which have either over all depths lower doping concentrations resulting in high leakage current or enhanced doping concentration resulting in bad softness.

Abstract: Disclosed herein are various methods of forming an anode and a cathode of a substrate diode by performing angled ion implantation processes. In one example, the method includes performing a first angled ion implantation process to form a first doped region in a bulk layer of an SOI substrate for one of the anode or the diode and, after performing the first angled ion implantation process, performing a second angled ion implantation process to form a second doped region in the bulk layer of the SOI substrate for the other of the anode and the diode, wherein said first and second angled ion implantation process are performed through the same masking layer.

Abstract: A light-emitting device package including a lead frame formed of a metal and on which a light-emitting device chip is mounted; and a mold frame coupled to the lead frame by injection molding. The lead frame includes: a mounting portion on which the light-emitting device chip is mounted; and first and second connection portions that are disposed on two sides of the mounting portion in a first direction and connected to the light-emitting device chip by wire bonding, wherein the first connection portion is stepped with respect to the mounting portion, and a stepped amount is less than a material thickness of the lead frame.

Abstract: A semiconductor structure includes a module with a plurality of die regions, a plurality of light-emitting devices disposed upon the substrate so that each of the die regions includes one of the light-emitting devices, and a lens board over the module and adhered to the substrate with glue. The lens board includes a plurality of microlenses each corresponding to one of the die regions, and at each one of the die regions the glue provides an air-tight encapsulation of one of the light-emitting devices by a respective one of the microlenses. Further, phosphor is included as a part of the lens board.

Abstract: The subject matter disclosed herein relates to formation of silicon germanium devices with tensile strain. Tensile strain applied to a silicon germanium device in fabrication may improve performance of a silicon germanium laser or light detector.

Abstract: Some embodiments include memory cells including a memory component having a first conductive material, a second conductive material, and an oxide material between the first conductive material and the second conductive material. A resistance of the memory component is configurable via a current conducted from the first conductive material through the oxide material to the second conductive material. Other embodiments include a diode comprising metal and a dielectric material and a memory component connected in series with the diode. The memory component includes a magnetoresistive material and has a resistance that is changeable via a current conducted through the diode and the magnetoresistive material.

Abstract: Embodiments of the invention relate to a camera assembly including a rear-facing camera and a front-facing camera operatively coupled together (e.g., bonded, stacked on a common substrate). In some embodiments of the invention, a system having an array of frontside illuminated (FSI) imaging pixels is bonded to a system having an array of backside illuminated (BSI) imaging pixels, creating a camera assembly with a minimal size (e.g., a reduced thickness compared to prior art solutions). An FSI image sensor wafer may be used as a handle wafer for a BSI image sensor wafer when it is thinned, thereby decreasing the thickness of the overall camera module. According to other embodiments of the invention, two package dies, one a BSI image sensor, the other an FSI image sensor, are stacked on a common substrate such as a printed circuit board, and are operatively coupled together via redistribution layers.

Abstract: A silicon carbide Schottky diode device with mesa terminations and the manufacturing method thereof are provided. The silicon carbide Schottky diode device includes an n-type epitaxial silicon carbide layer with mesa terminations on an n-type silicon carbide substrate, two p-type regions in the n-type epitaxial silicon carbide layer and a Schottky metal contact on the n-type epitaxial silicon carbide layer and the p-type regions, a dielectric layer on sidewalls and planes of the mesa terminations.

Abstract: Thermal management solutions for higher power LEDs. In accordance with embodiments, a heat sink, preferably copper, is connected directly to the thermal pad of an LED. Directly connecting the LED thermal pad to the copper heat sink reduces the thermal resistance between the LED package and the heat sink, and more efficiently conducts heat away from the LED through the copper heat sink. In embodiments, the copper heat sink is directly soldered to the LED thermal pad.

Abstract: A diode and memory device including the diode, where the diode includes a conductive portion and another portion formed of a first material that has characteristics allowing a first decrease in a resistivity of the material upon application of a voltage to the material, thereby allowing current to flow there through, and has further characteristics allowing a second decrease in the resistivity of the first material in response to an increase in temperature of the first material.

Abstract: Oxygen is released from the insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the insulating layer and the oxide semiconductor layer can be reduced. Accordingly, a semiconductor device where reliability is high and variation in electric characteristics is small can be manufactured.

Abstract: A method of manufacturing a semiconductor light emitting device made of nitride III-V compound semiconductors is includes an active layer made of a first nitride III-V compound semiconductor containing In and Ga, such as InGaN; an intermediate layer made of a second nitride III-V compound semiconductor containing In and Ga and different from the first nitride III-V compound semiconductor, such as InGaN; and a cap layer made of a third nitride III-V compound semiconductor containing Al and Ga, such as p-type AlGaN, which are deposited in sequential contact.

Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.

Abstract: A wafer-level package structure of a light emitting diode and a manufacturing method thereof, and the package structure includes: a die including a first side and a second side opposite to the first side; a first insulating layer on the first side of the die; at least two wires which are arranged on the insulating layer and electrically isolated from each other; bumps which are arranged on the wires and adapted to be electrically connected correspondingly with electrodes of a bare chip of the light emitting diode; at least two discrete lead areas on the second side of the die; and leads in the lead areas, electrically isolated from each other and electrically connected correspondingly with the wires.

Abstract: Disclosed are a light emitting device and a light emitting device package. The light emitting device includes a substrate including a plurality of patterns, each pattern including three protrusion parts, a plurality of spaces formed between the patterns, and a light emitting device structure over the patterns and the spaces. Each space includes a medium having a refractive index different from a refractive index of the light emitting device structure.

Abstract: A semiconductor thermoelectric cooler is configured to direct heat through channels of the cooler. The thermoelectric cooler has multiple electrodes and a first dielectric material positioned between side surfaces of the electrodes. A second dielectric material, different from the first dielectric material, is in contact with top surfaces of the electrodes. The first dielectric material extends above the top surface of the electrodes, separating portions of the second dielectric material, and is in contact with a portion of the top surfaces of the electrodes. The first dielectric material has a thermal conductivity different than a thermal conductivity of the second dielectric material. A ratio of the first dielectric material to the second dielectric material in contact with the top surface of the electrodes may be selected to control the heat retention. The semiconductor thermoelectric cooler may be manufactured using thin film technology.

Abstract: A method for forming a field effect power semiconductor is provided. The method includes providing a semiconductor body, a conductive region arranged next to a main surface of the semiconductor body, and an insulating layer arranged on the main horizontal surface. A narrow trench is etched through the insulating layer to expose the conductive region. A polycrystalline semiconductor layer is deposited and a vertical poly-diode structure is formed. The polycrystalline semiconductor layer has a minimum vertical thickness of at least half of the maximum horizontal extension of the narrow trench. A polycrystalline region which forms at least a part of a vertical poly-diode structure is formed in the narrow trench by maskless back-etching of the polycrystalline semiconductor layer. Further, a semiconductor device with a trench poly-diode is provided.

Abstract: In a first embodiment, a method of forming a memory cell is provided that includes (a) forming one or more layers of steering element material above a substrate; (b) etching a portion of the steering element material to form a pillar of steering element material having an exposed sidewall; (c) forming a sidewall collar along the exposed sidewall of the pillar; and (d) forming a memory cell using the pillar. Numerous other aspects are provided.

Abstract: The method for forming wavelike coherent nanostructures by irradiating a surface of a material by a homogeneous flow of ions is disclosed. The rate of coherency is increased by applying preliminary preprocessing steps.

Abstract: A light emitting device includes a substrate, a first lead frame and a second lead frame on the substrate, an installation portion electrically connected to the first lead frame or the second lead frame, the installation portion being thinner than the first lead frame or the second lead frames, a light emitting diode on the installation portion, and a conductive member electrically connecting at least one of the lead frames to the light emitting diode.

Abstract: A method of producing a radiation-emitting thin film component includes providing a substrate, growing nanorods on the substrate, growing a semiconductor layer sequence with at least one active layer epitaxially on the nanorods, applying a carrier to the semiconductor layer sequence, and detaching the semiconductor layer sequence and the carrier from the substrate by at least partial destruction of the nanorods.

Abstract: An apparatus includes a wafer with a number of openings therein. For each opening, an LED device is coupled to a conductive carrier and the wafer in a manner so that each of the coupled LED device and a portion of the conductive carrier at least partially fill the opening. A method of fabricating an LED device includes forming a number of openings in a wafer. The method also includes coupling light-emitting diode (LED) devices to conductive carriers. The LED devices with conductive carriers at least partially fill each of the openings.

Abstract: A trench semiconductor power device integrated with a Gate-Source and a Gate-Drain clamp diodes without using source mask is disclosed, wherein a plurality source regions of a first conductivity type of the trench semiconductor device and multiple doped regions of the first conductivity type of the clamp diodes are formed simultaneously through contact open areas defined by a contact mask.

Abstract: The embodiment is to provide a light emitting device and a method for manufacturing the same, in which the light emitting device includes a first conductive semiconductor layer; an active layer formed on the first conductive semiconductor layer; a second conductive semiconductor layer formed on the active layer; and a phosphor layer formed on the second conductive semiconductor layer; in which the phosphor layer includes a phosphor receiving member including a plurality of cavities and phosphor particles fixed in the cavities.

Abstract: A fast recovery diode includes an n-doped base layer having a cathode side and an anode side opposite the cathode side. A p-doped anode layer is arranged on the anode side. The anode layer has a doping profile and includes at least two sublayers. A first one of the sublayers has a first maximum doping concentration, which is between 2*1016 cm?3 and 2*1017 cm?3 and which is higher than the maximum doping concentration of any other sublayer. A last one of the sublayers has a last sublayer depth, which is larger than any other sublayer depth. The last sublayer depth is between 90 to 120 ?m. The doping profile of the anode layer declines such that a doping concentration in a range of 5*1014 cm?3 and 1*1015 cm?3 is reached between a first depth, which is at least 20 ?m, and a second depth, which is at maximum 50 ?m. Such a profile of the doping concentration is achieved by using aluminum diffused layers as the at least two sublayers.

Abstract: Provided are a novel anthracene derivative and an organic light-emitting device using the same, and more particularly, an anthracene derivative having a core (e.g., an indenoanthracene core) where an anthracene moiety with excellent device characteristics is fused with a fluorene moiety or the like with excellent fluorescent properties, wherein an aryl group is introduced at the core, and an organic light-emitting device using the anthracene derivative, which is enhanced in efficiency, operating voltage, lifetime, etc.

Abstract: Provided is a semiconductor device with a high breakdown voltage yield of a bipolar transistor and a high bandwidth and quantum efficiency of a light receiving element. An optical semiconductor device includes monolithically integrated transistor and light receiving element. The light receiving element includes a p-type semiconductor layer, an n-type epitaxial layer formed on the p-type semiconductor layer, and an n-type diffusion layer formed on the n-type epitaxial layer. An n-type impurity concentration of the n-type diffusion layer is 3×1018 cm?3 or less at a depth of 0.12 ?m or more below a surface of the n-type diffusion layer, 1×1016 cm?3 or more at a depth of 0.4 ?m or less below the surface, and 1×1016 cm?3 or less at a depth of 0.8 ?m or more below the surface, and an interface between the p-type semiconductor layer and the n-type epitaxial layer is located at a depth of 0.9 ?m to 1.5 ?m below the surface.

Abstract: A graphene substrate is doped with one or more functional groups to form an electronic device.

Abstract: A solid state imaging device includes a pixel having a photoelectric conversion element formed on a semiconductor substrate. The photoelectric conversion element includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer and forming a junction therebetween; a third semiconductor layer formed on the second semiconductor layer and having a smaller band gap energy than the second semiconductor layer, the third semiconductor layer being made of a single-crystal semiconductor and containing an impurity; and a fourth semiconductor layer of the first conductivity type covering a side surface and an upper surface of the third semiconductor layer. Provision of the fourth semiconductor layer can reduce a current flowing in dark conditions.

Abstract: A method for manufacturing a light-emitting diode includes the steps of: growing a light-emitting diode structure-forming semiconductor layer of a compound semiconductor having a zincblende crystal structure on a first substrate formed of a compound semiconductor having a zincblende crystal structure and that has a principal surface tilted in a [110] direction with respect to a (001) plane; bonding the first substrate to a second substrate on the side of the semiconductor layer; removing the first substrate so as to expose the semiconductor layer; forming an etching mask on the exposed surface of the semiconductor layer in a rectangular planar shape so that a longer side extends in a [110] or [?1-10] direction, and that a shorter side extends in a [?110] or [1-10] direction; and patterning the semiconductor layer by wet etching using the etching mask.

Abstract: Methods of forming isolation structures are disclosed. A method of forming isolation structures for an image sensor array of one aspect may include forming a dielectric layer over a semiconductor substrate. Narrow, tall dielectric isolation structures may be formed from the dielectric layer. The narrow, tall dielectric isolation structures may have a width that is no more than 0.3 micrometers and a height that is at least 1.5 micrometers. A semiconductor material may be epitaxially grown around the narrow, tall dielectric isolation structures. Other methods and apparatus are also disclosed.

Abstract: A bipolar diode is provided having a drift layer of a first conductivity type on a cathode side and an anode layer of a second conductivity type on an anode side. The anode layer includes a diffused anode contact layer and a double diffused anode buffer layer. The anode contact layer is arranged up to a depth of at most 5 ?m, and the anode buffer layer is arranged up to a depth of 18 to 25 ?m. The anode buffer layer has a doping concentration between 8.0*1015 and 2.0*1016 cm?3 in a depth of 5 ?m and between 1.0*1014 up to 5.0*1014 cm?3 in a depth of 15 ?m (Split C and D), resulting in good softness of the device and low leakage current. Split A and B show anode layer doping concentrations of known diodes, which have either over all depths lower doping concentrations resulting in high leakage current or enhanced doping concentration resulting in bad softness.

Abstract: A semiconductor diode has a first semiconductor layer (102) of a first conductivity type and a second semiconductor layer of a second conductivity type having a doping. The second semiconductor layer has a vertical electrical via region (106) which is connected to the first semiconductor layer and in which the doping is modified in such a way that the electrical via region (106) has the first conductivity type. A method for producing such a semiconductor diode is described.

Abstract: A light emitting module comprises a light emitting device (LED) mounted on a high thermal dissipation sub-mount, which performs the traditionally function of heat spread and the first part of the heat sinking. The sub-mount is a grown metal that is formed by an electroplating, electroforming, electrodeposition or electroless plating process, thereby minimizing thermal resistance at this stage. An electrically insulating and thermally conducting layer is at least partially disposed across the interface between the grown semiconductor layers of the light emitting device and the formed metal layers of the sub-mount to further improve the electrical isolation of the light emitting device from the grown sub-mount. The top surface of the LED is protected from electroplating or electroforming by a wax or polymer or other removable material on a temporary substrate, mold or mandrel, which can be removed after plating, thereby releasing the LED module for subsequent processing.

Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.