Abstract: A method of making a semiconductor device includes forming a first conductivity type polysilicon layer over a substrate, forming an insulating layer over the first conductivity type polysilicon layer, where the insulating layer comprises an opening exposing the first conductivity type polysilicon layer, and forming an intrinsic polysilicon layer in the opening over the first conductivity type polysilicon layer. A nonvolatile memory device contains a first electrode, a steering element located in electrical contact with the first electrode, a storage element having a U-shape cross sectional shape located over the steering element, and a second electrode located in electrical contact with the storage element.
Abstract: A method for fabricating an image sensor, which includes the following steps, is provided. A semiconductor substrate including a sensor array, a pad and a passivation layer is provided, and the passivation layer covers the sensor array and the pad. An opening, which comprises tapered sidewalls not perpendicular to a bared surface of the pad, is formed in the semiconductor substrate to expose the pad. An under layer is formed on the semiconductor substrate, and covers the pad and the passivation layer. A color filter array is formed on the under layer and over the corresponding sensor array. A planar layer is formed on the color filter array. A portion of the under layer is removed to expose the pad. A plurality of U-lenses is formed on the planar layer.
Abstract: A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn-junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn-junction between the first and second regions.
Abstract: A phase change memory device includes a semiconductor substrate active region, a plurality of first conductivity type silicon pillars, and a plurality of second conductivity type silicon patterns. The plurality of first conductivity type silicon pillars is formed on the semiconductor active region such that each first conductivity type silicon pillar is provided for two adjoining cells. The plurality of second conductivity type silicon patterns is formed on the plurality of first conductivity type silicon pillars such that two second conductivity type silicon patterns are formed on opposite sidewalls of each first conductivity type silicon pillars. Two adjoining cells together share only one first conductivity type silicon pillar and each adjoining cell is connected to only one second conductivity type silicon pattern which constitutes a PN diode which serves as a single switching element for each corresponding cell.
Abstract: A complementary metal oxide semiconductor (CMOS) image sensor (CIS) and a method for fabricating the same. A method for fabricating a CIS includes implanting first conductive type dopants in a semiconductor substrate to form a photodiode region in a surface of the semiconductor substrate, implanting second conductive type dopants in the photo diode region to form a second conductive type diffusion region, and implanting fluorine ions in the second conductive type diffusion region to form a fluorine diffusion region.
Abstract: Imager devices having an array of photosensors, each photosensor having at least two doped regions. The two doped regions are each independently tailored to a particular wavelength.
Type:
Grant
Filed:
August 30, 2005
Date of Patent:
April 27, 2010
Assignee:
Aptina Imaging Corporation
Inventors:
John Ladd, Inna Patrick, Gennadiy A. Agranov, Jeff A. McKee
Abstract: A dual emitting device includes a transparent substrate and an array of pixels. The array of pixels is disposed on the transparent, and each pixel of the array includes at least one first sub-pixel and at least one second sub-pixel. The first sub-pixel includes a first OLED driven by a first TFT, and a first sheltering layer on the first OLED. The second sub-pixel includes a second OLED driven by a second TFT, and a second sheltering layer formed between the transparent substrate and the second OLED.
Abstract: An image sensor module includes a semiconductor chip. Photodiode units are disposed in an active region of the semiconductor chip to convert light into electric signals. Pads are disposed in a peripheral region formed around the active region and the pads are electrically connected to the photodiode units. A connecting region is formed around the peripheral region. Re-distribution layers are electrically connected to respective pads and extend to the connecting region. A transparent substrate covers the photodiode units and the pads and exposes at least a portion of the re-distribution layers. Connecting layers are electrically connected to the respective re-distribution layers and extend to a top surface of the transparent substrate. Connecting members are connected to the respective connecting layers disposed on the top surface of the transparent substrate.
Abstract: A laser diode has a plurality of structures, each of which having a function of scattering, absorbing or reflecting stray light, disposed in a region along an optical waveguide, wherein at least one of said structures is formed in each divided region obtained by equally dividing said region along said optical waveguide into three or more parts in the longitudinal direction of said optical waveguide.
Abstract: A method of making a device includes forming at least one anodizable metal layer over at least one of an electrode or a semiconductor device, forming a plurality of pores in the anodizable metal layer by anodization of the anodizable metal layer to expose a portion of the electrode or semiconductor device, and filling at least one pore with a rewritable material such that at least some of the rewritable material is in electrical contact with the electrode or semiconductor device.
Abstract: Techniques for fabricating metal devices, such as vertical light-emitting diode (VLED) devices, power devices, laser diodes, and vertical cavity surface emitting laser devices, are provided. Devices produced accordingly may benefit from greater yields and enhanced performance over conventional metal devices, such as higher brightness of the light-emitting diode and increased thermal conductivity. Moreover, the invention discloses techniques in the fabrication arts that are applicable to GaN-based electronic devices in cases where there is a high heat dissipation rate of the metal devices that have an original non- (or low) thermally conductive and/or non- (or low) electrically conductive carrier substrate that has been removed.
Type:
Grant
Filed:
October 11, 2006
Date of Patent:
March 30, 2010
Assignee:
SemiLEDs Optoelectronics Co., Ltd.
Inventors:
Trung Tri Doan, Chuong Anh Tran, Chen-Fu Chu, Chao-Chen Cheng, Jiunn-Yi Chu, Wen-Huang Liu, Hao-Chun Cheng, Feng-Hsu Fan, Jui-Kang Yen
Abstract: The method is disclosed as applied to roughening the light-emitting surface of an LED wafer for reduction of the internal total reflection of the light generated. A masking film of silver is first deposited on the surface of a wafer to be diced into LED chips. Then the masking film is heated to cause its coagulation into discrete particles. Then, using the silver particles as a mask, the wafer surface is dry etched to create pits therein. The deposition of silver on the wafer surface and its thermal coagulation into particles may be either successive or concurrent.
Abstract: To provide a stacked photoelectric conversion device and a method for producing the same, in which an interlayer is provided between photoelectric conversion layers to obtain an effect of controlling the amount of incidence light, and carrier recombination at an interface between the interlayer and a semiconductor layer is decreased to enhance photoelectric conversion efficiency. The stacked photoelectric conversion device of the present invention comprises a plurality of silicon-based photoelectric conversion layers having a p-i-n structure stacked, wherein at least a pair of adjacent photoelectric conversion layers have an interlayer of a silicon nitride therebetween, the pair of the photoelectric conversion layers are electrically connected with each other, and a p-type silicon-based semiconductor layer constituting a part of the photoelectric conversion layer and contacting the interlayer contains a nitrogen atom.
Abstract: An improved diode energy converter for chemical kinetic electron energy transfer is formed using nanostructures and includes identifiable regions associated with chemical reactions isolated chemically from other regions in the converter, a region associated with an area that forms energy barriers of the desired height, a region associated with tailoring the boundary between semiconductor material and metal materials so that the junction does not tear apart, and a region associated with removing heat from the semiconductor.
Abstract: An active pixel using a photodiode with multiple species of N type dopants is disclosed. The pixel comprises a photodiode formed in a semiconductor substrate. The photodiode is an N? region formed within a P-type region. The N? region is formed from an implant of arsenic and an implant of phosphorus. Further, the pixel includes a transfer transistor formed between the photodiode and a floating node and selectively operative to transfer a signal from the photodiode to the floating node. Finally, the pixel includes an amplification transistor controlled by the floating node.
Abstract: A PIN diode has an n? drift layer, a p anode layer, an n buffer layer, an n+ layer, a front surface electrode and a back surface electrode. The n+ layer has an impurity concentration having a stepwise profile substantially fixed for a predetermined depth measured from a second major surface. The n buffer layer has an impurity concentration gently decreasing as seen at the n+ layer toward n? drift layer. The n? drift layer has an impurity concentration reflecting that of the semiconductor substrate and thus substantially fixed depthwise. The p anode layer has an impurity concentration relatively steeply decreasing as seen at a first major surface toward the n? drift layer. Thus there can be provided a semiconductor device that can provide characteristics, as desired, with high precision to accommodate the product applied, and a method of fabricating the semiconductor device.
Abstract: According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.
Type:
Grant
Filed:
July 24, 2007
Date of Patent:
December 29, 2009
Assignee:
Texas Instruments Incorporated
Inventors:
James D. Gallia, Srikanth Krishnan, Anand T. Krishnan
Abstract: A structure to diminish high voltage instability in a high voltage device when under stress includes an amorphous silicon layer over a field oxide on the high voltage device.
Abstract: A process is provided for fabricating a semiconductor device having a germanium nanofilm layer that is selectively deposited on a silicon substrate in discrete regions or patterns. A semiconductor device is also provided having a germanium film layer that is disposed in desired regions or having desired patterns that can be prepared in the absence of etching and patterning the germanium film layer. A process is also provided for preparing a semiconductor device having a silicon substrate having one conductivity type and a germanium nanofilm layer of a different conductivity type. Semiconductor devices are provided having selectively grown germanium nanofilm layer, such as diodes including light emitting diodes, photodetectors, and like. The method can also be used to make advanced semiconductor devices such as CMOS devices, MOSFET devices, and the like.
Type:
Application
Filed:
June 10, 2008
Publication date:
December 10, 2009
Inventors:
Sean R. McLaughlin, Narsingh Bahadur Singh, Brian Wagner, Andre Berghmans, David J. Knuteson, David Kahler, Anthony A. Margarella
Abstract: A method of manufacturing silicon nano wires including forming microgrooves on a surface of a silicon substrate, forming a first doping layer doped with a first dopant on the silicon substrate and forming a second doping layer doped with a second dopant between the first doping layer and a surface of the silicon substrate, forming a metal layer on the silicon substrate, forming catalysts by heating the metal layer within the microgrooves of the silicon substrate and growing the nano wires between the catalysts and the silicon substrate using a thermal process.
Type:
Grant
Filed:
February 27, 2006
Date of Patent:
December 1, 2009
Assignee:
Samsung Electronics Co., Ltd.
Inventors:
Byoung-lyong Choi, Wan-jun Park, Eun-kyung Lee, Jao-woong Hyun
Abstract: The present invention discloses a printed circuit board. The printed circuit board is made by the method of providing a substrate; forming a first circuit on the substrate; depositing a thin film on the substrate; building an electronic component on the substrate by the thin film and allowing the electronic component to electrically connect the first circuit; forming a blanket dielectric layer enclosing the electronic component; and removing the substrate.
Abstract: A method of growing nitride semiconductor material and particularly a method of growing Indium nitride is disclosed can increase surface flatness of a nitride semiconductor material and decrease density of V-defects therein. Further, the method can increase light emission efficiency of a quantum well or quantum dots of the produced LED as well as greatly increase yield. The method is also applicable to the fabrications of electronic devices made of nitride semiconductor material and diodes of high breakdown voltage for rectification. The method can greatly increase surface flatness of semiconductor material for HBT, thereby increasing quality of the produced semiconductor devices.
Abstract: Provided is a method for fabricating CMOS image sensor. One method includes: preparing a semiconductor substrate in which a photodiode region and a transistor region are defined; sequentially forming an insulating layer and a conductive layer on an entire surface of the semiconductor substrate; forming a photoresist pattern for a gate electrode on the conductive layer; etching the conductive layer to a predetermined thickness using the photoresist pattern as a mask; performing an ion implantation process on the etched conductive layer to form a doped conductive layer; performing an oxidation process on the resultant structure including the doped conductive layer for oxidizing the doped conductive layer so as to form an oxide layer; and removing the oxide layer and the insulating layer disposed thereunder to define a gate electrode and a gate insulating layer.
Abstract: A photo-detector, in which metal wiring for connecting electrodes is arranged on a planarized surface and thus the metal wiring arrangement is simplified, and a method of manufacturing the same are provided. The photo-detector includes a multi-layer compound semiconductor layer formed on a compound semiconductor substrate. A number of p-n junction diodes are arranged in a regular order in a selected region of the compound semiconductor layer, and an isolation region for individually isolating the p-n junction diodes is formed by implanting impurity ions in the multi-layer compound semiconductor layer. The isolation region and the surface of the compound semiconductor layer are positioned on the same level. The isolation region may be a Fe-impurity region.
Type:
Application
Filed:
April 23, 2009
Publication date:
September 24, 2009
Inventors:
Eun Soo Nam, Seon Eui Hong, Myoung Sook Oh, Yong Won Kim, Ho Young Kim, Bo Woo Kim
Abstract: A semiconductor substrate and a method of its manufacture has a semiconductor substrate having a carbon concentration in a range of 6.0×1015 to 2.0×1017 atoms/cm3, both inclusively. One principal surface of the substrate is irradiated with protons and then heat-treated to thereby form a broad buffer structure, namely a region in a first semiconductor layer where a net impurity doping concentration is locally maximized. Due to the broad buffer structure, lifetime values are substantially equalized in a region extending from an interface between the first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer to the region where the net impurity doping concentration is locally maximized. In addition, the local minimum of lifetime values of the first semiconductor layer becomes high.
Type:
Application
Filed:
February 8, 2009
Publication date:
September 10, 2009
Applicant:
FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
Abstract: A method for manufacturing a semiconductor laser device in which a first conductivity type cladding layer, and active layer, a second conductivity type first cladding layer, and a second conductivity type second cladding layer are laminated in this order on a semiconductor substrate by crystal growth, the second conductivity type second cladding layer is processed into a plurality of stripe-shaped ridge structure portions, and a laser bar is formed by cleavage in a direction orthogonal to a longitudinal direction of the ridge structure portions. According to this method, it is possible to provide a method for manufacturing a semiconductor laser device and a method for inspecting a semiconductor laser bar in the manufacturing process, capable of determining for each chip whether or not a deviation of a resonator length is within the tolerance in a simple manner.
Abstract: A method for manufacturing a photodiode array includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has a first layer of a first conductivity proximate the first main surface and a second layer of a second conductivity proximate the second main surface. A via is formed in the substrate which extends to a first depth position relative to the first main surface. The via has a first aspect ratio. Generally simultaneously with forming the via, an isolation trench is formed in the substrate spaced apart from the via which extends to a second depth position relative to the first main surface. The isolation trench has a second aspect ratio different from the first aspect ratio.
Type:
Grant
Filed:
August 10, 2007
Date of Patent:
August 25, 2009
Assignee:
Icemos Technology Ltd.
Inventors:
Robin Wilson, Conor Brogan, Hugh J. Griffin, Cormac MacNamara
Abstract: A photo sensor that is capable of generating a photo sensing signal corresponding only to ambient light by comprehending changes in electrical current depending on the change of temperature and compensating for the electrical current according the change of temperature and a flat panel display device using the photo sensor, and the photo sensor including a photo sensing unit generating a first current corresponding to an ambient light and a second current corresponding to an ambient temperature; a temperature compensating unit including a dark diode generating a third current having a same magnitude as the second current, corresponding to the ambient temperature due to block of light to be incident; and a buffer unit outputting a light sensing signal corresponding to current having the same magnitude as the first current by subtracting the third current generated in the temperature compensating unit from the second current generated in the photo sensing unit.
Type:
Application
Filed:
February 13, 2009
Publication date:
August 13, 2009
Inventors:
Do-Youb Kim, Matsueda Yojiro, Keum-Nam Kim
Abstract: A method of manufacturing an LED of high reflectivity includes forming a substrate; depositing an n-type GaN layer on the substrate; depositing an active layer on a first portion of the n-type GaN layer; attaching an n-type metal electrode to a second portion of the n-type GaN layer; depositing a p-type GaN layer on the active layer; forming a metal reflector on the p-type GaN layer; attaching a p-type metal electrode to the metal reflector; and attaching the p-type metal electrode and the n-type metal electrode to an epitaxial layer respectively. The metal reflector includes a transparent layer, an Ag layer, and an Au layer. The transparent layer and the Ag layer are formed by annealing in a furnace, and the Au layer is subsequently coated on the Ag layer.
Abstract: A method for producing a laser diode component having an electrically insulating housing basic body and electrical connecting conductors, which are led out from the housing basic body and are accessible from outside the housing basic body. The housing basic body is produced from a material which is transmissive to a laser radiation emitted by the laser diode component. The housing basic body includes a chip mounting region. A beam axis of the laser diode component runs through the housing basic body. A housing that can be produced in this way and laser diode component having a housing of this type are also disclosed.
Type:
Grant
Filed:
May 26, 2004
Date of Patent:
July 21, 2009
Assignee:
Osram Opto Semiconductors GmbH
Inventors:
Christian Ferstl, Stefan Grötsch, Markus Zeiler
Abstract: A nanowire-based device and method employ removal of residual carriers. The nanowire-based device includes a semiconductor nanowire having a semiconductor junction, and a residual carrier sink. The residual carrier sink is located at or adjacent to the semiconductor nanowire near the semiconductor junction and employs one or both of enhanced recombination and direct extraction of the residual carriers. The method includes providing a semiconductor nanowire, forming a semiconductor junction within the semiconductor nanowire, forming a residual carrier sink, and removing residual carriers from the semiconductor junction region using the residual carrier sink.
Abstract: A method of making a pillar device includes providing an insulating layer having an opening, and selectively depositing germanium or germanium rich silicon germanium semiconductor material into the opening to form the pillar device.
Abstract: A power semiconductor component and method for producing it. The component has a semiconductor base body with a first doping and a pn junction formed by a contact region having a second doping with a doping profile in the base body. The second contact region is arranged at a second surface of the base body and extends into the base body. The base body has a trench-type cutout with an edge area and a base area, wherein the base area is formed as a second partial area of the second surface, and wherein the second contact region extends from the base area via the edge area as far as a first partial area. Furthermore, the pn junction has a curvature adjacent to the edge area.
Abstract: An image sensor may comprise circuitry, a first lower electrode, a photodiode, an upper electrode, a second lower electrode, and an upper interconnection. The circuitry may comprise a first lower interconnection and a second lower interconnection over a dielectric of a substrate. The first lower electrode, the photodiode, and the upper electrode may be sequentially formed over the first lower interconnection. The second lower electrode may comprise a passivation layer over the second lower interconnection. The upper interconnection may be formed over the second lower electrode and electrically connected to the upper electrode.
Abstract: Embodiments relate to an image sensor and a method of forming an image sensor. According to embodiments, an image sensor may include a first substrate and a photodiode. A circuitry including a metal interconnection may be formed on and/or over the first substrate. The photodiode may be formed over a first substrate, and may contact the metal interconnection. The circuitry of the first substrate may include a first transistor, a second transistor, an electrical junction region, and a first conduction type region. The first and second transistors may be formed over the first substrate. According to embodiments, an electrical junction region may be formed between the first transistor and the second transistor. The first conduction type region may be formed at one side of the second transistor, and may be connected to the metal interconnection.
Type:
Application
Filed:
December 28, 2008
Publication date:
July 2, 2009
Inventors:
Hee-Sung Shim, Seoung-Hyun Kim, Joon Hwang, Kwang-Soo Kim, Jin-Su Han
Abstract: The invention provides an organic electroluminescent device and a method of manufacturing the same which conveniently reduce or suppress the transfer of ionic impurities into a light-emitting layer, and reduce or prevent the light-emitting property in the light-emitting layer from degrading, which promotes life extension. An organic electroluminescent device includes a functional layer having at least a light-emitting layer between a first electrode and a second electrode. At least a part of the functional layer is formed of the inorganic ion exchange material added to the functional material to form the functional layer.
Abstract: A laminated structure having light-emitting units is formed on a single-crystal wafer. Electrode patterns are formed on the single-crystal wafer opposite the light-emitting units. Dummy patterns are formed on the single-crystal wafer at a location spaced apart from a location opposite the light-emitting units, and offset from a desired cleavage line intersecting the light-emitting units. A scratch is formed on the desired cleavage line. The wafer is cleaved, originating on the scratch, along the cleavage line orientation, in the direction from the dummy pattern, toward the light-emitting units.
Abstract: A photo-detector, in which metal wiring for connecting electrodes is arranged on a planarized surface and thus the metal wiring arrangement is simplified, and a method of manufacturing the same are provided. The photo-detector includes a multi-layer compound semiconductor layer formed on a compound semiconductor substrate. A number of p-n junction diodes are arranged in a regular order in a selected region of the compound semiconductor layer, and an isolation region for individually isolating the p-n junction diodes is formed by implanting impurity ions in the multi-layer compound semiconductor layer. The isolation region and the surface of the compound semiconductor layer are positioned on the same level. The isolation region may be a Fe-impurity region.
Type:
Application
Filed:
December 7, 2006
Publication date:
June 4, 2009
Inventors:
Eun Soo Nam, Seon Eui Hong, Myoung Sook Oh, Yong Won Kim, Ho Young Kim, Bo Woo Kim
Abstract: A microwave switch array includes a plurality of microwave slotlines, each of which is controlled by a semiconductor switch including a first PIN junction formed by a primary P-type electrode and a primary N-type electrode separated by the slotline. The switches inject a plasma into the slotline in response to a potential applied across the first PIN junction. Each of the switches includes a second PIN junction between the primary P-type electrode and a secondary N-type electrode, and a third PIN junction between the primary N-type electrode and a secondary P-type electrode. Metal contacts connect the primary P-type electrode and the secondary N-type electrode across second PIN junction, and the primary N-type electrode and the secondary P-type electrode across the third PIN junction. The secondary electrodes extract plasma that diffuses away from the first PIN junction, thereby minimizing the performance degrading effects of plasma diffusion.
Type:
Application
Filed:
November 13, 2007
Publication date:
May 14, 2009
Inventors:
Vladimir Manasson, Vladimir I. Litvinov, Lev Sadovnik, Aramais Avakian
Abstract: A semiconductor diode includes a drift region of a first conductivity type and an anode region of a second conductivity type in the drift region such that the anode region and the drift region form a pn junction therebetween. A first highly doped silicon region of the first conductivity type extends in the drift region, and is laterally spaced from the anode region such that upon biasing the semiconductor power diode in a conducting state, a current flows laterally between the anode region and the first highly doped silicon region through the drift region. A plurality of trenches extends into the drift region perpendicular to the current flow. Each trench includes a dielectric layer lining at least a portion of the trench sidewalls and also includes at least one conductive.
Abstract: An image sensor capable of overcoming a decrease in photo sensitivity resulted from using a single crystal silicon substrate, and a method for fabricating the same are provided. An image sensor includes a single crystal silicon substrate, an amorphous silicon layer formed inside the substrate, a photodiode formed in the amorphous silicon layer, and a transfer gate formed over the substrate adjacent to the photodiode and transferring photoelectrons received from the photodiode.
Abstract: A semiconductor light-emitting device and method for manufacturing the semiconductor light-emitting device includes a mask layer etching process on first and second mask layers provided on a Group-III nitride-based compound semiconductor substrate, the mask layer with a higher etching rate being closer to the p-type semiconductor layer; a semiconductor layer etching process; a side-etching process that selectively etches the side of the mask layer with the high etching rate to define a groove portion with a portion of the p-type semiconductor layer exposed; a ZrO2 film forming process that forms a ZrO2 film so as to cover the exposed p-type semiconductor layer; an Al2O3 film forming process that forms an Al2O3 film so as to cover the ZrO2 film; a mask layer removing process; and an electrode layer forming process.
Abstract: A pixel and imager device, and method of forming the same, where the pixel has a transfer transistor gate associated with a photoconversion device and is isolated in a substrate by shallow trench isolation. The transfer transistor gate does not overlap the shallow trench isolation region.
Abstract: A method for forming an ohmic contact and a zener zap diode in an integrated circuit includes forming a first contact opening in the insulating layer over a first diffusion region to expose the semiconductor substrate; forming a barrier metal layer on the insulating layer and in the first contact opening; forming a second contact opening in the barrier metal layer over a second diffusion region and the insulating layer to expose the semiconductor substrate; forming a third contact opening in the barrier metal layer and the insulating layer over a third diffusion region to expose the semiconductor substrate; forming an aluminum layer on the barrier metal layer and the insulating layer and in the first, second and third contact openings; and patterning the aluminum layer to form the ohmic contact over the first diffusion region and the zener zap diode over the second and third diffusion regions.
Abstract: Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.
Type:
Application
Filed:
September 27, 2007
Publication date:
April 2, 2009
Inventors:
Christian Russ, Christian Pacha, Snezana Jenei, Klaus Schruefer
Abstract: A semiconductor having a an n-type material and a p-type material, wherein the n-type material and p-type material are joined to form a space-charge-free p-n junction. The energy of the Fermi-level of the n-type material is equal to the energy of the Fermi-level of the p-type material. This allows for the pre-alignment of the Fermi-levels of the n-type and the p-type materials. The semiconductor has minimal or no g-r noise. The semiconductor can be operated at TBLIP in the range of about 220° to about 240° K.
Abstract: A method of making an inorganic light emitting layer includes combining a solvent for semiconductor nanoparticle growth, a solution of core/shell quantum dots, and semiconductor nanoparticle precursor(s); growing semiconductor nanoparticles to form a crude solution of core/shell quantum dots, semiconductor nanoparticles, and semiconductor nanoparticles that are connected to the core/shell quantum dots; forming a single colloidal dispersion of core/shell quantum dots, semiconductor nanoparticles, and semiconductor nanoparticles that are connected to the core/shell quantum dots; depositing the colloidal dispersion to form a film; and annealing the film to form the inorganic light emitting layer.
Abstract: An image sensor and a manufacturing method thereof are provided. The sensor includes a substrate, a bottom electrode, an intrinsic layer and a first conductive layer formed over the substrate, a diffusion barrier film formed over the first conductive layer, and an upper transparent electrode formed over the diffusion barrier film. Therefore, a vertical integration of a transistor circuitry and a photodiode can be provided. Further, the leakage current is prevented and the photosensitivity is increased by performing the plasma treatment on the first conductive layer. Due to the vertically integrated transistor circuitry and photodiode, the fill factor can approach 100%, and higher sensitivity compared with the related art having the same pixel size can be provided. The sensitivity of each unit pixel is not reduced, even though more complex circuitry is realized on the image sensor.
Abstract: A solid state imaging device includes a pixel having a photoelectric conversion element formed on a semiconductor substrate. The photoelectric conversion element includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer and forming a junction therebetween; a third semiconductor layer formed on the second semiconductor layer and having a smaller band gap energy than the second semiconductor layer, the third semiconductor layer being made of a single-crystal semiconductor and containing an impurity; and a fourth semiconductor layer of the first conductivity type covering a side surface and an upper surface of the third semiconductor layer. Provision of the fourth semiconductor layer can reduce a current flowing in dark conditions.