Abstract: Semiconductor devices including at least one diode over a conductive strap. The semiconductor device may include at least one conductive strap over an insulator material, at least one diode comprising a single crystalline silicon material over a conductive material, and a memory cell on the at least one diode. The at least one diode may be formed from a single crystalline silicon material. Methods of forming such semiconductor devices are also disclosed.

Abstract: A light source with enhanced brightness includes an angle-selective optical filter and a light emitting diode (LED) having a high reflective layer. The angle-selective filter is located on the top surface of emitting diode to pass lights at specified angles. According to one embodiment, the angle-selective filter includes index-alternating layers. With a reflective polarizer, the light source can produce polarized light with enhanced brightness.

Abstract: Provided are a method of fabricating a semiconductor device and an electronic system. The method of fabricating a semiconductor device includes forming a well impurity region, a lower impurity region and an upper impurity region in a semiconductor substrate. The lower impurity region has a different conductivity type than a conductivity type of the well impurity region, the upper impurity region has a different conductivity type than the conductivity type of the lower impurity region, and the upper impurity region has a same conductivity type as the conductivity type of the well impurity region and has a higher impurity concentration than an impurity concentration of the well impurity region.

Abstract: A TFD (21) includes: a glass substrate (10); a polysilicon layer (12a) formed on the glass substrate (10), and including a p-type semiconductor region (12ap) and an n-type semiconductor region (12an) which are both formed in a same plane and doped with impurity ions; and an insulating film (13) provided to cover the polysilicon layer (12a). In at least one of the p-type semiconductor region (12ap) or the n-type semiconductor region (12an), the concentration of the impurity ions in a multilayer of the polysilicon layer (12a) and the insulating film (13) along the thickness of the multilayer reaches a peak concentration in the insulating film (13) or in a portion of the polysilicon layer (12a) located between the midpoint of the thickness of the polysilicon layer (12a) and the insulating film (13).

Abstract: In a first embodiment, a method of forming a memory cell is provided that includes (a) forming one or more layers of steering element material above a substrate; (b) etching a portion of the steering element material to form a pillar of steering element material having an exposed sidewall; (c) forming a sidewall collar along the exposed sidewall of the pillar; and (d) forming a memory cell using the pillar. Numerous other aspects are provided.

Abstract: A nonvolatile memory cell including a storage element in series with a diode steering element. At least one interface of the diode steering element is passivated.

Abstract: Example embodiments may provide methods of manufacturing an image sensor. Example methods of manufacturing an image sensor may include forming a photoelectric converter in a semiconductor substrate, forming an interlayer insulating film covering a surface of the semiconductor substrate, forming metal wires and an inter-metal insulating film filling between the metal wires on the interlayer insulating film, forming openings above the photoelectric converter by removing a part of the inter-metal insulating film and the interlayer insulating film, curing the surface above the photoelectric converter by irradiating light into the openings, and/or forming a light transmitter filling the openings.

Abstract: This invention relates to imaging device and its related transferring technologies to independent substrate able to attain significant broadband capability covering the wavelengths from ultra-violet (UV) to long-Infrared. More particularly, this invention is related to the broadband image sensor (along with its manufacturing technologies), which can detect the light wavelengths ranges from as low as UV to the wavelengths as high as 20 ?m covering the most of the wavelengths using of the single monolithic image sensor on the single wafer. This invention is also related to the integrated circuit and the bonding technologies of the image sensor to standard integrated circuit for multicolor imaging, sensing, and advanced communication. Our innovative approach utilizes surface structure having more than micro-nano-scaled 3-dimensional (3-D) blocks which can provide broad spectral response.

Abstract: A Schottky or PN diode is formed where a first cathode portion is an N epitaxial layer that is relatively lightly doped. An N+ buried layer is formed beneath the cathode for conducting the cathode current to a cathode contact. A more highly doped N-well is formed, as a second cathode portion, in the epitaxial layer so that the complete cathode comprises the N-well surrounded by the more lightly doped first cathode portion. An anode covers the upper areas of the first and second cathode portions so both portions conduct current when the diode is forward biased. When the diode is reverse biased, the depletion region in the central N-well will be relatively shallow but substantially planar so will have a relatively high breakdown voltage. The weak link for breakdown voltage will be the curved edge of the deeper depletion region in the lightly doped first cathode portion under the outer edges of the anode. Therefore, the N-well lowers the on-resistance without lowering the breakdown voltage.

Abstract: Methods of forming high-current density vertical p-i-n diodes on a substrate are described. The methods include the steps of concurrently combining a group-IV-element-containing precursor with a sequential exposure to an n-type dopant precursor and a p-type dopant precursor in either order. An intrinsic layer is deposited between the n-type and p-type layers by reducing or eliminating the flow of the dopant precursors while flowing the group-IV-element-containing precursor. The substrate may reside in the same processing chamber during the deposition of each of the n-type layer, intrinsic layer and p-type layer and the substrate is not exposed to atmosphere between the depositions of adjacent layers.

Abstract: A light emitting diode (LED) and a method of making the same are disclosed. The present invention uses a metal layer of high conductivity and high reflectivity to prevent the substrate from absorbing the light emitted. This invention also uses the bonding technology of dielectric material thin film to replace the substrate of epitaxial growth with high thermal conductivity substrate to enhance the heat dissipation of the chip, thereby increasing the performance stability of the LED, and making the LED applicable under higher current.

Abstract: A translucent solar cell and a manufacturing method thereof are provided. The translucent solar cell at least includes a substrate, a front electrode layer, a photoconductive layer, and a back electrode layer stacked in order. Therein, a plurality of apertures are formed on the front electrode layer. In addition, a plurality of light-transmissive regions are formed on the back electrode layer and further extended in a depth direction so as to reach the plurality of apertures on the front electrode layer. Thus, the projected area of each light-transmissive region is within and smaller than that of the corresponding aperture.

Abstract: A method of forming an imaging array includes providing a single crystal silicon substrate having an internal separation layer, forming a patterned conductive layer proximate a first side of the single crystal silicon substrate, forming an electrically conductive layer on the first side of the single crystal silicon substrate and in communication with the patterned conductive layer, securing the single crystal silicon substrate having the patterned conductive layer and electrically conductive layer formed thereon to a glass substrate with the first side of the single crystal silicon substrate proximate the glass substrate, separating the single crystal silicon substrate at the internal separation layer to create an exposed surface opposite the first side of the single crystal silicon substrate and forming an array comprising a plurality of photosensitive elements and readout elements on the exposed surface.

Abstract: Cobalt silicide (CoSi2) Schottky diodes fabricated per the current art suffer from excess leakage currents in reverse bias. In this invention, an floating p-type region encircles each anode of a CoSi2 Schottky diode comprising of one or more CoSi2 anodes. The resulting p-n junction forms a depletion region under the Schottky junction that reduces leakage current through the Schottky diodes in reverse bias operation.

Abstract: The embodiment is to provide a light emitting device and a method for manufacturing the same, in which the light emitting device includes a first conductive semiconductor layer; an active layer formed on the first conductive semiconductor layer; a second conductive semiconductor layer formed on the active layer; and a phosphor layer formed on the second conductive semiconductor layer; in which the phosphor layer includes a phosphor receiving member including a plurality of cavities and phosphor particles fixed in the cavities.

Abstract: Methods for forming a bipolar junction transistor device are described herein. A method for forming the bipolar junction transistor device may include doping a first portion of a substrate with a first dopant to form a base pick-up region, and after doping the first portion of the substrate, doping a second portion of the substrate with a second dopant to form at least one emitter region. A bipolar junction transistor device may include a floating collector, in which case the bipolar junction transistor device may be operated as a diode for improved emitter current.

Abstract: A diode and memory device including the diode, where the diode includes a conductive portion and another portion formed of a first material that has characteristics allowing a first decrease in a resistivity of the material upon application of a voltage to the material, thereby allowing current to flow there through, and has further characteristics allowing a second decrease in the resistivity of the first material in response to an increase in temperature of the first material.

Abstract: An indirect connection to and across a photodiode array. The backside contact is used as one portion which connects to a capacitor. The capacitor forms a shunt across the bulk substrate, thus shunting across the series resistance of the substrate, and reducing the series resistance.

Abstract: A method for manufacturing a photodiode array includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has a first layer of a first conductivity proximate the first main surface and a second layer of a second conductivity proximate the second main surface. A via is formed in the substrate which extends to a first depth position relative to the first main surface. The via has a first aspect ratio. Generally simultaneously with forming the via, an isolation trench is formed in the substrate spaced apart from the via which extends to a second depth position relative to the first main surface. The isolation trench has a second aspect ratio different from the first aspect ratio.

Abstract: A semiconductor p-i-n diode and method for forming the same are described herein. In one aspect, a SiGe region is formed between a region doped to have one conductivity (either p+ or n+) and an electrical contact to the p-i-n diode. The SiGe region may serve to lower the contact resistance, which may increase the forward bias current. The doped region extends below the SiGe region such that it is between the SiGe region and an intrinsic region of the diode. The p-i-n diode may be formed from silicon. The doped region below the SiGe region may serve to keep the reverse bias current from increasing as result of the added SiGe region. In one embodiment, the SiGe is formed such that the forward bias current of an up-pointing p-i-n diode in a memory array substantially matches the forward bias current of a down-pointing p-i-n diode which may achieve better switching results when these diodes are used with the R/W material in a 3D memory array.

Abstract: Provides is a semiconductor light-emitting device. The semiconductor light-emitting device includes a first conduction-type cladding layer, an active layer, and a second conduction-type cladding layer, on a substrate. Portions of the substrate and the first conduction-type cladding layer are removed. According to the light-emitting device having the above-construction, damage to a grown epitaxial layer is reduced, and a size of an active layer increases, so that a light-emission efficiency increases. Even when a size of a light-emitting device is small, a short-circuit occurring between electrodes can be prevented. Further, brightness and reliability of the light-emitting device are improved.

Abstract: Provided are a method of manufacturing an organic light emitting device. The method includes forming an electron injection layer by vacuum co-depositing an organic semiconductor material having an electron mobility of about 1×10?6 cm2/V·s or more in an electric field of about 1×106 V/m and a metal azide.

Abstract: Provided is an image sensor and a method for manufacturing the same. In the image sensor, a first substrate has a lower metal line and circuitry thereon. A crystalline semiconductor layer contacts the lower metal line and is bonded to the first substrate. A photodiode is provided in the crystalline semiconductor layer and electrically connected with the lower metal line. A pixel isolation layer is formed in regions of the photodiode.

Abstract: Disclosed are a light emitting device and a method for manufacturing the same. The light emitting device includes a substrate having a lead frame, a light emitting diode mounted on the substrate, a mold member formed on the substrate and the light emitting diode, and a reflecting member having an opening portion at one side thereof and being inclined at an outer portion of the mold member.

Abstract: A color unit is disclosed in which is included in an imaging device. The color unit includes; a first p-type electrode layer disposed on a light receiving side of the color unit, and including a light-absorptive organic material which selectively absorbs a wavelength other than a desired wavelength in a visible light band of the electromagnetic spectrum, a second p-type electrode layer disposed under the first p-type electrode layer and including a light-absorptive organic material which absorbs a desired wavelength and an n-type electrode layer disposed under the second p-type electrode layer and including an organic material, wherein photoelectric conversion is performed through a p-n junction between the second p-type electrode layer and the n-type electrode layer and light of the desired wavelength is converted into electrical current.

Abstract: A semiconductor light detecting element having a mesa structure comprises: a first semiconductor layer having n-type conductivity located on a semiconductor substrate, a light absorbing layer located on the first semiconductor layer, and a second semiconductor layer located on the light absorbing layer; a burying layer burying peripheries of the light absorbing layer and the second semiconductor layer. The burying layer has a band gap larger than the band gap of the light absorbing layer. The second semiconductor layer has a first region having p-type conductivity, and a second region having i-type or n-type conductivity and located between the first region and the burying layer.

Abstract: A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.

Abstract: Provided is an image sensor and method for manufacturing the same. In the image sensor, a first substrate has a lower metal line and a circuitry thereon. A crystalline semiconductor layer contacts the lower metal line and is bonded to the first substrate. A photodiode is provided in the crystalline semiconductor layer and electrically connected with the lower metal line. A light shielding layer is formed in regions of the photodiode.

Abstract: In some aspects, a method of forming a memory cell is provided that includes (1) forming a first conductor above a substrate; (2) forming a diode above the first conductor; (3) forming a reversible resistance-switching element above the first conductor using a selective deposition process; and (4) forming a second conductor above the diode and the reversible resistance-switching element. Numerous other aspects are provided.

Abstract: A diode for fast switching applications includes a base layer of a first conductivity type with a first main side and a second main side opposite the first main side, an anode layer of a second conductivity type, which is arranged on the second main side, a plurality of first zones of the first conductivity type with a higher doping concentration than the base layer, and a plurality of second zones of the second conductivity type. The first and second zones are arranged alternately on the first main side. A cathode electrode is arranged on top of the first and second zones on the side of the zones which lies opposite the base layer, and a anode electrode is arranged on top of the anode layer on the side of the anode layer which lies opposite the base layer. The base layer includes a first sublayer, which is formed by the second main sided part of the base layer, and a second sublayer, which is formed by the first main sided part of the base layer.

Abstract: In a phase change memory, electric property of a diode used as a selection device is extremely important. However, since crystal grain boundaries are present in the film of a diode using polysilicon, it involves a problem that the off leak property varies greatly making it difficult to prevent erroneous reading. For overcoming the problem, the present invention provides a method of controlling the temperature profile of an amorphous silicon in the laser annealing for crystallizing and activating the amorphous silicon thereby controlling the crystal grain boundaries. According to the invention, variation in the electric property of the diode can be decreased and the yield of the phase-change memory can be improved.

Abstract: A lateral passive device is disclosed including a dual annular electrode. The annular electrodes form an anode and a cathode. The annular electrodes allow anode and cathode series resistances to be optimized to the lowest values at a fixed device area. In addition, the parasitic capacitance to a bottom plate (substrate) is greatly reduced. In one embodiment, a device includes a first annular electrode surrounding a second annular electrode formed on a substrate, and the second annular electrode surrounds an insulator region. A related method is also disclosed.

Abstract: A method for wafer-to-wafer bonding of a sensor readout circuitry separately fabricated with a silicon substrate to a photodiode device made of non-silicon materials grown from a separate substrate. In preferred embodiments the non-silicon materials are epitaxially grown on a silicon wafer. The bonding technique of preferred embodiments of the present invention utilizes lithographically pre-fabricated metallic interconnects to connect each of a number of pixel circuits on a readout circuit wafer to each of a corresponding number of pixel photodiodes on a photodiode wafer. The metallic interconnects are extremely small (with widths of about 2 to 4 microns) compared to prior art bump bonds with the solder balls of diameter typically larger than 20 microns. The present invention also provides alignment techniques to assure proper alignment of the interconnects during the bonding step.

Abstract: A semiconductor integrated circuit having a diode element includes a diffusion layer which constitutes the anode and two diffusion layers which are provided on the left and right sides of the anode and which constitute the cathode, such that the anode and the cathode constitute the diode. A well contact is provided to surround both the diffusion layers of the anode and cathode. Distance tS between a longer side of the well contact and the diffusion layers of the cathode is shorter, while distance tL between a shorter side of the well contact and the diffusion layers of the anode and cathode is longer (tL>tS). Accordingly, the resistance value between the diffusion layer of the anode and the shorter side of the well contact is larger, so that the current from the diffusion layer of the anode is unlikely to flow toward the shorter side of the well contact.

Abstract: A semiconductor patch antenna for microwave radiation having a wide pin-junction or pn-junction with the depletion region or embodiments having a separating buried oxide (SiO2) layer between p- and n-doped regions as the natural resonator volume. Embodiments that do not include a metal ground plane and/or a metal patch are disclosed.

Abstract: A switching element for a memory device includes a base layer including a plurality of line-type trenches. First insulation patterns are formed on the base layer excluding the trenches. First diode portions are formed on the bottoms of the trenches in the form of a thin film. Second insulation patterns are formed on the first diode portions and are spaced apart from each other to form holes in the trenches having the first diode portions provided therein. Square pillar-shaped second diode portions are formed in the holes over the first diode portions.

Abstract: Methods for forming a bipolar junction transistor device are described herein. A method for forming the bipolar junction transistor device may include doping a first portion of a substrate with a first dopant to form a base pick-up region, and after doping the first portion of the substrate, doping a second portion of the substrate with a second dopant to form at least one emitter region. A bipolar junction transistor device may include a floating collector, in which case the bipolar junction transistor device may be operated as a diode for improved emitter current.

Abstract: A lateral DMOS device and a fabrication method therefor that may include forming a second conductive type well in a first conductive type semiconductor substrate and forming a Schottky contact in contact with the second conductive type well in a Schottky diode region, thereby preventing breakdown of the device due to high voltage.

Abstract: In a SiGe BJT process, a diode is formed by defining a p-n junction between the BJT collector and BJT internal base, blocking the external gate regions of the BJT and doping the emitter poly of the BJT with the same dopant type as the internal base thereby using the emitter contact to define the contact to the internal base. Electrical contact to the collector is established through a sub-collector or by means of a second emitter poly and internal base both doped with the same dopant type as the collector.

Abstract: Provided are an oxide diode, a method of fabricating the oxide diode, and an electronic device including the oxide diode. The oxide diode may include an n-type oxide layer treated with plasma, and a p-type oxide layer on the n-type oxide layer. The plasma may include nitrogen.

Abstract: A microwave switch array includes a plurality of microwave slotlines, each of which is controlled by a semiconductor switch including a first PIN junction formed by a primary P-type electrode and a primary N-type electrode separated by the slotline. The switches inject a plasma into the slotline in response to a potential applied across the first PIN junction. Each of the switches includes a second PIN junction between the primary P-type electrode and a secondary N-type electrode, and a third PIN junction between the primary N-type electrode and a secondary P-type electrode. Metal contacts connect the primary P-type electrode and the secondary N-type electrode across second PIN junction, and the primary N-type electrode and the secondary P-type electrode across the third PIN junction. The secondary electrodes extract plasma that diffuses away from the first PIN junction, thereby minimizing the performance degrading effects of plasma diffusion.

Abstract: A piezo thin-film diode (piezo-diode) cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method deposits thin-films overlying a substrate. The substrate can be made of glass, polymer, quartz, metal foil, Si, sapphire, ceramic, or compound semiconductor materials. Amorphous silicon (a-Si), polycrystalline Si (poly-Si), oxides, a-Site, poly-SiGe, metals, metal-containing compounds, nitrides, polymers, ceramic films, magnetic films, and compound semiconductor materials are some examples of thin-film materials. A cantilever beam is formed from the thin-films, and a diode is embedded with the cantilever beam. The diode is made from a thin-film shared in common with the cantilever beam. The shared thin-film may a film overlying a cantilever beam top surface, a thin-film overlying a cantilever beam bottom surface, or a thin-film embedded within the cantilever beam.

Abstract: A photonic device comprises a substrate and a dielectric material including two or more openings that expose a portion of the substrate, the two or more openings each having an aspect ratio of at least 1. A bottom diode material comprising a compound semiconductor material that is lattice mismatched to the substrate occupies the two or more openings and is coalesced above the two or more openings to form the bottom diode region. The device further includes a top diode material and an active diode region between the top and bottom diode materials.

Abstract: A nitride-based semiconductor device includes a diode provided on a semiconductor substrate. The diode contains a first nitride-based semiconductor layer made of non-doped AlXGa1-XN (0?X<1); a second nitride-based semiconductor layer made of non-doped or n-type AlYGa1-YN (0<Y?1, X<Y) having a lattice constant smaller than that of the first nitride-based semiconductor layer; a first electrode formed on the second nitride-based semiconductor layer; a second electrode formed on the second nitride-based semiconductor layer; and an insulating film that covers the second nitride-based semiconductor layer below a peripheral portion of the first electrode. In the diode, a recess structure portion is formed at a position near the peripheral portion of the first electrode on the second nitride-based semiconductor layer, and the first electrode covers the second nitride-based semiconductor layer and at least a part of the insulating film.

Abstract: Methods for fabricating CMOS image sensor devices are provided, wherein active pixel sensors are constructed with non-planar transistors having vertical gate electrodes and channels, which minimize the effects of image lag and dark current.

Abstract: A diode is provided. The diode includes first and second diffusion layers formed in a substrate, a first metal coupled to the first diffusion layer, and a second metal coupled to the second diffusion layer that has width that is smaller than a width of the second diffusion layer.

Abstract: A positive-intrinsic-negative (PIN)/negative-intrinsic-positive (NIP) diode includes a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate is of a first conductivity. The PIN/NIP diode includes at least one trench formed in the first main surface which defines at least one mesa. The trench extends to a first depth position in the semiconductor substrate. The PIN/NIP diode includes a first anode/cathode layer proximate the first main surface and the sidewalls and the bottom of the trench. The first anode/cathode layer is of a second conductivity opposite to the first conductivity. The PIN/NIP diode includes a second anode/cathode layer proximate the second main surface, a first passivation material lining the trench and a second passivation material lining the mesa. The second anode/cathode layer is the first conductivity.

Abstract: Memory devices are described along with methods for manufacturing. A memory device as described herein includes a first electrode and a second electrode. The memory device further includes a diode and an anti-fuse metal-oxide memory element comprising aluminum oxide and copper oxide. The diode and the metal-oxide memory element are arranged in electrical series between the first electrode and the second electrode.

Abstract: A semiconductor light detecting element having a mesa structure comprises: a first semiconductor layer having n-type conductivity located on a semiconductor substrate, a light absorbing layer located on the first semiconductor layer, and a second semiconductor layer located on the light absorbing layer; a burying layer burying peripheries of the light absorbing layer and the second semiconductor layer. The burying layer has a band gap larger than the band gap of the light absorbing layer. The second semiconductor layer has a first region having p-type conductivity, and a second region having i-type or n-type conductivity and located between the first region and the burying layer.

Abstract: A diode structure fabrication method. In a P? substrate, an N+ layer is implanted. The N+ layer has an opening whose size affects the breakdown voltage of the diode structure. Upon the N+ layer, an N? layer is formed. Then, a P+ region is formed to serve as an anode of the diode structure. An N+ region can be formed on the surface of the substrate to serve as a cathode of the diode structure. By changing the size of the opening in the N+ layer during fabrication, the breakdown voltage of the diode structure can be changed (tuned) to a desired value.