Abstract: A method of forming a current mirror device for an integrated circuit includes configuring a reference current source; forming a first field effect transistor (FET) in series with the reference current source, the first FET of a first conductivity type formed on a first portion of a substrate having a first crystal lattice orientation; and forming a second FET of the first conductivity type on a second portion of the substrate having a second crystal lattice orientation, with a gate terminal of the first FET coupled to a gate terminal of the second FET, and the gate terminals of the first and second FETs coupled to the reference current source; wherein the carrier mobility of the first FET formed on the first portion of the substrate is different than the carrier mobility of the second FET formed on the second portion of the substrate.

Abstract: An array substrate includes a base substrate, a switching element, and a pixel electrode. The switching element is on the base substrate. The switching element includes a poly silicon pattern having at least one block. Grains are formed in each of the at least one block that are extended in a plurality of directions. The pixel electrode is electrically connected to the switching element. Therefore, current mobility and design margin of the switching element are improved.

Abstract: A structure and a method for forming the same. The structure includes (a) a substrate, (b) a semiconductor fin region on top of the substrate, (c) a gate dielectric region on side walls of the semiconductor fin region, and (d) a gate electrode region on top and on side walls of the semiconductor fin region. The gate dielectric region (i) is sandwiched between and (ii) electrically insulates the gate electrode region and the semiconductor fin region. The structure further includes a first spacer region on a first side wall of the gate electrode region. A first side wall of the semiconductor fin region is exposed to a surrounding ambient. A top surface of the first spacer region is coplanar with a top surface of the gate electrode region.

Abstract: In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region, a portion of the semiconductor substrate in the cell region and in the peripheral circuit region including an isolation region defining an active region, a portion of the active region protruding above an upper surface of the isolation region to define at least two active channels, a gate dielectric layer formed over the active region of the semiconductor substrate including the at least two protruding active channels, a gate electrode formed over the gate dielectric layer and the isolation region of the semiconductor substrate, and a source/drain region formed in the active region of the semiconductor substrate on either side of the gate electrode.

Abstract: An array substrate includes a substrate, a gate line on the substrate, a data line crossing the gate line to define a pixel region, a thin film transistor connected to the gate and data lines, a pixel electrode in the pixel region, and a common electrode including first, second, third, fourth and fifth portions, wherein the first and second portions are disposed at both sides of the data line, each of the third and fourth portions is connected to the first and second portions, and the fifth portion is connected to the second portion and is extended into a next pixel region adjacent to the pixel region.

Abstract: A method of manufacturing a semiconductor device contact including forming an insulating layer over a substrate and forming an agglutinating layer over the insulating layer. The agglutinating layer is then exposed to a plasma treatment. A barrier layer is formed over the plasma-treated agglutinating layer, and a conductive layer is formed over the barrier layer.

Abstract: A field effect transistor and a method of fabricating the field effect transistor. The field effect transistor includes: a silicon body, a perimeter of the silicon body abutting a dielectric isolation; a source and a drain formed in the body and on opposite sides of a channel formed in the body; and a gate dielectric layer between the body and an electrically conductive gate electrode, a bottom surface of the gate dielectric layer in direct physical contact with a top surface of the body and a bottom surface the gate electrode in direct physical contact with a top surface of the gate dielectric layer, the gate electrode having a first region having a first thickness and a second region having a second thickness, the first region extending along the top surface of the gate dielectric layer over the channel region, the second thickness greater than the first thickness.

Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.

Abstract: A semiconductor device and manufacturing method thereof capable of improving an operating speed of a MOSFET using an inexpensive structure. The method comprises the steps of forming a stress film to cover a source, drain, sidewall insulating layer and gate of the MOSFET and forming in the stress film a slit extending from the stress film surface toward the sidewall insulating layer. As a result, an effect of allowing local stress components in the stress films on the source and the drain to be relaxed by local stress components in the stress film on the gate is suppressed by the slit.

Abstract: Disclosed are embodiments a technique for inducing strain into the polysilicon gate of a non-planar FET (e.g., a finFET or trigate FET) in order to impart a similar strain on the FET channel region, while simultaneously protecting the source/drain regions of the semiconductor fin. Specifically, a protective cap layer is formed above the source/drain regions of the fin in order to protect those regions during a subsequent amporphization ion implantation process. The fin is further protected, during this implantation process, because the ion beam is directed towards the gate in a plane that is parallel to the fin and tilted from the vertical axis. Thus, amorphization of the fin and damage to the fin are limited. Following the implantation process and the formation of a straining layer, a recrystallization anneal is performed so that the strain of the straining layer is ‘memorized’ in the polysilicon gate.

Abstract: A method of fabricating a titanium silicide nitride (TiSiN) layer of a semiconductor device may include forming a gate electrode on a semiconductor substrate and forming spacers on sidewalls of the gate electrode, forming a source and a drain in the semiconductor substrate, and forming TiSiN layers on the gate electrode and the source and the drain, respectively. Further, a semiconductor device may include a gate electrode, a spacer formed on sidewalls of the gate electrode, a source and a drain, wherein TiSiN layers are formed on the gate electrode, the source and the drain, respectively.

Abstract: A method of manufacturing a thin TFT over a flexible substrate is provided. In formation of a TFT on a surface of a substrate having heat resistance, a liquid repellent film is formed selectively on a surface of the substrate, and an organic film is formed thereover. An element such as a TFT is formed over the organic film. Since the liquid repellent film is formed over the substrate, adhesion between the substrate and the organic film is low; therefore, the element which is formed can be peeled off from the substrate easily. Further, since the element is not transferred to another substrate, a semiconductor device which is thinner than conventional ones can be manufactured. In order to form the liquid repellent film selectively, light exposure of a front surface or a back surface of the substrate provided with a mask, a droplet discharging method, or the like is used.

Abstract: A semiconductor substrate is patterned to form a depression and prominence. A floating gate is formed so as to cover at least both sidewalls of the prominence of the depression and prominence, and is then etched to form a trench for a device isolation self-aligned with the floating gate. Related structures are also described.

Abstract: The invention includes methods for forming electrical connections associated with semiconductor constructions. A semiconductor substrate is provided which has a conductive line thereover, and which has at least two diffusion regions adjacent the conductive line. A patterned etch stop is formed over the diffusion regions. The patterned etch stop has a pair of openings extending through it, with the openings being along a row substantially parallel to an axis of the line. An insulative material is formed over the etch stop. The insulative material is exposed to an etch to form a trench within the insulative material, and to extend the openings from the etch stop to the diffusion regions. At least a portion of the trench is directly over the openings and extends along the axis of the line. An electrically conductive material is formed within the openings and within the trench.

Abstract: A semiconductor device provides a gate structure that includes a conductive portion and a high-k dielectric material formed beneath and along sides of the conductive material. An additional gate dielectric material such as a gate oxide may be used in addition to the high-k dielectric material. The method for forming the structure includes forming an opening in an organic material, forming the high-k dielectric material and a conductive material within the opening and over the organic material then using chemical mechanical polishing to remove the high-k dielectric material and conductive material from regions outside the gate region.

Abstract: A potassium/sodium ion sensing device applying an extended-gate field effect transistor, which using an extended-gate ion sensitive field effect transistor (EGFET) as base to fabricate a potassium/sodium ion sensing device, using the extended gate of the extended-gate ion sensitive field effect transistor as a signal intercept electrode, and immobilizing the hydro-aliphatic urethane diacrylate (EB2001) intermixed with electronegative additive, potassium ionophore, sodium ionophore, and the like, to fabricate a potassium/sodium ion sensing electrode. The present invention utilizes the photocurability and good hydrophilicity of the hydro-aliphatic urethane diacrylate (EB2001), and fixes potassium/sodium ionophore, can obtain a non-wave filter, single-layer, stable signal potassium and sodium ion sensor.

Abstract: The invention includes methods for forming electrical connections associated with semiconductor constructions. A semiconductor substrate is provided which has a conductive line thereover, and which has at least two diffusion regions adjacent the conductive line. A patterned etch stop is formed over the diffusion regions. The patterned etch stop has a pair of openings extending through it, with the openings being along a row substantially parallel to an axis of the line. An insulative material is formed over the etch stop. The insulative material is exposed to an etch to form a trench within the insulative material, and to extend the openings from the etch stop to the diffusion regions. At least a portion of the trench is directly over the openings and extends along the axis of the line. An electrically conductive material is formed within the openings and within the trench.

Abstract: Embodiments of the invention relate to a fabrication method of an electronic device, more particularly to a fabrication method of a power device in which an oxide layer at the bottom of the trench is provided to reduce Miller capacitance and further reduce RC delay. In one embodiment, a method for forming an oxide layer at the bottom of a trench comprises providing a first substrate with at least one trench therein; forming a first oxide layer on the bottom and sidewalls of the trench; removing the first oxide layer at the bottom of the trench; and forming a second oxide layer at the bottom of the trench.

Abstract: A field effect transistor having a high field effect mobility is provided which can be obtained by a simple method. The field effect transistor includes an organic semiconductor layer composed of a crystallized film of a naphthoporphyrin compound represented by formula (2), which is obtained by the conversion by heating of the coating film of a porphyrin compound represented by formula (1), the organic semiconductor layer having crystal grains with a maximum diameter of 1 ?m or more, wherein R1 and R2 each independently denote at least one selected from the group consisting of hydrogen, halogen, hydroxyl, and alkyl having 1 to 12 carbon atoms; R3 denotes at least one selected from the group consisting of a hydrogen atom and an aryl group; and M denotes two hydrogen atoms, a metal atom or a metal oxide.