Abstract: Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in the integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching.

Abstract: Disclosed are a field effect transistor structure and a method of forming the structure. A gate stack is formed on the wafer above a designated channel region. Spacer material is deposited and anisotropically etched until just prior to exposing any horizontal surfaces of the wafer or gate stack, thereby leaving relatively thin horizontal portions of spacer material on the wafer surface and relatively thick vertical portions of spacer material on the gate sidewalls. The remaining spacer material is selectively and isotropically etched just until the horizontal portions of spacer material are completely removed, thereby leaving only the vertical portions of the spacer material on the gate sidewalls. This selective isotropic etch removes the horizontal portions of spacer material without damaging the wafer surface. Raised epitaxial source/drain regions can be formed on the undamaged wafer surface adjacent to the gate sidewall spacers in order to tailor source/drain resistance values.

Abstract: A first transistor includes a first gate insulating film, a first gate electrode, and a first sidewall. A second transistor includes a second gate insulating film, a second gate electrode, and a second sidewall. A capacitive element is connected to one side of source and drain regions of the second transistor. The first gate insulating film has the same thickness as that of the second gate insulating film, and the first gate electrode has the same thickness of that of the second gate electrode. The width of the second sidewall is larger than the width of the first sidewall.

Abstract: An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.

Abstract: A semiconductor device includes a substrate having shallow trench isolation and source/drain regions located therein, a gate stack located on the substrate between the source/drain regions, a first gate spacer on the sidewall of the gate stack, and a second gate spacer on the sidewall of the first gate spacer.

Abstract: A semiconductor device capable of improving the driving power and a manufacturing method therefor are provided. In a semiconductor device, a gate structure formed by successively stacking a gate oxide film and a silicon layer is arranged over a semiconductor substrate. An oxide film is arranged long the lateral side of the gate structure and another oxide film is arranged along the lateral side of the oxide film and the upper surface of the substrate. In the side wall oxide film comprising these oxide films, the minimum value of the thickness of the first layer along the lateral side of the gate structure is less than the thickness of the second layer along the upper surface of the substrate.

Abstract: A semiconductor device and associated methods, the semiconductor device including a semiconductor substrate with a first well region, a first gate electrode disposed on the first well region, and a first N-type capping pattern, a first P-type capping pattern, and a first gate dielectric pattern disposed between the first well region and the first gate electrode.

Abstract: The invention provides a method for forming a contact plug, comprising: forming a gate, a sidewall spacer, a sacrificial sidewall spacer, a source region and a drain region on a substrate, wherein the sidewall spacer is formed around the gate, the sacrificial sidewall spacer is formed over the sidewall spacer, and the source region and the drain region are formed within the substrate and on respective sides of the gate; forming an interlayer dielectric layer, with the gate, the sidewall spacer and the sacrificial sidewall spacer being exposed; removing the sacrificial sidewall spacer to form a contact space, the sacrificial sidewall spacer material being different from that of the gate, the sidewall spacer and the interlayer dielectric layer; forming a conducting layer to fill the contact space; and cutting off the conducting layer, to form at least two conductors connected to the source region and the drain region respectively.

Abstract: An exemplary structure for a gate structure of a field effect transistor comprises a gate electrode; a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of upper portion of the sealing layer on sidewalls of the gate electrode, whereby the field effect transistor made has almost no recess in the substrate surface.

Abstract: Provided is a method for manufacturing a MOS transistor.

Abstract: A method of forming an integrated circuit includes providing a semiconductor substrate and forming a gate over the semiconductor substrate. A gate sidewall spacer is formed around the gate and a resist is deposited on the gate sidewall spacer with the gate sidewall spacer and the gate exposed. A portion of the gate within the gate sidewall spacer is removed and a gate silicide is formed within the curved gate sidewall spacer. A dielectric layer is formed over the gate silicide and a contact is formed to the gate silicide.

Abstract: A semiconductor device includes: a gate pattern over a substrate; recess patterns provided in the substrate at both sides of the gate pattern, each having a side surface extending below the gate pattern; and a source and a drain filling the recess patterns, and forming a strained channel under the gate pattern.

Abstract: A semiconductor device includes a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; an offset spacer formed on a side surface of the gate electrode; an inner sidewall formed on the side surface of the gate electrode with the offset spacer interposed therebetween, and having an L-shaped cross section; and an insulating film formed to cover the gate electrode, the offset spacer, the inner sidewall, and a part of the semiconductor region located laterally outward from the inner sidewall. The offset spacer includes an inner offset spacer formed on the side surface of the gate electrode and an outer offset spacer formed to cover the side surface of the gate electrode and the inner offset spacer. The outer offset spacer is in contact with a top end and outer side surface of the inner offset spacer.

Abstract: An extended drain transistor (100) comprising a substrate (101), a gate (103) formed on the substrate (100), the gate (103) having a first side wall (104) and a second side wall (105) opposing the first side wall (104), an extended drain (106) implanted in a surface portion of the substrate (101) adjacent the second side wall (105) of the gate (103), a spacer (107) on the second side wall (105) of the gate (103), a source (108) implanted in a surface portion of the substrate (101) adjacent the first side wall (104) of the gate (103), and a drain (109) implanted in a surface portion of the substrate (101) adjacent the spacer (107) in such a manner that the extended drain (106) is arranged between the gate (103) and the drain (109).

Abstract: A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.

Abstract: A method of manufacturing a transistor (300), the method comprising forming a gate (101) on a substrate (102), forming a spacer (201) on lateral side walls of the gate (101) and on an adjacent portion (202) of the substrate (102), modifying material of the spacer (201) so that the modified spacer (301) covers only a lower portion (303) of the lateral side walls of the gate (101), and providing source/drain regions (301) in the modified spacer (301).

Abstract: A CMOS structure is disclosed in which a first type FET has an extremely thin oxide liner. This thin liner is capable of preventing oxygen from reaching the high-k dielectric gate insulator of the first type FET. A second type FET device of the CMOS structure has a thicker oxide liner. As a result, an oxygen exposure is capable to shift the threshold voltage of the second type of FET, without affecting the threshold value of the first type FET. The disclosure also teaches methods for producing the CMOS structure in which differing type of FET devices have differing thickness liners, and the threshold values of the differing type of FET devices is set independently from one another.

Abstract: Structures and methods of forming self aligned silicided contacts are disclosed. The structure includes a gate electrode disposed over an active area, a liner disposed over the gate electrode and at least a portion of the active area, an insulating layer disposed over the liner. A first contact plug is disposed in the insulating layer and the liner, the first contact plug disposed above and in contact with a portion of the active area, the first contact plug including a first conductive material. A second contact plug is disposed in the insulating layer and the liner, the second contact plug disposed above and in contact with a portion of the gate electrode, the second contact plug includes the first conductive material. A contact material layer is disposed in the active region, the contact material layer disposed under the first contact plug and includes the first conductive material.

Abstract: Improved semiconductor topographies and methods are provided herein for reducing the gate induced drain leakage (GIDL) associated with MOS transistors. In particular, a disposable spacer layer is used as an additional mask during implantation of one or more source/drain regions. The physical spacing between the gate and the source/drain regions of a MOS transistor (i.e., the gate/drain overlap) can be varied by varying the thickness of the disposable spacer layer. For example, a larger spacer layer thickness may be used to decrease the gate/drain overlap and reduce the GIDL associated with the MOS transistor. The disposable spacer layer is completely removed after implantation to enable electrical contact between the source/drain regions and subsequently formed source/drain contacts. A method is also provided herein for independently customizing the amount of current leakage associated with two or more MOS transistors.

Abstract: A method of fabricating a memory is provided. A substrate including a memory region and a periphery region is provided. A plurality of gates each having spacers is formed on the substrate. A plurality of openings is formed between the gates in the memory region. A first material layer is formed in the memory region to cover the gates and fill the openings. A barrier layer is formed on the substrate to cover the gates in the periphery region and the first material layer in the memory region. A second material layer is formed on the substrate in the periphery region to cover the barrier layer in the periphery region. The barrier layer covering the first material layer is removed. The first material layer is partially removed to form a plurality of second openings. Each second opening is disposed on a top of the gate in the memory region.

Abstract: Aimed at providing a highly reliable semiconductor device appropriately increased in stress at the channel region so as to improve carrier injection rate, thereby dramatically improved in transistor characteristics, and made adaptable also to recent narrower channel width, and a method of manufacturing the same, and a method of manufacturing the same, a first sidewall composed of a stress film having expandability is formed on the side faces of a gate electrode, a second sidewall composed of a film having smaller stress is formed on the first sidewall, and a semiconductor, which is a SiC layer for example, is formed as being positioned apart from the first sidewall while placing the second sidewall in between.

Abstract: Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics.

Abstract: A semiconductor device including a bilayer charge storing layer and methods of forming the same are provided. Generally, the method includes: (i) forming a first layer of the bilayer charge storing layer; and (ii) forming a second layer formed on a surface of the first layer, the second layer including an oxynitride charge trapping layer. Preferably, the first layer includes a substantially trap free oxynitride layer. More preferably, the oxynitride charge trapping layer includes a significantly higher stoichiometric composition of silicon than that of the first layer. In certain embodiments, the oxynitride charge trapping layer has a concentration of carbon selected to increase the number of traps therein. Other embodiments are also disclosed.

Abstract: In sophisticated semiconductor devices, stress memorization techniques may be applied on the basis of a silicon nitride material, which may be subsequently modified into a low-k dielectric material in order to obtain low-k spacer elements, thereby enhancing performance of sophisticated semiconductor devices. The modification of the initial silicon nitride-based spacer material may be accomplished on the basis of an oxygen implantation process.

Abstract: A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer.

Abstract: Crisscrossing spacers formed by pitch multiplication are used as a mask to form isolated features, such as contacts vias. A first plurality of mandrels are formed on a first level and a first plurality of spacers are formed around each of the mandrels. A second plurality of mandrels is formed on a second level above the first level. The second plurality of mandrels is formed so that they cross, e.g., are orthogonal to, the first plurality of mandrels, when viewed in a top down view. A second plurality of spacers is formed around each of the second plurality of mandrels. The first and the second mandrels are selectively removed to leave a pattern of voids defined by the crisscrossing first and second pluralities of spacers. These spacers can be used as a mask to transfer the pattern of voids to a substrate. The voids can be filled with material, e.g., conductive material, to form conductive contacts.

Abstract: A method is provided for fabricating a semiconductor device. The method includes providing a substrate including a dummy gate structure formed thereon, removing the dummy gate structure to form a trench, forming a first metal layer over the substrate to fill a portion of the trench, forming a protection layer in a remaining portion of the trench, removing a unprotected portion of the first metal layer, removing the protection layer from the trench, and forming a second metal layer over the substrate to fill the trench.

Abstract: A method of manufacturing the semiconductor device is provided, which provides a prevention for a “dug” of a silicon substrate caused by the etching in regions except a region for forming a film during a removal of the film with a chemical solution. A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a first silicon oxide film on a surface of a silicon substrate or on a surface of a gate electrode when a silicon nitride film for a dummy side wall is etched off, to provide a protection for such surfaces, and then etching a portion of the silicon nitride film with a chemical solution, and then a second oxide film for supplementing a simultaneously-etched portion of the first silicon oxide film is formed, and eventually performing an etching for completely removing the silicon nitride film for the dummy side wall.

Abstract: According to an illustrative example, a method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first feature and a second feature. A material layer is formed over the first feature and the second feature. A mask is formed over the first feature. At least one etch process adapted to form a sidewall spacer structure adjacent the second feature from a portion of the material layer is performed. The mask protects a portion of the material layer over the first feature from being affected by the at least one etch process. An ion implantation process is performed. The mask remains over the first feature during the ion implantation process.

Abstract: By selectively modifying the spacer width, for instance, by reducing the spacer width on the basis of implantation masks, an individual adaptation of dopant profiles may be achieved without unduly contributing to the overall process complexity. For example, in sophisticated integrated circuits, the performance of transistors of the same or different conductivity type may be individually adjusted by providing different sidewall spacer widths on the basis of an appropriate masking regime.

Abstract: A semiconductor device includes a plurality of first MIS transistors and a plurality of second MIS transistors formed on a semiconductor substrate and a liner insulating film applying stress along the gate length direction. Each of the first MIS transistors includes first L-shaped sidewalls each having an L-shaped cross-sectional shape, and each of the second MIS transistors includes second L-shaped sidewalls each having an L-shaped cross-sectional shape and outer sidewalls. The minimum thickness of a part of the liner insulating film located on each of second source/drain regions of the second MIS transistor is larger than the minimum thickness of a part thereof located on each of first source/drain regions of the first MIS transistor.

Abstract: A semiconductor process and apparatus provide a FinFET device by forming a second single crystal semiconductor layer (19) that is isolated from an underlying first single crystal semiconductor layer (17) by a buried insulator layer (18); patterning and etching the second single crystal semiconductor layer (19) to form a single crystal mandrel (42) having vertical sidewalls; thermally oxidizing the vertical sidewalls of the single crystal mandrel to grow oxide spacers (52) having a substantially uniform thickness; selectively removing any remaining portion of the single crystal mandrel (42) while substantially retaining the oxide spacers (52); and selectively etching the first single crystal semiconductor layer (17) using the oxide spacers (52) to form one or more FinFET channel regions (92).

Abstract: A manufacturing method of a semiconductor device includes a first electrode formation step of forming a control gate electrode above a surface of a semiconductor substrate with a control gate insulating film interposed between the control gate electrode and the semiconductor substrate, a step of forming a storage node insulating film on the surface of the semiconductor substrate, and a second electrode formation step of forming a memory gate electrode on a surface of the storage node insulating film. The second electrode formation step includes a step of forming a memory gate electrode layer on the surface of the storage node insulating film, a step of forming an auxiliary film, having an etching rate slower than that of the memory gate electrode layer, on a surface of the memory gate electrode layer, and a step of performing anisotropic etching on the memory gate electrode layer and the auxiliary film.

Abstract: A semiconductor device according to an embodiment includes: a fin type MOSFET having a first gate electrode, and a first gate insulating film for generating Fermi level pinning in the first gate electrode; and a planar type MOSFET having a second gate electrode, and a second gate insulating film for generating no Fermi level pinning in the second gate electrode, or generating Fermi level pinning weaker than that generated in the first gate electrode in the second gate electrode.

Abstract: A forms spacers in a electronic device integrated on a semiconductor substrate that includes: first and second transistors each comprising a gate electrode projecting from the substrate and respective source/drain regions. The process comprises: forming in cascade a first protective layer and a first conformal insulating layer of a first thickness on the whole electronic device; forming a first mask to cover the first transistor; removing the first conformal insulating layer not covered by the first mask; removing the first mask; forming a second conformal insulating layer of a second thickness on the whole device; and removing the insulating layers until the protective layer is exposed to form first spacers of a first width on the side walls of the gate electrodes of the first transistor and second spacers of a second width on the side walls of the gate electrodes of the second transistor.

Abstract: Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, sacrificial nitride spacers on opposing sidewalls of the gate electrode and source/drain regions, which are self-aligned to the sacrificial nitride spacers, on a semiconductor substrate. The sacrificial nitride spacers are selectively removed using a diluted hydrofluoric acid solution having a nitride-to-oxide etching selectivity in excess of one. In order to increase charge carrier mobility within a channel of the field effect transistor, a stress-inducing electrically insulating layer is formed on opposing sidewalls of the gate electrode. This insulating layer is configured to induce a net tensile stress (NMOS) or compressive stress (PMOS) in the channel.

Abstract: A method for making a semiconductor device is disclosed. In accordance with the method, a semiconductor structure is provided which includes (a) a substrate (203), (b) first and second gate electrodes (219) disposed over the substrate, each of the first and second gate electrodes having first and second sidewalls, and (c) first (223) and second (225) sets of spacer structures disposed adjacent to the first and second gate electrodes, respectively. A first layer of photoresist (231) is then disposed over the structure such that the first set of spacer structures is exposed and the second set of spacer structures is covered, after which the first set of spacer structures is partially etched.

Abstract: A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.

Abstract: Encapsulation of a gate stack comprising a high-k dielectric material may be accomplished on the basis of a silicon nitride material that is deposited in a sequence of two deposition processes, in which the first process may be performed on the basis of a moderately low process temperature, thereby passivating sensitive surfaces without unduly contaminating the same, while, in a second deposition process, a moderately high process temperature may be used to provide enhanced material characteristics and a reduced overall cycle time compared to conventional ALD or multi-layer deposition techniques.

Abstract: A method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a gate stack overlying the semiconductor substrate; forming spacers each having a first inner spacer and a second outer spacer on sidewalls of the gate stack; forming a protective layer on sidewalls of the spacers, covering a part of the semiconductor substrate, wherein an etching selectivity of the protective layer is higher than that of the first inner spacer.

Abstract: Disclosed are a non-volatile semiconductor memory device capable of simplifying the complicated structure of a transistor, and a fabrication method for the same.

Abstract: An improved source/drain junction configuration in a metal-oxide semiconductor transistor is provided, as well as a novel method for fabricating this junction. This configuration employs gate double sidewall spacers in the peripheral region and gate single sidewall spacers in the cell array region. The double sidewall spacers are advantageously formed to suppress the short channel effect, to prevent current leakage, and to reduce sheet resistance. The insulating layer used to form the second spacers in the peripheral region remains in the cell array region and serves as an etching stopper during the etching step of interlayer insulating layer for contact opening formation and also serves as a barrier layer during the step of silicidation formation. As a result the fabrication process of the resulting device is simplified.

Abstract: Embodiments relate to a flash memory device and a method for manufacturing a flash memory device. According to embodiments, a method may include forming a gate on and/or over a semiconductor substrate on and/or over which a device isolation film may be formed, forming a first spacer including a first oxide pattern and a first nitride pattern on and/or over side walls of the gate, forming a source and drain area on and/or over the semiconductor substrate using the gate and spacer as masks, removing the first nitride pattern of the first spacer, and forming a second spacer including a second oxide film pattern and a second nitride film pattern on and/or over the side walls of the gate by performing an annealing process on and/or over the semiconductor substrate on and/or over which the first oxide film pattern is formed.

Abstract: A gate electrode structure is provided, which includes, from bottom to top, an optional, yet preferred metallic layer, a Ge rich-containing layer and a Si rich-containing layer. The sidewalls of the Ge rich-containing layer include a surface passivation layer. The inventive gate electrode structure serves as a low-temperature electrically activated gate electrode of a MOSFET in which the materials thereof as well as the method of fabricating the same are compatible with existing MOSFET fabrication techniques. The inventive gate electrode structure is electrically activated at low processing temperatures (on the order of less than 750° C.). Additionally, the inventive gate electrode structure also minimizes gate-depletion effects, does not contaminate a standard MOS fabrication facility and has sufficiently low reactivity of the exposed surfaces that renders such a gate electrode structure compatible with conventional MOSFET processing steps.

Abstract: Fabricating a semiconductor device includes forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate having a gate top surface that extends substantially above the top substrate surface at least in center region of the trench opening, the gate having a vertical edge that includes an extended portion, the extended portion extending above the trench opening and being substantially aligned with the trench wall.

Abstract: An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.

Abstract: Embodiments of the present invention provide a method of forming a conductive stud contacting a semiconductor device. The method includes forming a protective layer covering the semiconductor device; selectively etching an opening down through the protective layer reaching a contact area of the semiconductor device, the opening being away from a protected area of the semiconductor device; and filling the opening with a conductive material to form the conductive stud. One embodiment may further include forming a dielectric liner directly on top of the semiconductor device, and forming the protective layer on top of the dielectric liner. Embodiments of the present invention also provide a semiconductor device made thereof.

Abstract: A semiconductor device has a structure of contacts whose size and pitch are finer that those that can be produced under the resolution provided by conventional photolithography. The contact structure includes a semiconductor substrate, an interlayer insulating layer disposed on the substrate, annular spacers situated in the interlayer insulating layer, first contacts surrounded by the spacers, and a second contact buried in the interlayer insulating layer between each adjacent pair of the first spacers. The contact structure is formed by forming first contact holes in the interlayer insulating layer, forming the spacers over the sides of the first contact holes to leave second contact holes within the first contact holes, etching the interlayer insulating layer from between the spacers using the first spacers as an etch mask to form third contact holes, and filling the first and second contact holes with conductive material. In this way, the pitch of the contacts can be half that of the first contact holes.

Abstract: A non-volatile semiconductor memory device includes a gate stack formed on a substrate, semiconductor spacers, an oxide-nitride-oxide stack, and a contact pad. The semiconductor spacers are adjacent to sides of the gate stack and over the substrate. The oxide-nitride-oxide stack is located between the spacers and the gate stack, and located between the spacers and the substrate, such that the oxide-nitride-oxide stack has a generally L-shaped cross-section on at least one side of the gate stack. The contact pad is over and in electrical contact with the gate electrode and the semiconductor spacers. The contact pad may be further formed into recessed portions of the oxide-nitride-oxide stack between the gate electrode and the semiconductor spacers. The contact pad may include an epitaxial silicon having a metal silicide formed thereon.

Abstract: A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer.