Abstract: A process includes planarizing a microelectronic device that includes a gate stack and adjacent trench contacts. The process also includes removing a gate spacer at the gate stack and replacing the gate spacer with a dielectric that results in a lowered overlap capacitance between the gate stack and an adjacent embedded trench contact.

Abstract: A semiconductor device and method. One embodiments provides a semiconductor substrate having a trench with a sidewall isolation comprising a first isolating material, a field electrode formed in lower portion of the trench, a cover comprising a second material above the field electrode, the second material being selectively etchable to the first isolating material, a gate dielectric on the sidewall in an upper portion of the trench and a gate electrode in the upper portion of the trench.

Abstract: A method for making a semiconductor device is provided. In accordance with the method, a semiconductor structure is provided which comprises (a) a substrate (203), (b) first (219) and second (220) gate electrodes disposed over the substrate, and (c) first (223) and second (225) sets of spacer structures disposed adjacent to said first and second gate electrodes, respectively. A first layer of photoresist (231) is disposed over the structure such that the first set of spacer structures is exposed and the second set of spacer structures is covered. The structure is then subjected to an etch which etches the first layer of photoresist and a portion of the first and second sets of spacer structures.

Abstract: A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, selectively removing the spaced apart features, filling a space between a first sidewall spacer and a second sidewall spacer with a filler feature, selectively removing the sidewall spacers to leave a plurality of the filler features spaced apart from each other, and etching the at least one device layer using the filler feature as a mask.

Abstract: A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, silicides on the first gate, the second gate and respective source and drain regions; forming additional spacers on the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.

Abstract: A semiconductor device including a gate stack located over a substrate and a spacer located over the substrate and adjacent the gate stack. The spacer includes a plurality of layers, wherein at least one of the plurality of layers is a batch layer and at least one of the plurality of layers is a non-batch layer.

Abstract: Methods are provided for the fabrication of abrupt and tunable offset spacers for improved transistor short channel control. The methods include the formation of a gate electrode within a dielectric layer, with only a top portion of the gate electrode exposed. Silicon is added on the top portion of the gate electrode, by selective epitaxial growth, for example. Etching of the dielectric layer is performed with added silicon at the top portion of the gate electrode serving as a silicon mask to prevent etching of the dielectric layer directly underneath the silicon mask, which includes overhangs over the gate electrode sidewalls. The etching creates offset spacers in a production-worthy manner, and can be used to form offset spacers that are asymmetrical in width. By running the methodology in a microloading regime, wider offset spacers may be created on narrower polysilicon gate features, thereby improving Vt roll-off.

Abstract: A semiconductor process and apparatus includes forming PMOS transistors (90) with enhanced hole mobility in the channel region by forming a hydrogen-rich silicon nitride layer (91, 136) on or adjacent to sidewalls of the PMOS gate structure as either a hydrogen-rich implant sidewall spacer (91) or as a post-silicide hydrogen-rich implant sidewall spacer (136), where the hydrogen-rich dielectric layer acts as a hydrogen source for passivating channel surface defectivity under the PMOS gate structure.

Abstract: Crisscrossing spacers formed by pitch multiplication are used as a mask to form isolated features, such as contacts vias. A first plurality of mandrels are formed on a first level and a first plurality of spacers are formed around each of the mandrels. A second plurality of mandrels is formed on a second level above the first level. The second plurality of mandrels is formed so that they cross, e.g., are orthogonal to, the first plurality of mandrels, when viewed in a top down view. A second plurality of spacers is formed around each of the second plurality of mandrels. The first and the second mandrels are selectively removed to leave a pattern of voids defined by the crisscrossing first and second pluralities of spacers. These spacers can be used as a mask to transfer the pattern of voids to a substrate. The voids can be filled with material, e.g., conductive material, to form conductive contacts.

Abstract: A method of forming a semiconductor device that embeds an L-shaped spacer is provided. The method includes defining an L-shaped spacer on each side of a gate region of a substrate and embedding the L-shaped spacers in an oxide layer so that the oxide layer extends over a portion of the substrate a predetermined distance from a lateral edge of the L-shaped spacer. And removing oxide layers to expose the L-shape spacers.

Abstract: A method for manufacturing a semiconductor device. In one example embodiment of the present invention, a method for manufacturing a semiconductor device includes various steps. First, a gate pattern is formed on a substrate. Next, a first oxide layer is formed on the gate pattern. Then, a second oxide layer, a first silicon nitride layer, and a second silicon nitride layer are sequentially formed over the substrate and the first oxide layer. Next, a first etching process is performed to remove horizontal portions of the first and second silicon nitride layers. Then, source/drain regions are formed in the substrate. Next, the vertical portions first and second silicon nitride layers are removed. Then, a third silicon nitride layer is formed over the second oxide layer. Finally, a second etching process is performed to remove horizontal portions of the third silicon nitride layer and the second oxide layer.

Abstract: A semiconductor memory device comprises a memory cell unit including at least one memory cell having a structure with a floating gate and a control gate stacked via an insulator on a semiconductor substrate. A common source line is connected to one end of the memory cell unit. A bit line is connected to the other end of the memory cell unit. The control gate has at least an upper portion with a width along the gate length formed wider than the width of the floating gate.

Abstract: A semiconductor device according to an embodiment of the present invention includes: a semiconductor substrate; an isolation structure formed in a trench, formed in the semiconductor substrate, through a semiconductor oxide film; a floating gate formed on the semiconductor substrate between the isolation structures through an insulating film; a gate oxidation protection film formed on a side surface, on the isolation structure side, of the floating gate so that each of a part of a side surface and a bottom surface of the gate oxidation protection film contacts the insulating film; and a control gate formed on the floating gate through an inter-gate insulating film.

Abstract: The invention relates to a method for the production of both MOS transistors with extremely low leakage currents at the pn junctions and logic/switching transistors, whose gates are laterally defined by spacers in a p-substrate or a p-well in an n-substrate. The aim of the invention is to provide a method for the production of MOS transistors with extremely low leakage currents that allows for parallel logic/switching transistors.

Abstract: In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement.

Abstract: Embodiments of the invention provide a method of forming embedded silicon germanium (eSiGe) in source and drain regions of a p-type field-effect-transistor (pFET) through a disposable spacer process; depositing a gap-filling layer directly on the eSiGe in the source and drain regions in a first process; depositing a layer of offset spacer material on top of the gap-filling layer in a second process different from the first process; etching the offset spacer material and the gap-filling layer, thus forming a set of offset spacers and exposing the eSiGe in the source and drain regions of the pFET; and finishing formation of the pFET.

Abstract: A liquid crystal display device includes first and second substrates bonded to each other, first column spacers on the first substrate, protrusions on the second substrate that contact a center portion of an upper surface of the spacers, respectively, recesses formed in the second substrate surrounding the protrusions, respectively, and a liquid crystal layer between the first and second substrates.

Abstract: A semiconductor structure having a plurality of gate stacks on a semiconductor substrate provided with a gate dielectric. The gate stacks have a lower first layer made of polysilicon, an overlying second layer made of a metal silicide, and an upper third layer made of an insulating material, and a sidewall oxide on the sidewalls of the first and second layers. The sidewall oxide is thinned or removed on one of the sidewalls, and the gate stacks have sidewall spacers made of the insulating material.

Abstract: A growth material that grows selectively on the vertical sidewalls of a vertical device forms sidewall spacers on substantially vertical sidewalls of the vertical device that is disposed on a horizontal substrate surface of a semiconductor substrate. A spacer-like seed liner may be provided on the vertical sidewalls of the vertical device to control selective growth. The vertical device may be a gate electrode of a field effect transistor (FET). With selectively grown sidewall spacers, heavily doped contact regions of the FET may be precisely spaced apart from the gate electrode. The distance of the heavily doped contact regions to the gate electrode does not depend from the height of the gate electrode. Distances of more than 150 nm between the heavily doped contact region and the gate electrode may be achieved so as to facilitate the formation of, for example, DMOS devices.

Abstract: A complementary metal oxide semiconductor (CMOS) device has a substrate 100, a gate structure 108 disposed atop the substrate, and spacers 250, deposited on opposite sides of the gate structure 108 to govern formation of deep source drain regions S, D in the substrate. Spacers 250 are formed of an oxynitride (SiOxNyCz) wherein x and y are non-zero but z may be zero or greater; such oxynitride spacers reduce parasitic capacitance, thus improving device performance.

Abstract: Methods of forming spacers on sidewalls of features of semiconductor devices and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece and at least one feature disposed over the workpiece. A first spacer is disposed on the sidewalls of the at least one feature, the first spacer comprising a first material. A first liner is disposed over the first spacer and over a portion of the workpiece proximate the first spacer, the first liner comprising the first material. A second spacer is disposed over the first liner, the second spacer comprising a second material. A second liner is disposed over the second spacer, the second liner comprising the first material.

Abstract: Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in the integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching.

Abstract: A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer.

Abstract: A method of manufacturing an L-shaped spacer is described. First, a substrate is provided and a protruding structure is formed thereon. Next, a dielectric material is formed on the substrate and covers the stacked structure. Then, the dielectric material on the top of the protruding structure and on portions of the substrate is removed to form an L-shaped spacer.

Abstract: A MOS transistor having a highly stressed channel region and a method for forming the same are provided. The method includes forming a first semiconductor plate over a semiconductor substrate, forming a second semiconductor plate on the first semiconductor plate wherein the first semiconductor plate has a substantially greater lattice constant than the second semiconductor plate, and forming a gate stack over the first and the second semiconductor plates. The first and the second semiconductor plates include extensions extending substantially beyond side edges of the gate stack. The method further includes forming a silicon-containing layer on the semiconductor substrate, preferably spaced apart from the first and the second semiconductor plates, forming a spacer, a LDD region and a source/drain region, and forming a silicide region and a contact etch stop layer. A high stress is developed in the channel region. Current crowding effects are reduced due to the raised silicide region.

Abstract: A sidewall spacer pullback scheme is implemented in forming a transistor. The scheme, among other things, allows silicide regions of the transistor to be made larger, or rather have a larger surface area. The larger surface area has a lower resistance and thus allows voltages to be applied to the transistor more accurately. The scheme also allows transistors to be made slightly thinner so that the formation of voids in a layer of dielectric material formed over the transistors is mitigated. This mitigates yield loss by facilitating more predictable or otherwise desirable transistor behavior.

Abstract: An apparatus includes a first substrate having a set of semiconductor devices formed within it. The apparatus also includes a second substrate. A third substrate has a data conductor coupled between first and second connections to the second substrate. The data conductor is coupled to the set of semiconductor devices at respective connection points.

Abstract: Gate insulating films 12A and 12B of different thickness are formed in element openings 16a and 16b in the isolation film 16 of a wafer 10. The gate insulating film 12B is the thinnest gate insulating film. A dummy insulating film having the same thickness as the thinnest gate insulating film 12B is formed in wafer periphery area WP. Gate electrodes 20A and 20B are formed on the gate insulating films 12A and 12B, and thereafter an insulating film is deposited on the wafer surface. The deposited insulating film is dry-etched to form side wall spacers 22a to 22d on side walls of the gate electrodes 20A and 20B. During dry etching, the time when the semiconductor surfaces are exposed in the element opening 16b and area WP is detected as an etching end point by a change in the emission spectrum intensity of etching byproducts.

Abstract: A method of manufacturing a semiconductor device including at least one step of: forming a transistor on and/or over a semiconductor substrate; forming silicide on and/or overa gate electrode and a source/drain region of the transistor; removing an uppermost oxide film from a spacer of the transistor; and forming a contact stop layer on and/or over the entire surface of the substrate including the gate electrode.

Abstract: A CMOS device having dual-epi channels comprises a first epitaxial region formed on a substrate, a PMOS device formed on the first epitaxial region, a second epitaxial region formed on the substrate, wherein the second epitaxial region is formed from a different material than the first epitaxial region, an NMOS device formed on the second epitaxial region, and electrical contacts coupled to the PMOS and NMOS devices, wherein the electrical contacts are self-aligned.

Abstract: The electrical performance enhancing effects of inducing strain in semiconductor devices is made substantially uniform across a substrate having a varying population density of device components by selectively spacing apart the strain-inducing structures from the effected regions of the semiconductor devices depending upon the population density of device components. Differing separation distances are obtained by selectively forming sidewall spacers on device components, such as MOS transistor gate electrodes, in which the sidewall spacers have a relatively small width in regions having a relatively high density of device components, and a relatively larger width in regions having a relatively low density of device components. By varying the separation distance of strain-inducing structures from the effected components, uniform electrical performance is obtained in the various components of the devices in an integrated circuit regardless of the component population density.

Abstract: Provided are a method of fabricating an improved multi-gate transistor and a multi-gate transistor fabricated using the method, in which an active pattern is formed on a substrate, the active pattern having two or more surfaces on which channel regions are to be formed, a gate insulating layer is formed on the channel regions, and a patterned gate electrode is formed on the gate insulating layer while maintaining a shape conformal to the active pattern.

Abstract: An active region and an opposite conductivity active region are formed in a semiconductor substrate. The opposite conductivity active region is covered with a resist pattern. Impurities are implanted into a surface layer of the active region. An angle ?0 is defined as a tilt angle obtained by tilting a virtual plane perpendicular to the substrate and including an edge of the active region, toward the resist pattern by using as a fulcrum a point on the substrate nearest to the resist pattern, until the virtual plane contacts the resist pattern. The ion implantation is performed in a direction having a tilt angle larger than ?0 and allowing ions passed through the uppermost edge of the resist pattern to be incident upon an area between the resist pattern and the active region, and is not performed along a direction allowing the ions to be incident upon the active region.

Abstract: A metal layer etch process deposits, patterns and anisotropically etches a polysilicon layer (24) down to an underlying metal layer (22) to form an etched polysilicon structure (54) with polymer layers (50, 52) formed on its sidewall surfaces. The polymer layer (50, 52) are removed to expose an additional surface area (60, 62) of the metal layer (22), and dielectric layers (80, 82) are formed on the sidewall surfaces of the etched polysilicon structure (54). Next, the metal layer (22) is plasma etched to form an etched metal layer (95) with substantially vertical sidewall surfaces (97, 99) by simultaneously charging the dielectric layers (80, 82) to change plasma ion trajectories near the dielectric layers (80, 82) so that plasma ions (92, 94) impact the sidewall surfaces (97, 99) in a more perpendicular angle to enhance etching of the sidewall surfaces (97, 99) of the etched metal layer (95).

Abstract: A method of manufacturing a semiconductor device is provided. The method includes: sequentially forming an oxide layer and a nitride layer on a substrate having a gate insulating layer and a gate formed in the order named thereon; forming a spacer at both sidewalls of the gate by etching the nitride layer; forming a source region and a drain region at both sides of the spacer in the substrate; removing the oxide layer formed on the gate and the substrate; partially removing surfaces of the gate, the source region and the drain region from which the oxide layer is removed; and depositing and thermally annealing a metal layer on the surfaces of the gate, source and drain whose surfaces are partially removed, to form a salicide layer.

Abstract: Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted in to the exposed gate structure.

Abstract: Embodiments of the invention provide a semiconductor device and a fabrication method for a semiconductor device that includes the processes of forming multiple gates on a silicon substrate, forming a gate spacer having a positive slope at the gate spacer edge, depositing a polysilicon layer on the silicon substrate between the gates, etching a portion of the polysilicon layer to form an opening exposing a portion of the silicon substrate, and forming an inter-insulation layer to the exposed portion of the silicon substrate to fill the opening. Using an annealing process applied to a layer in the gate spacer, the etch selectivity can be selectively controlled and consequently, the degree of slope at the gate spacer edge is predetermined.

Abstract: A memory device, such as a DRAM, SRAM or non-volatile memory device, includes a substrate, a gate electrode disposed on the substrate, and source and drain regions in the substrate adjacent respective first and second sidewalls of the gate electrode. First and second sidewall spacers are disposed on respective ones of the first and second sidewalls of the gate electrode. The first and second sidewall spacers have different dielectric constants. The first and second sidewall spacers may be substantially symmetrical and/or have substantially the same thickness.

Abstract: First and second impurity doped regions are formed in a semiconductor substrate. A first gate electrode is formed on the first impurity doped region with a first gate insulation film interposed therebetween. A second gate electrode is formed on the second impurity doped region with a second gate insulation film interposed therebetween. A first sidewall insulation film is formed on either side of the first gate electrode. A second sidewall insulation film has a thickness different from that of the first sidewall insulation film and are formed on either side of the second gate electrode. A third sidewall insulation film is formed on the first sidewall insulation film on the side of the first gate electrode. A fourth sidewall insulation films have a thickness different from that of the third sidewall, insulation film and are formed on the second sidewall insulation film on the side of the second gate electrode.

Abstract: A method of forming nonvolatile memory devices according to example embodiments of the present invention includes forming a device isolation layer defining active regions in a semiconductor substrate; forming a plurality of transistors on the active regions, the plurality of transistors comprising a pair of adjacent string selection transistors, a pair of adjacent ground selection transistors, and a plurality of memory cell transistors connected in series between the string selection transistors and ground selection transistors; forming a common source line using SEG between a pair of adjacent ground selection transistors so that the common source line has a top surface lower than a top surface of the pair of adjacent ground selection transistors.

Abstract: A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a plurality of gate electrodes thereon in both NMOS and PMOS regions using the surface. A multi-layer offset spacer stack including a top layer and a compositionally different bottom layer is formed and the multi-layer spacer stack is etched to form offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize a thinner offset spacer are covered with a first masking material, and transistors designed to utilize a thicker offset spacer are patterned and first implanted. At least a portion of the top layer is removed to leave the thinner offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize the thicker offset spacer are covered with a second masking material, and the transistors designed to utilize the thinner offset spacer are patterned and second implanted.

Abstract: Embodiments of the present invention provide a method of forming a conductive stud contacting a semiconductor device. The method includes forming a protective layer covering the semiconductor device; selectively etching an opening down through the protective layer reaching a contact area of the semiconductor device, the opening being away from a protected area of the semiconductor device; and filling the opening with a conductive material to form the conductive stud. One embodiment may further include forming a dielectric liner directly on top of the semiconductor device, and forming the protective layer on top of the dielectric liner. Embodiments of the present invention also provide a semiconductor device made thereof.

Abstract: A method of manufacturing a semiconductor device comprising removing a first oxide layer deposited over a semiconductor substrate, thereby exposing source and drain regions of the substrate. The first oxide layer is configured as an etch-stop for forming silicon nitride sidewall spacers of a gate structure located adjacent to the source and drain regions. The method further comprises depositing a second oxide layer selectively on the exposed source and drain regions and then removing lateral segments of the silicon nitride sidewall spacers.

Abstract: Semiconductor devices have gate structures on a semiconductor substrate with first spacers on sidewalls of the respective gate structures. First contact pads are positioned between the gate structures and have heights lower than the heights of the gate structures. Second spacers are disposed on sidewalls of the first spacers and on exposed sidewalls of the first contact pads. Second contact pads are disposed on the first contact pads.

Abstract: Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate. The wide sidewall spacers are then removed and slim sidewall spacers are formed alongside a gate stack of the transistor. The slim spacers facilitate transferring stress from an overlying pre metal dielectric (PMD) liner to a channel of the transistor, and also facilitate reducing a resistance in the transistor by allowing silicide regions to be formed closer to the channel. This mitigates yield loss by facilitating predictable or otherwise desirable behavior of the transistor.

Abstract: The method for fabricating the semiconductor device comprises: the step of forming a ferroelectric capacitor over a semiconductor substrate 10; the step of forming an insulating film 54, covering the ferroelectric capacitor; the step of processing thermal treatment to eliminate hydrogen and/or water adsorbed on a surface of the insulating film 54 or occluded in the insulating film 54; and the step of forming a capacitor protective film 56 of an aluminum oxide film over the insulating film 54. The step of processing the thermal treatment and the step of forming the capacitor protective film are performed continuously in the same system without exposing to an ambient atmosphere.

Abstract: MOSFET gate structures comprising multiple width offset spacers are provided. A first and a second gate structure are formed on a semiconductor substrate. A pair of first offset spacers are formed adjacent either side of the first gate structure. Each of the first offset spacers comprises a first silicon oxide layer with a first dielectric layer overlying. A pair of second offset spacers are formed adjacent either side of the second gate structure. Each of the second offset spacers comprises a second silicon oxide layer with a second dielectric layer overlying. Ion implanted doped regions are formed in the semiconductor substrate adjacent the first and second offset spacers respectively to form a first and second MOSFET device. A maximum width of each of the first offset spacers is different from that of the second offset spacers. The first silicon oxide layer is thinner than the second silicon oxide layer.

Abstract: A nonvolatile semiconductor memory according to an example of the present invention is provided with a memory cell having a floating gate electrode and a control gate electrode, and a select gate transistor having a select gate electrode and connected in series to the memory cell. A cell unit is comprised with the memory cell and the select gate transistor. A bird's beak of the edge at the memory cell side of the select gate electrode is larger than a bird's beak of at least one edge of the floating gate electrode.

Abstract: Method of manufacturing a semiconductor chip. An array region gate stack is formed on an array region of a substrate and a periphery region gate stack is formed on a periphery region of a substrate. A first dielectric material, a charge-storing material, and a second dielectric material are deposited over the substrate. Portions of the first dielectric material, the charge-storing material, and the second dielectric material are removed to form storage structures on the array region gate stack and on the periphery region gate stack. The storage structures have a generally L-shaped cross-section. A first source/drain region is formed in the array region well. A third dielectric material and a spacer material are deposited over the substrate. Portions of the third dielectric material and the spacer material are removed to form spacers. A second source/drain region is formed in the periphery region well.

Abstract: A gate stack is formed on a substrate. The gate stack has a sidewall. An oxide-nitride-oxide material is deposited on the gate stack. Portions of the oxide-nitride-oxide material are removed to form an oxide-nitride-oxide structure. The oxide-nitride-oxide structure has a generally L-shaped cross-section with a vertical portion along at least part of the gate stack sidewall and a horizontal portion along the substrate. A top oxide material is deposited over the substrate. A silicon nitride spacer material is deposited over the top oxide material. Portions of the top oxide material and the silicon nitride spacer material are removed to form a silicon nitride spacer separated from the oxide-nitride-oxide stack by the top oxide material. Source/drain regions are formed in the substrate.