Abstract: An aspect of the present disclosure, there is provided semiconductor memory device including a ferroelectric capacitor and a field effect transistor as a memory cell, the ferroelectric capacitor including a lower electrode connected to one of the pair of the impurity diffusion layers, a bit line formed below the lower electrode, wherein each of the memory cells shares the bit line contact with an adjacent memory cell at one side in the first direction to connect to the bit line, and three of the word lines are formed between the bit line contacts in the first direction.

Abstract: A method of manufacturing a semiconductor device has forming a ferroelectric film over a substrate, placing the substrate having the ferroelectric film in a chamber substantially held in vacuum, introducing oxygen and an inert gas into the chamber, annealing the ferroelectric film in the chamber, and containing oxygen and the inert gas while the chamber is maintained sealed.

Abstract: Provided are a ferroelectric recording medium and a method of manufacturing the same. The ferroelectric recording medium includes a substrate, a plurality of supporting layers which are formed on the substrate, each of the supporting layers having at least two lateral surfaces; and data recording layers formed on the lateral surfaces of the supporting layers. First and second data recording layers may be respectively disposed on two facing lateral surfaces of each of the supporting layers. The supporting layers may be polygonal pillars having at least three lateral surfaces. A plurality of the supporting layers can be disposed at uniform intervals in a two-dimensional array.

Abstract: A capacitor includes a pair of electrodes and a ferroelectric film sandwiched between the electrodes. The electrodes are provided perpendicular to the direction of the polarization axis of the ferroelectric film.

Abstract: A ferroelectric memory device manufacturing method includes the steps of forming an interlayer isolating film for covering a transistor formed on a semiconductor substrate; forming a conductive plug in the interlayer insulating film to contact a diffusion region of the transistor formed on the semiconductor substrate; forming a ferroelectric capacitor including a lower electrode, a ferroelectric film and an upper electrode; and forming a compound film including silicon (Si) and a CH group on a surface of the interlayer insulating film and a surface of the conductive plug by depositing a Si compound containing Si atoms and the CH groups; wherein the compound film is formed after forming the conductive plug, and the compound film is formed before forming the lower electrode; and a self-orientation film is formed on a surface of the compound film.

Abstract: A semiconductor device includes a ferroelectric capacitor formed above the lower interlevel insulating film covering a MOS transistor formed on a semiconductor substrate, including lamination of a lower electrode, an oxide ferroelectric film, a first upper electrode made of conductive oxide having a stoichiometric composition AOx1 and an actual composition AOx2, a second upper electrode made of conductive oxide having a stoichiometric composition BOy1 and an actual composition BOy2, where y2/y1>x2/x1, and a third upper electrode having a composition containing metal of the platinum group; and a multilayer wiring structure formed above the lower ferroelectric capacitor, and including interlevel insulating films and wirings. Abnormal growth and oxygen vacancies can be prevented which may occur when the upper electrode of the ferroelectric capacitor is made of a conductive oxide film having a low oxidation degree and a conductive oxide film having a high oxidation degree.

Abstract: A ferroelectric memory device includes a field effect transistor formed over a semiconductor substrate and including first and second diffusion regions, an interlayer insulation film formed over the semiconductor substrate so as to cover the field effect transistor, a conductive plug formed in the interlayer insulation film in contact with the first diffusion region, and a ferroelectric capacitor formed over the interlayer insulation in contact with the conductive plug. The ferroelectric capacitor includes a ferroelectric film and upper and lower electrodes sandwiching the ferroelectric film respectively from above and below.

Abstract: A manufacturing method for a ferroelectric memory device including: forming a lower electrode; forming an electrode oxide film composed of an oxide of a constituent material of the lower electrode; forming a first ferroelectric layer on the lower electrode by reaction between organometallic source material gas and oxygen gas; forming a second ferroelectric layer on the first ferroelectric layer by reaction between organometallic source material gas and oxygen gas; and forming an upper electrode on the second ferroelectric layer. In the method, the oxygen gas in the forming of the first ferroelectric layer is in an amount less than the amount of oxygen necessary for reaction of the organometallic source material gas. In the method, the oxygen gas in the forming of the second ferroelectric layer is in an amount greater than the amount of oxygen necessary for reaction of the organometallic source material gas.

Abstract: A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.

Abstract: The memory cell array includes a memory cell, the memory cell including a ferroelectric capacitor and a transistor. The memory cell array includes a word line selecting the memory cell, a plate line applying a drive voltage to the ferroelectric capacitor, and a bit line reading data from the ferroelectric capacitor. A selection transistor selectively connects the memory cell to the bit line. A dummy cell provides a reference potential, the reference potential being referred to for a potential read from the memory cell. A sense amplifier circuit includes a plurality of amplification circuits amplifying the potential difference between a bit-line pair. A decoupling circuit electrically cuts off the bit line between the amplification circuits.

Abstract: A semiconductor device includes a semiconductor substrate and a capacitor which is disposed on a principal surface of the semiconductor substrate. The capacitor includes a lower electrode film disposed on the principal surface of the semiconductor substrate, a dielectric film disposed on the lower electrode and an upper electrode film disposed on the dielectric film. The semiconductor device further includes an interconnection film which includes a portion disposed on the upper electrode film so as to be electrically coupled to the upper electrode film. Directions of residual stresses of the upper electrode film coincide with directions of residual stresses of the portion of the interconnection film. Each of the upper electrode film and the interconnection film may include at least one of platinum and iridium. Also, there is provided a method of manufacturing the semiconductor device.

Abstract: A ferroelectric capacitor including: a substrate; a first electrode formed above the substrate; a first ferroelectric layer formed above the first electrode and including a complex oxide shown by Pb(Zr,Ti)O3; a second ferroelectric layer formed above the first ferroelectric layer and including a complex oxide shown by Pb(Zr,Ti)1-xNbxO3; and a second electrode formed above the second ferroelectric layer.

Abstract: A nonvolatile ferroelectric memory device includes a plurality of unit cells. Each of the unit cells includes a cell capacitor and a cell transistor. The cell capacitor includes a storage node, a ferroelectric layer, and a plate line. The cell capacitors of more than one of the plurality of unit cells are provided in a trench.

Abstract: A method for manufacturing a reservoir capacitor of a semiconductor device reduces the resistance of the reservoir capacitor to secure reliability of the semiconductor device. The method comprises: forming a dummy pattern having a lattice structure over a transistor; forming a first interlayer insulating film over the resulting structure including the dummy pattern; etching the first interlayer insulating film to form a line-structured storage node contact region between the lattice structures; and filling a conductive layer in the line-structured storage node contact region to form a line-structured storage node contact.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a first ferroelectric film over a lower electrode, crystallizing the first ferroelectric film, forming a second ferroelectric film in an amorphous state over the first ferroelectric film so as to fill voids existing on a surface of the first ferroelectric film, and forming an upper electrode over the second ferroelectric film of the amorphous state, wherein the crystallizing step of the first ferroelectric film is conducted by a thermal annealing process at a temperature of 585° C. or higher.

Abstract: A semiconductor memory device, comprising: a semiconductor substrate; a memory cell section comprising a memory transistor provided on the semiconductor substrate, the memory transistor including a first gate electrode provided on the semiconductor substrate with a gate insulating film interposed therebetween, and a source and drain provided at both sides of the first gate electrode on the semiconductor substrate, and a ferroelectric capacitor provided above the memory transistor, the ferroelectric capacitor including a first electrode film connected to any one of a source and drain of the memory transistor, a second electrode film connected to the other one of the drain and source of the memory transistor, and a ferroelectric film provided between the first electrode film and the second electrode film, the memory cell section having the memory transistor and the ferroelectric capacitor connected in parallel to each other; and a select transistor section, comprising a select transistor provided at an end of t

Abstract: A ferroelectric polymer memory module includes a first set of layers including: a first ILD layer defining trenches therein; a first electrode layer disposed in the trenches of the first ILD layer; a first conductive polymer layer disposed on the first electrode layer and in the trenches of the first ILD layer; and a ferroelectric polymer layer disposed on the first conductive polymer layer and in the trenches of the first ILD layer; and a second set of layers disposed on the first set of layers to define memory cells therewith, the second set of layers including: a second ILD layer defining trenches therein; a second conductive polymer layer disposed in the trenches of the second ILD layer; and a second electrode layer disposed on the second conductive polymer layer.

Abstract: There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating film) formed over the capacitor and the first interlayer insulating film, and a metal pattern formed on the fourth interlayer insulating film over the capacitor and its periphery to have a stress in an opposite direction to the fourth interlayer insulating film. As a result, characteristics of the capacitor covered with the interlayer insulating film can be improved.

Abstract: A nonvolatile magnetic memory device including a magnetoresistance device having a recording layer formed of a ferromagnetic material for storing information by use of variation in resistance depending on the magnetization inversion state. The plan-view shape of the recording layer includes a pseudo-rhombic shape having four sides, at least two of the four sides each include a smooth curve having a central portion curved toward the center of the pseudo-rhombic shape. The easy axis of magnetization of the recording layer is substantially parallel to the longer axis of the pseudo-rhombic shape. The hard axis of magnetization of the recording layer is substantially parallel to the shorter axis of the pseudo-rhombic shape. The sides constituting the plan-view shape of the recording layer are smoothly connected to each other.

Abstract: A semiconductor device fabrication method that improves the efficiency of semiconductor device production. A plurality of wafer substrates are set and a process for fabricating semiconductor devices each having a ferroelectric capacitor is begun. After ferroelectric layers are formed over the plurality of wafer substrates, the ferroelectric layers formed are damaged. The plurality of wafer substrates are then rearranged and treatment is performed. In each step in which the ferroelectric layers formed may be damaged, the plurality of wafer substrates are rearranged and treatment is performed. As a result, retention characteristic variations among wafer substrates in the same lot are reduced and the productivity of semiconductor devices is improved.

Abstract: A lower electrode film is formed above a semiconductor substrate first, and then a ferroelectric film is formed on the lower electrode film. After that, an upper electrode film is formed on the ferroelectric film. When forming the upper electrode, an IrOx film containing crystallized small crystals when formed is formed on the ferroelectric film first, and then an IrOx film containing columnar crystals is formed.

Abstract: In a semiconductor device manufacturing method having the etching step of an electrode material film constituting a capacitor using ferroelectric substance or high- dielectric substance, etching of a conductive film that acts as an electrode of the capacitor formed over a semiconductor substrate is carried out in an atmosphere containing bromine, and a heating temperature of the semiconductor substrate is set in a range of 300° C. to 600° C., otherwise etching of at least the conductive film is carried out in an atmosphere to which only hydrogen bromide and oxygen are supplied from an outside.

Abstract: A semiconductor device includes a ferroelectric capacitor formed above the lower interlevel insulating film covering a MOS transistor formed on a semiconductor substrate, including lamination of a lower electrode, an oxide ferroelectric film, a first upper electrode made of conductive oxide having a stoichiometric composition AOx1 and an actual composition AOx2, a second upper electrode made of conductive oxide having a stoichiometric composition BOy1 and an actual composition BOy2, where y2/y1>x2/x1, and a third upper electrode having a composition containing metal of the platinum group; and a multilayer wiring structure formed above the lower ferroelectric capacitor, and including interlevel insulating films and wirings. Abnormal growth and oxygen vacancies can be prevented which may occur when the upper electrode of the ferroelectric capacitor is made of a conductive oxide film having a low oxidation degree and a conductive oxide film having a high oxidation degree.

Abstract: A memory includes a first interlayer on transistors; a first and second plugs connected to the transistor; ferroelectric capacitors; a second interlayer covering a side surface of the capacitor; a local interconnection connecting the second plug to the upper electrode, wherein two upper electrodes adjacent to each other on the second plug are connected to the second plug, the lower electrodes adjacent to each other on the first plug are connected to the first plug, cell blocks comprising the connected capacitors are arranged, cell blocks adjacent to each other are arranged to be shifted by a half pitch of the local interconnection, a first gap between two capacitors adjacent to each other on the second plug is larger than twice a thickness of the second interlayer, and a second gap between the cell blocks adjacent to each other is smaller than twice the thickness of the second interlayer.

Abstract: Conventionally, the layer of the insulator between a cathode and an anode is formed by a droplet discharge method, vapor deposition, or the like separately from an interlayer insulating film formed over a thin film transistor, which creates problems of increase in cost and the number of manufacturing steps. A memory device of the present invention includes a first conductive film; an insulating film formed over the first conductive film; and a second conductive film formed over the insulating film, and an opening and a contact hole which are formed in the insulating film. Further, the insulating film exists between the first conductive film and the second conductive film formed in the opening, and the first conductive film and the second conductive film are electrically connected in the contact hole.

Abstract: According to the present invention, contact plugs are formed by a CVD method without deteriorating the properties of the ferroelectric capacitor in a semiconductor device having a fine ferroelectric capacitor. Adhesive film is formed in a contact hole, which exposes an upper electrode of the ferroelectric capacitor after conducting heat treatment in an oxidizing atmosphere, and a W layer is deposited by the CVD method using such TiN adhesive film as a hydrogen barrier and the contact hole is filled.

Abstract: A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current density distribution around the first electrode.

Abstract: A first electrode film, a ferroelectric film, and a second electrode film are accumulated above a semiconductor in this order, a hard mask is accumulated above the second electrode, scrub cleaning is performed on the surface of the hard mask with an surfactant, the hard mask on which the scrub cleaning is performed has been patterned according to a planar shape of a ferroelectric capacitor, and etching is performed by using as a hard mask the hard mask that has been patterned.

Abstract: According to an aspect of the invention, there is provided a semiconductor device including a semiconductor substrate, a lower electrode film formed on the semiconductor substrate, a dielectric film formed on the lower electrode film, and an upper electrode film formed on the dielectric film, wherein the lower electrode film, the dielectric film and the upper electrode film construct a capacitor in a predetermined region on the semiconductor substrate, the dielectric film is separated from the upper electrode film outside the predetermined region, and the dielectric film is formed continuously with respect to an adjacent cell.

Abstract: According to an aspect of the present invention, there is provided a semiconductor memory device, including a TC unit series-type FeRAM in which a plurality of memory cells, each of the memory cells comprising a memory transistor and a ferroelectric capacitor connected each other in parallel, are serially connected, including, a first electrode over and electrically connected to one of a source and a drain in the memory transistor, a second electrode opposed to the first electrode over and electrically connected to the other of the source and the drain in the memory transistor, a third electrode on both sidewalls of the second electrode other than an under portion of the second electrode, and a ferroelectric film between the first electrode and the two electrodes, the second electrode and the third electrode, wherein the ferroelectric capacitor comprises the first and the third electrode, and the ferroelectric film.

Abstract: A method of manufacturing a ferroelectric layer, including: forming a first ferroelectric layer above a base by a vapor phase method; and forming a second ferroelectric layer above the first ferroelectric layer by a liquid phase method.

Abstract: This disclosure relates to amorphous ferroelectric memory devices and methods for forming them.

Abstract: A semiconductor memory device includes: a transistor on a semiconductor substrate; an interlayer dielectric film covering the transistor; a ferroelectric capacitor comprising a first upper electrode, a ferroelectric film, and a lower electrode on the interlayer dielectric film; a contact plug which is in the interlayer dielectric film and electrically connects the lower electrode to the transistor; a second upper electrode on the first upper electrode, a side surface of the second upper electrode being formed in a forward tapered shape; and an interconnection electrically connected via the second upper electrode to the first upper electrode.

Abstract: A semiconductor device incorporating a capacitor structure that includes a ferroelectric thin film is obtained by forming, on a single crystalline substrate 10 having a surface suited for growing thereon a thin film layer of ferroelectric single crystal having a plane (111), a ferroelectric single crystalline thin film 12? containing Pb and having a plane (111) 11 in parallel with the surface of the substrate (or a ferroelectric polycrystalline thin film containing Pb and oriented parallel with the plane (111) in parallel with the surface of the substrate) and part 16 of a circuit of a semiconductor device, to thereby fabricate the single crystalline substrate 10 having said ferroelectric thin film containing Pb and said part of the circuit of the semiconductor device; and bonding said single crystalline substrate 10 to another substrate on which the other circuit of the semiconductor device has been formed in advance, to couple the two circuits together.

Abstract: According to an aspect of the present invention, there is provided a nonvolatile memory including: a cell transistor including: a gate electrode and first and second diffusion layers; a second insulating film covering the cell transistor; first and second plugs penetrating the second insulating film to reach the first and second diffusion layers, respectively; a ferroelectric capacitor having a ferroelectric film and first and second electrodes, the first electrode contacting with the first plug; a first conductive spacer contacting with the second plug and including the same material as the first electrode; a third insulating film covering side faces of the first electrode, the ferroelectric film and the first conductive spacer; and a first wiring that is continuously formed with the second electrode and connected to the first conductive spacer and that includes the same material as the second electrode.

Abstract: A lower electrode film is formed above a semiconductor substrate first, and then a ferroelectric film is formed on the lower electrode film. After that, an upper electrode film is formed on the ferroelectric film. When forming the upper electrode, an IrOx film containing crystallized small crystals when formed is formed on the ferroelectric film first, and then an IrOx film containing columnar crystals is formed.

Abstract: A semiconductor device includes a semiconductor substrate, a first electrode that is formed over said semiconductor substrate, a capacitive insulating film that is formed on the first electrode and is made of a metal oxide ferroelectric, a second electrode that is formed on the capacitive insulating film, an insulating film that has a first opening exposing a portion of an upper side of the second electrode and is formed so that it covers the first electrode, the capacitive insulating film, and the second electrode, a first barrier film having an amorphous structure which is formed inside the first opening and on the insulating film, and a wiring film that is formed over the first barrier film.

Abstract: Provided is a semiconductor device that includes: a base insulating film 25 formed above a silicon substrate 10; a ferroelectric capacitor Q formed on the base insulating film 25; multiple interlayer insulating films 35, 48, and 62, and metal interconnections 45, 58, and 72 which are alternately formed on and above the capacitor Q; and conductive plugs 57 which are respectively formed inside holes 54a provided in the interlayer insulating films 48 and are electrically connected to the metal interconnections 45. In the semiconductor device, a first capacitor protection insulating film 50 is formed on an upper surface of the interlayer insulating film 48 by sequentially stacking a first insulating metal oxide film 50a, an intermediate insulating film 50b having a relative dielectric constant lower than that of the interlayer insulating film 48, and a second insulating metal oxide film 50c; and the holes 54a are also formed in the first capacitor protection insulating film 50.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a PbTiOx film having a predominantly (111) orientation on a lower electrode as a nucleation layer by an MOCVD process with a film thickness exceeding 2 nm, and forming a PZT film having a predominantly (111) orientation on the nucleation layer, wherein the step of forming the PbTiOx film is conducted under an oxygen partial pressure of less than 340 Pa.

Abstract: According to the present invention, a method of fabricating a semiconductor device is provided including forming a first interlayer insulating film 11, a crystalline conductive film 21, a first conductive film 23, a ferroelectric film 24 and a second conductive film 25 on a silicon substrate 1 in sequence, forming a conductive cover film 18 on the second conductive film 25, forming a hard mask 26a on the conductive cover film 18, forming a capacitor upon etching the conductive cover film 18, the second conductive film 25, the ferroelectric film 24 and the first conductive film 23 using the hard mask 26a as an etching mask in areas exposed from the hard mask 26a, and etching the hard mask 26a and the crystalline conductive film 21 exposed from the lower electrode 23a using an etching condition under which the hard mask 26a is etched.

Abstract: A semiconductor device includes at least one phase-change pattern disposed on a semiconductor substrate. A planarized capping layer, a planarized protecting layer, and a planarized insulating layer are sequentially stacked to surround sidewalls of the at least one phase-change pattern. An interconnection layer pattern is disposed on the planarized capping layer, the planarized protecting layer, and the planarized insulating layer. The interconnection layer pattern is in contact with the phase-change pattern.

Abstract: A ferroelectric capacitor formation method necessary for stably fabricating an FeRAM and a semiconductor device fabrication method. After a PZT film is deposited on a lower electrode layer, the PZT film is crystallized by performing heat treatment in an atmosphere of a mixed gas which contains O2 gas and Ar gas. In this case, the flow rate of the O2 gas is controlled by one mass flow controller. The flow rate of the Ar gas used for purging and the flow rate of the Ar gas used for adjusting O2 gas concentration are controlled by different mass flow controllers. Before raising the temperature, the O2 gas, the Ar gas used for purging, and the Ar gas used for adjusting O2 gas concentration are made to flow at predetermined flow rates. Only the Ar gas used for purging is stopped, raising the temperature is begun, and the heat treatment is performed. At this time the O2 gas and the Ar gas used for adjusting O2 gas concentration flow at the predetermined flow rates.

Abstract: There are provided the steps of forming an insulating film over a semiconductor substrate, forming sequentially a first conductive film, a dielectric film, a second conductive film on the insulating film, etching the second conductive film and the dielectric film into a first pattern shape by using a first mask, removing the first mask, and etching simultaneously the first conductive film and the second conductive film having the first pattern shape by using a second mask to form a plurality of capacitor upper electrodes made of the second conductive film and also form a plate line as a capacitor lower electrode, which is covered with the dielectric film having the first pattern shape and has a contact region, made of the first conductive film. Accordingly, a plurality of capacitors can be formed on the capacitor lower electrode with good precision.

Abstract: A capacitor with zirconium oxide and a method for fabricating the same are provided. The method includes: forming a storage node; forming a multi-layered dielectric structure on the storage node, the multi-layered dielectric structure including a zirconium oxide (ZrO2) layer and an aluminum oxide (Al2O3) layer; and forming a plate electrode on the multi-layered dielectric structure.

Abstract: According to the present invention, a method of fabricating a semiconductor device is provided including forming a first interlayer insulating film 11, a crystalline conductive film 21, a first conductive film 23, a ferroelectric film 24 and a second conductive film 25 on a silicon substrate 1 in sequence, forming a conductive cover film 18 on the second conductive film 25, forming a hard mask 26a on the conductive cover film 18, forming a capacitor upon etching the conductive cover film 18, the second conductive film 25, the ferroelectric film 24 and the first conductive film 23 using the hard mask 26a as an etching mask in areas exposed from the hard mask 26a, and etching the hard mask 26a and the crystalline conductive film 21 exposed from the lower electrode 23a using an etching condition under which the hard mask 26a is etched.

Abstract: A ferroelectric memory device includes a semiconductor substrate, a first insulating film, a plurality of first and second plugs which extend through the first insulating film, conductive hydrogen barrier films, ferroelectric capacitor structural bodies, a first insulating hydrogen barrier film provided so as to cover the ferroelectric capacitor structural bodies, a second insulating film, local wirings extending on the second insulating film, a second insulating hydrogen barrier film which covers the local wirings, a third insulating film, third plugs which extend through the third insulating film so as to connect to their corresponding conductive hydrogen barrier films, and a first wiring layer extending on the third insulating film.

Abstract: A ferroelectric film having a ferroelectric shown by a general formula (Pb1-dBid)(B1-aXa)O3, B including at least one of Zr and Ti, X including at least one of Nb and Ta, “a” being in a range of “0.05?a?0.4”, and “d” being in a range of “0<d<1”.

Abstract: In a method for forming a semiconductor device, a device isolation layer is formed in a capacitor region of a silicon substrate, and a bottom electrode and a dielectric layer are formed on the device isolation layer. Insulation sidewalls are formed on both sides of the bottom electrode. A top electrode is formed on the dielectric layer, and simultaneously a gate electrode is formed in a transistor region of the silicon substrate. Source/drain impurity regions are formed in the silicon substrate at both sides of the gate electrode.

Abstract: A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of row and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes.

Abstract: A ferroelectric memory device, which includes a vertical ferroelectric capacitor having an electrode distance smaller than a minimum feature size of lithography technology being used and suitable for the miniaturization, and a method of manufacturing the same are disclosed. According to one aspect of the present invention, it is provided a ferroelectric memory device comprising an MIS transistor formed on a substrate, and a ferroelectric capacitor formed on an interlevel insulator above the MIS transistor, wherein a pair of electrodes of the ferroelectric capacitor are disposed in a channel length direction of the MIS transistor to face each other putting a ferroelectric film in-between, and wherein a distance between the electrodes of the ferroelectric capacitor is smaller than a gate length of the MIS transistor.