Abstract: The invention provides a semiconductor device having a ferroelectric substance capacitor small in the occupying area and large in capacitance and a semiconductor device having a ferroelectric substance capacitor reducing influence of noise and being few in malfunctions. The semiconductor device includes a first capacitor formed on a surface of a semiconductor substrate and a second capacitor of a ferroelectric substance capacitance laminated on the first capacitor so as to connect in series.

Abstract: A semiconductor memory cell and production method provides a storage capacitor connected to a selection transistor. The storage capacitor is formed as a contact hole capacitor in at least one contact hole for a source or drain region. Such a semiconductor memory cell can be produced cost-effectively and allows a high integration density.

Abstract: A method for manufacturing a memory device comprises patterning a dielectric layer and a conductive layer to align near the center of the top surface of a first contact drain plug and near the center of the top surface of a second contact drain plug. A first electrode is formed on the right sidewalls of the patterned dielectric layer and the conductive layer. A sidewall insulating member has a first sidewall surface and a second sidewall surface where the first sidewall surface of the sidewall insulating member is in contact with a sidewall of the first electrode. A second electrode is formed by depositing an electrode layer overlying the top surface of the sidewall insulating member and the second sidewall of the insulating member and isotropically etching the electrode layer to form the second electrode.

Abstract: According to an aspect of the present invention, there is provided a semiconductor memory device including a ferroelectric capacitor, including a semiconductor substrate, a transistor having diffusion layers being a source and a drain, the transistor being formed on a surface of the semiconductor substrate, a ferroelectric capacitor being formed over the transistor, the ferroelectric capacitor including a lower electrode, a ferroelectric film and an upper electrode stacked in order, an interlayer insulator separating between the transistor and the ferroelectric capacitor, a first contact plug being embedded in the interlayer insulator formed beneath the ferroelectric capacitor, the first contact plug directly connecting between one of the diffusion layers and the lower electrode, a first hydrogen barrier film covering the transistor a second hydrogen barrier film, a portion of the second hydrogen barrier film being formed on the first hydrogen barrier film, another portion of the second hydrogen barrier film

Abstract: A semiconductor device includes: a semiconductor substrate; a MOS transistor formed in the semiconductor substrate and having an insulated gate and source/drain regions on both sides of the insulated gate; a ferroelectric capacitor formed above the semiconductor substrate and having a lower electrode, a ferroelectric layer and an upper electrode; a metal film formed on the upper electrode and having a thickness of a half of or thinner than a thickness of the upper electrode; an interlayer insulating film burying the ferroelectric capacitor and the metal film; a conductive plug formed through the interlayer insulating film, reaching the metal film and including a conductive glue film and a tungsten body; and an aluminum wiring formed on the interlayer insulating film and connected to the conductive plug. A new problem near an upper electrode contact is solved which may otherwise be caused by adopting a W plug over the F capacitor.

Abstract: A ferroelectric capacitor includes a bottom electrode, a ferroelectric layer formed on the bottom electrode, and a top electrode formed on the ferroelectric layer. A plurality of projection electrodes are formed on the bottom electrode.

Abstract: A semiconductor device includes: a semiconductor substrate and a transistor formed on the semiconductor substrate. The semiconductor device also includes: a first interlayer insulation film formed on the semiconductor substrate including the upper portion of the transistor, a first contact formed to be connected through the first interlayer insulation film to the transistor, a ferroelectric capacitor formed to be connected to the first contact, a second interlayer insulation film formed on the first interlayer insulation film, and a second contact formed to connect the ferroelectric capacitor to a wiring through the second interlayer insulation film. The contact surfaces between the second contact and the ferroelectric capacitor have the same planar shape.

Abstract: A semiconductor device according to an aspect of the present invention comprises a semiconductor substrate, a ferroelectric capacitor, a protective film and an auxiliary capacitor. The ferroelectric capacitor is provided above the semiconductor substrate and comprises an upper electrode, a lower electrode and a ferroelectric film interposed between the upper and lower electrodes. The protective film is formed, covering the ferroelectric capacitor. The auxiliary capacitor is provided in a circuit section peripheral to the ferroelectric capacitor and uses the protective film as capacitor insulating film.

Abstract: A ferroelectric capacitor including a bottom electrode (15), a ferroelectric film (16) and a top electrode (17) is covered with an interlayer insulating film (18). One end of the bottom electrode (15) is formed like comb teeth. To match with the remaining portion of that end, a plurality of contact holes (21) are formed in the interlayer insulating film (18). In other words, gaps (notches) are formed in the bottom electrode (15) between lower ends of at least two of the contact holes (21). And a wiring (25) connected to the bottom electrode (15) through the contact holes (21) is formed on the interlayer insulating film (18).

Abstract: The present invention is to provide a semiconductor memory device capable of providing excellent storage properties, scaling and high integration and a method of fabricating the same. A semiconductor memory device has a multiferroic film exhibiting ferroelectricity and ferromagnetism, a channel region on an interface of a semiconductor substrate below the multiferroic film, source and drain regions formed on both sides of the channel region, a gate electrode (data write electrode) applying gate voltage to the multiferroic film to write data in such a way that the orientation of magnetization is changed as corresponding to the orientation of dielectric polarization, and source and drain electrodes (data read electrodes) that read data based on a deviation in a flow of the carrier, the deviation caused by applying the Lorentz force to the carrier flowing in the channel region from a magnetic field occurring in the channel region because of magnetization.

Abstract: Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are provided. A self-limiting nitric oxide (NO) anneal of a polysilicon layer such as an HSG polysilicon capacitor electrode, at less than 800° C., is utilized to grow a thin oxide (oxynitride) layer of about 40 angstroms or less over the polysilicon layer. The NO anneal provides a nitrogen layer at the polysilicon-oxide interface that limits further oxidation of the polysilicon layer and growth of the oxide layer. The oxide layer is exposed to a nitrogen-containing gas to nitridize the surface of the oxide layer and reduce the effective dielectric constant of the oxide layer. The process is particularly useful in forming high K dielectric insulating layers such as tantalum pentoxide over polysilicon.

Abstract: A three-dimensional (“3-D”) memory capacitor comprises a bottom electrode, a ferroelectric thin film, and a top electrode that conform to a 3-D surface of an insulator layer. The capacitance area is greater than the horizontal footprint area of the capacitor. Preferably, the footprint of the capacitor is less than 0.2 nm2, and the corresponding capacitance area is typically in a range of from 0.4 nm2 to 1.0 nm2 The ferroelectric thin film preferably has a thickness not exceeding 60 nm. A capacitor laminate including the bottom electrode, ferroelectric thin film, and the top electrode preferably has a thickness not exceeding 200 nm. A low-thermal-budget MOCVD method for depositing a ferroelectric thin film having a thickness in a range of from 30 nm to 90 nm includes an RTP treatment before depositing the top electrode and an RTP treatment after depositing the top electrode and etching the ferroelectric layer.

Abstract: A method for non-volatile memory fabrication is provided, in which a substrate is provided, a bottom electrode is formed on the substrate, a solution with precursors of Zr and Sr is coated on the bottom electrode, the solution on the bottom electrode surface is dried and then fired to form a resistor layer of SrZrO3, and a top electrode is formed on the resistor layer.

Abstract: A semiconductor device fabrication method includes the steps of forming a conductive plug in an insulating layer on a semiconductor substrate so as to be connected to an element on the substrate; forming a titanium aluminum nitride (TiAlN) oxygen barrier film over the conductive plug; forming a titanium (Ti) film over the oxygen barrier film; applying a thermal process to the titanium film in nitrogen atmosphere to allow the titanium film to turn into a titanium nitride (TiN) film; and forming a lower electrode film of a capacitor over the titanium nitride film.

Abstract: This disclosure concerns a semiconductor device comprising a switching transistor provided on a semiconductor substrate; an interlayer dielectric film formed on the switching transistor; a ferroelectric capacitor including an upper electrode, a ferroelectric film, and a lower electrode formed on the interlayer dielectric film; a contact plug provided within the interlayer dielectric film and electrically connected to the lower electrode; a diffusion layer connected to between the contact plug and the switching transistor; a barrier metal covering a whole upper surface of the upper electrode; and an insulation sidewall film provided on a side surface of the barrier metal and provided substantially on a same plane as a side surface of the upper electrode.

Abstract: A capacitor includes a pair of electrodes and a ferroelectric film sandwiched between the electrodes. The electrodes are provided perpendicular to the direction of the polarization axis of the ferroelectric film.

Abstract: The present invention provides a method for manufacturing a semiconductor device, including the steps of: forming a ferroelectric film on a first conductive film by a sol-gel method; forming a first conductive metal oxide film on the ferroelectric film; carrying out a first annealing on the first conductive metal oxide film; forming a second conductive metal oxide film on the first conductive metal oxide film, so that the first and second conductive films serve as a second conductive film; and forming a capacitor by patterning the first conductive film, the ferroelectric film and the second conductive film. In the step of forming the first conductive metal oxide film, ferroelectric characteristics are adjusted with a flow rate ratio of oxygen by utilizing the fact that the ferroelectric characteristics of the ferroelectric film improve as the flow rate ratio of oxygen in a sputtering gas increases.

Abstract: Provided is a method for manufacturing a material layer capable of increasing the deposition rate of a noble metal layer on a ferroelectric layer, a method for manufacturing a ferroelectric capacitor using the same, a ferroelectric capacitor manufactured by the same method, and a semiconductor memory device having the ferroelectric capacitor and a manufacturing method thereof. According to a method for manufacturing the material layer, a ferroelectric layer is formed. The ferroelectric layer may be exposed to seed plasma, and a material layer including a source material of the seed plasma may be formed on a region of the ferroelectric layer exposed to the seed plasma.

Abstract: According to an aspect of the present invention, there is provided a semiconductor apparatus including: a semiconductor substrate; a transistor including: a first diffusion layer formed on the semiconductor substrate, and a second diffusion layer formed on the semiconductor substrate; a ferroelectric capacitor including: a bottom electrode connected to the first diffusion layer, a ferroelectric film formed on the bottom electrode, and a top electrode formed on the ferroelectric film; a side wall disposed on a side surface of the ferroelectric capacitor, the side wall having a lower end positioned upper than a bottom plane of the ferroelectric capacitor; and a contact plug connected to the second diffusion layer and to the top electrode, the contact plug being in touch with the side wall.

Abstract: A capacitor is formed on an interlayer insulating film formed on a semiconductor substrate. The capacitor includes a bottom electrode made of platinum, a capacitor insulating film made of SrTaBiO (SBT) containing an element absorbing hydrogen such as titanium, for example, in grain boundaries, inter-lattice positions or holes, and a top electrode made of platinum.

Abstract: Two ferroelectric capacitors including a PZT film are connected to one MOS transistor. Electrodes of the ferroelectric capacitor are arranged above a main plane of a substrate parallel to the main plane. Therefore, high capacity can be obtained easily. Furthermore, a (001) direction of the PZT film is parallel to the virtual straight line linking between the two electrodes. Therefore, a direction in which an electric field is applied coincides with a direction of a polarization axis, so that high electric charge amount of remanent polarization can be obtained.

Abstract: A semiconductor memory device, which prevents the penetration of hydrogen or moisture to a ferroelectric capacitor from its surrounding area including a contact plug portion, comprises a ferroelectric capacitor formed above a semiconductor substrate, a first hydrogen barrier film formed on an upper surface of the ferroelectric capacitor to work as a mask in the formation of the ferroelectric capacitor, a second hydrogen barrier film formed on the upper surface and a side face of the ferroelectric capacitor including on the first hydrogen barrier film, and a contact plug disposed through the first and second hydrogen barrier films, and connected to an upper electrode of the ferroelectric capacitor, a side face thereof being surrounded with the hydrogen barrier films.

Abstract: A method for manufacturing a ferroelectric capacitor, includes the steps of: forming a ferroelectric capacitor layer having a lower electrode layer, a ferroelectric layer and an upper electrode layer on a base substrate; forming a titanium oxide layer on the ferroelectric capacitor layer; patterning the titanium oxide layer by high-temperature etching between 200° C. and 500° C. to thereby form a mask pattern; and etching the ferroelectric capacitor layer by using the mask pattern as a mask, to thereby form a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode.

Abstract: A PLZT film (30) is formed as the material film of a capacitor dielectric film and a top electrode film (31) is formed on the PLZT film (30). The top electrode film (31) comprises two IrOx films having different composition. Subsequently, back face of a semiconductor substrate (11) is cleaned and an Ir adhesion film (32) is formed on the top electrode film (31). Substrate temperature is set at 400° C. or above at that time. Thereafter, a TiN film and a TEOS film are formed sequentially as a hard mask. In such a method, carbon remaining on the top electrode film (31) after cleaning the back face is discharged into the chamber while the temperature of the semiconductor substrate (11) is kept at 400° C. or above in order to form the Ir adhesion film (32). Consequently, adhesion is enhanced between a TiN film being formed subsequently and the Ir adhesion film (32) thus preventing the TiN film from being stripped.

Abstract: A semiconductor memory, comprising: a first memory cell transistor disposed on a semiconductor substrate; a second memory cell transistor disposed on the semiconductor substrate and having a first source-drain region in common with the first memory cell transistor; a first ferroelectric capacitor disposed with a via in between above a second source-drain region of the first memory cell transistor; a second ferroelectric capacitor disposed with a via in between above a second source-drain region of the second memory cell transistor; an interlayer dielectric disposed on the semiconductor substrate, as coating the memory cell transistors and the ferroelectric capacitors, the interlayer dielectric having a contact hole through which the first source-drain region is partially exposed at the bottom and upper electrodes of the first and second ferroelectric capacitors are partially exposed at the top; and a wiring layer filled into the contact hole, which connects the first source-drain region, the upper electrode o

Abstract: A method of fabricating semiconductor devices. Upon formation of a trench for isolation in a cell region, a hard mask film is used as an etch mask. It is thus possible to prevent attacks of a lower layer due to deformation or loss of the etch mask.

Abstract: A ferroelectric device employs ferroelectric electrodes as local interconnect(s). One or more circuit features are formed within or on a semiconductor body. A first dielectric layer is formed over the semiconductor body. Lower contacts are formed within the first dielectric layer. A bottom electrode is formed over the first dielectric layer and on the lower contacts. A ferroelectric layer is formed on the bottom electrode. A top electrode is formed on the ferroelectric layer. A second dielectric layer is formed over the first dielectric layer. Upper contacts are formed within the second dielectric layer and in contact with the top electrode. Conductive features are formed on the upper contacts.

Abstract: A method of manufacturing a semiconductor device includes: forming a circuit element on a semiconductor substrate; forming a first insulation film on top to cover the circuit element; forming a first electrode on top; forming a ferroelectric film on the first electrode; forming a second electrode on the ferroelectric film; forming a mask film on the second electrode; etching the second electrode with the semiconductor substrate or a mounting electrode set to a first temperature using the mask film as a mask; etching the ferroelectric film with the semiconductor substrate or the mounting electrode set to a second temperature using the mask film as a mask, the second temperature being lower than the first temperature; and etching the first electrode with the semiconductor substrate or the mounting electrode set to a third temperature using the mask film as a mask, the third and first temperatures being approximately the same.

Abstract: An Ir film, an IrOx film, a Pt film, a PtO film and a Pt film are formed, and thereafter a PLZT film is formed. Then, heat treatment at 600° C. or lower is performed by the RTA method in an atmosphere containing Ar and O2 to thereby crystallize the PLZT film. Subsequently, an IrOx film and an IrO2 film are formed. Then, these films are patterned at once. Thereafter, an alumina film is formed as a protective film. Subsequently, heat treatment at 650° C. for 60 minutes in an oxygen atmosphere is performed as recovery annealing. Note that no heat treatment is performed from the crystallization of the PLZT film to the recovery annealing.

Abstract: The present invention relates to a capacitor in a semiconductor device and a method for fabricating the same. The capacitor fabrication method includes the steps of: forming a lower electrode by using a thin film of (Ba,Sr)RuO3 (BSR) on a substrate provided with various device elements; forming a dielectric layer on the lower electrode by using a thin film of barium strontium titanate (BST); and forming an upper electrode on the dielectric layer.

Abstract: A ferroelectric memory device may include a substrate, an interlayer insulating layer on the semiconductor substrate, a contact plug penetrating the interlayer insulating layer, the contact plug being formed of a sequentially stacked metal plug and buffer plug, a conductive protection pattern covering the contact plug, the conductive protection pattern being a conductive oxide layer, a lower electrode, a ferroelectric pattern, and an upper electrode sequentially stacked on the conductive protection pattern, and an insulating protection layer covering the sequentially stacked lower electrode, ferroelectric pattern, and upper electrode.

Abstract: A ferroelectric capacitor circuit for sensing hydrogen gas having a closed integrated circuit package, a ferroelectric capacitor within the closed integrated circuit package, the ferroelectric capacitor having a bismuth oxide based ferroelectric layer being able to absorb hydrogen gas that is within the closed integrated circuit package, absorbed hydrogen gas chemically reducing a portion of the bismuth oxide based ferroelectric layer into bismuth metal, the ferroelectric capacitor having a ferroelectric voltage, the ferroelectric voltage having a voltage strength, and means for measuring a decrease in the voltage strength of the ferroelectric voltage of the ferroelectric capacitor.

Abstract: A conduction film 36 is formed in a larger design thickness value on a ferroelectric film 32 by MOCVD, and the entire surface of the conduction film 36 is anisotropically etched back, whereby the surface morphology of the conduction film 36 can be improved. The conduction film 36, whose surface morphology has been improved and which has been flattened, can be patterned by photolithography without the reflection of the incident exposure light in various directions, and a desired pattern as designed can be formed. The method for fabricating a semiconductor device can improve the surface morphology of a ferroelectric film formed by organic metal chemical vapor deposition.

Abstract: A capacitor of a memory device, and a method of fabricating the same, includes a lower electrode electrically coupled to a doping region of a transistor structure, the lower electrode having a metal electrode and a metal oxide electrode, a ferroelectric layer covering and extending laterally along the lower electrode, and an upper electrode formed on the ferroelectric layer.

Abstract: A method of fabricating a conductive metal oxide gate ferroelectric memory transistor includes forming an oxide layer a substrate and removing the oxide layer in a gate area; depositing a conductive metal oxide layer on the oxide layer and on the exposed gate area; depositing a titanium layer on the metal oxide layer; patterning and etching the titanium layer and the metal oxide layer to remove the titanium layer and the metal oxide layer from the substrate except in the gate area; depositing, patterning and etching an oxide layer to form a gate trench; depositing and etching a barrier insulator layer to form a sidewall barrier in the gate trench; removing the titanium layer from the gate area; depositing, smoothing and annealing a ferroelectric layer in the gate trench; depositing, patterning and etching a top electrode; and completing the conductive metal oxide gate ferroelectric memory transistor.

Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.

Abstract: Metal organic chemical vapor deposition (MOCVD) may be utilized in methods of forming an (111) oriented PZT ferroelectric layer at a lower temperature, a ferroelectric capacitor and methods of fabricating, and a ferroelectric memory device using the same may be provided. Using the metal organic chemical vapor deposition, ferroelectric layers, capacitors, and memory devices, which may be fabricated and may have (111) preferred oriented crystal growth.

Abstract: A semiconductor device includes: a lower hydrogen-barrier film; a capacitor formed on the lower hydrogen-barrier film and including a lower electrode, a capacitive insulating film, and an upper electrode; an interlayer dielectric film formed so as to cover the periphery of the capacitor; and an upper hydrogen-barrier film covering the top and lateral portions of the capacitor. An opening, which exposes the lower hydrogen-barrier film where the lower hydrogen-barrier film is located around the capacitor, and which is tapered and flares upward, is formed in the interlayer dielectric film, and the upper hydrogen-barrier film is formed along the lateral and bottom faces of the opening, and is in contact with the lower hydrogen-barrier film in the opening.

Abstract: A W plug (24) is formed and a W oxidation preventing barrier metal film (25) is formed thereon. After that, an SiON film (27) thinner than the W oxidation preventing barrier metal film (25) is formed and Ar sputter etching is performed on the SiON film (27). As a result, the shape of the surface of the SiON film (27) becomes gentler and deep trenches disappear. Next, an SiON film (28) is formed on the whole surface. A voidless W oxidation preventing insulating film (29) is composed of the SiON (28) film and the SiON film (27).

Abstract: The invention relates to a ferroelectric device (10) with a body (11) comprising a substrate (1) and a ferroelectric layer (2) provided with a connection conductor (3) on a side facing away from the substrate (1), which ferroelectric layer contains an oxygen-free ferroelectric material (2) and is used to form an active electrical element (4), in particular a memory element (4). Such a device forms an attractive non-volatile memory device. In accordance with the invention, a conductive layer (5) is present between the substrate (1) and the ferroelectric layer (2), which conductive layer forms a further connection conductor (5) of the ferroelectric layer (2), and the active electrical element (4) is obtained as a result of the fact that the ferroelectric layer (2) forms a Schottky junction with at least one of the connection conductors (3, 5).

Abstract: An integrated circuit and a manufacturing method thereof are provided. A chip size can be reduced by forming a memory device in which a ferroelectric capacitor region is laminated on a DRAM. The integrated circuit includes a cell array region having a capacitor, a peripheral circuit region, and a ferroelectric capacitor region being formed on an upper layer of the cell array region and the peripheral circuit region, and having a ferroelectric capacitor device.

Abstract: A ferroelectric memory capacitor is formed by forming a barrier layer, a first metal layer, a ferroelectric layer, a second metal layer, and a hard mask layer, on dielectric layer (70). Using the patterned hard mask layer (255), the layers are etched to form an etched barrier layer (205), and etched first metal layer (215), and etched ferroelectric layer (225), and etched second metal layers (235, 245). The etched layers form a ferroelectric memory capacitor (270) with sidewalls that form an angle with the plane of the upper surface of the dielectric layer (70) between 78° and 88°. The processes used to etch the layers are plasma processes performed at temperatures between 200° C. and 500° C.

Abstract: A ferroelectric/paraelectric multilayer thin film having a high tuning rate of a dielectric constant and small dielectric loss to overcome limitations of a tuning rate of a dielectric constant and dielectric loss of a ferroelectric thin film, a method of forming the same, and a high frequency variable device having the ferroelectric/paraelectric multilayer thin film are provided. The ferroelectric/paraelectric multilayer thin film includes a perovskite ABO3 structure paraelectric seed layer formed on a substrate, and an epitaxial ferroelectric (BaxSr1-x)TiO3 thin film formed on the paraelectric seed layer. The high frequency variable device can realize a RF frequency/phase variable device having a high speed, low power consumption, and low prices and excellent microwaves characteristics.

Abstract: A method for manufacturing a ferroelectric memory includes: (a) forming first and second contact sections on a first dielectric layer formed above a base substrate; (b) forming a laminated body having a lower electrode, a ferroelectric layer and an upper electrode successively laminated; (c) forming a conductive hard mask above the laminated body and etching an area of the laminated body exposed through the hard mask, to thereby form a ferroelectric capacitor above the first contact section; (d) forming above the first dielectric layer a second dielectric layer that covers the hard mask, the ferroelectric capacitor and the second contact section; (e) forming a contact hole in the second dielectric layer which exposes the second contact section; (f) providing a conductive layer in an area including the contact hole for forming a third contact section; and (g) polishing the conductive layer and the second dielectric layer until the hard mask above the ferroelectric capacitor is exposed.

Abstract: A ferroelectric capacitor includes a pair of electrodes, and at least one ferroelectric held between the pair of electrodes, in which the ferroelectric includes a first ferroelectric layer having a surface roughness (RMS) determined with an atomic force microscope of 10 nm or more; and a second ferroelectric layer being arranged adjacent to the first ferroelectric layer and having an RMS of 5 nm or less. A process produces such a ferroelectric capacitor by forming a first ferroelectric layer on or above one of a pair of electrodes at a temperature equal to or higher than a crystallization temperature at which the first ferroelectric layer takes on a ferroelectric crystalline structure, and forming a second ferroelectric layer on the first ferroelectric layer at a temperature lower than a crystallization temperature at which the second ferroelectric layer takes on a ferroelectric crystalline structure.

Abstract: A semiconductor substrate formed with a MOSFET is prepared, and a first interlayer insulating film is deposited on the semiconductor substrate. A ferroelectric capacitor is formed on the first interlayer insulating film. Next, a second interlayer insulating film is formed on a first structure provided with the semiconductor substrate, the first interlayer insulating film and the ferroelectric capacitor so as to embed the ferroelectric capacitor therein. Openings for electrically connecting the MOSFET and the ferroelectric capacitor and an external circuit of a ferroelectric memory are formed in the second interlayer insulating film to form a second structure. A metal wiring is formed on the second interlayer insulating film to form a third structure. Next, the third structure is heat-treated in an atmosphere from over 350° C. to under 450° C.

Abstract: A method for manufacturing a ferroelectric capacitor in accordance with the present invention includes: (a) a step of forming a ferroelectric laminated body by successively laminating a lower electrode layer, a ferroelectric layer and an upper electrode layer over a base substrate; (b) a step of patterning at least the upper electrode layer and the ferroelectric layer by dry etching; (c) a step of coating a coating composition including a compound having an element composing the ferroelectric layer at least on a side wall of the ferroelectric layer; and (d) a step of thermally treating the coating composition, to crystallize the coating composition coated on the side wall of the ferroelectric layer.

Abstract: A semiconductor device including a ferroelectric random access memory, which has a structure suitable for miniaturization and easy to manufacture, and having less restrictions on materials to be used, comprises a field effect transistor formed on a surface area of a semiconductor wafer, a trench ferroelectric capacitor formed in the semiconductor wafer in one source/drain of the field effect transistor, wherein one electrode thereof is connected to the source/drain, and a wiring formed in the semiconductor wafer and connected to the other electrode of the trench ferroelectric capacitor.

Abstract: A memory device comprising a layer of piezoelectric material and a layer of ferroelectric material clamped together such that a voltage applied to one layer results in a voltage being generated across the other layer. The method of data storage and retrieval comprising the steps of: providing a layer of ferroelectric material, providing a layer of piezoelectric material, clamping the two layers together, storing data by internally polarising the ferroelectric material in one of two stable directions in accordance with the data to be stored, and retrieving stored data by applying a non-polarising voltage to one layer and detecting a resultant voltage from the other layer. Preferably, the piezoelectric material is implemented as a ferroelectric material.

Abstract: The present invention provides a semiconductor device including a semiconductor element and a dummy semiconductor element adjacent to the semiconductor element. When the semiconductor element is a capacitor element including a bottom electrode, a top electrode and a dielectric layer between the electrodes, a dummy capacitor element also has dummy electrodes and a dummy dielectric layer between the dummy electrodes. The dummy electrode is located so that a space between the top electrode of the capacitor element ad the dummy top electrode is in a predetermined range (e.g. 0.3 ?m to 14 ?m). The dummy capacitor element prevents the capacitor dielectric layer from degrading since the collisions of the etching ions with the capacitor dielectric layer in a dry etching process is suppressed.