Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract: A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.

Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor chip that has a first conductor pad and a passivation structure. A second conductor pad is fabricated around but not in physical contact with the first conductor pad to leave a gap. The second conductor pad is adapted to protect a portion of the passivation structure.

Abstract: A semiconductor package is assembled using first and second lead frames. The first lead frame includes a die flag and the second lead frame includes lead fingers. When the first and second lead frames are mated, the lead fingers surround the die flag. Side surfaces of the die flag are partially etched to form an extended die attach surface on the die flag, and portions of the top surface of each of the lead fingers also are partially etched to form lead finger surfaces that are complementary with the etched side surfaces of the die flag. A semiconductor die is attached to the extended die attach surface and bond pads of the semiconductor die are electrically connected to the lead fingers. An encapsulating material covers the die, electrical connections, and top surfaces of the die flag and lead fingers.

Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a first lead frame having a first die paddle, and a second lead frame, which has a second die paddle and a plurality of leads. The second die paddle is disposed over the first die paddle. A semiconductor chip is disposed over the second die paddle. The semiconductor chip has a plurality of contact regions on a first side facing the second lead frame. The plurality of contact regions is coupled to the plurality of leads.

Abstract: Embodiments of the present invention are directed to a thermal leadless array package with die attach pad locking feature and methods of producing the same. A copper layer is half-etched on both surfaces to define an array of package contacts and a die attach pad. Each die attach pad is fully embedded in encapsulate material to provide a positive mechanical locking feature for better reliability. In some embodiments, the contacts include four active corner contacts.

Abstract: A Quad Flat No-Lead (QFN) semiconductor package includes a die pad; I/O connections disposed at the periphery of the die pad; a chip mounted on the die pad; bonding wires; an encapsulant for encapsulating the die pad, the I/O connections, the chip and the bonding wires while exposing the bottom surfaces of the die pad and the I/O connections; a surface layer formed on the bottoms surfaces of the die pad and the I/O connections; a dielectric layer formed on the bottom surfaces of the encapsulant and the surface layer and having openings for exposing the surface layer. The surface layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the die pad and prevent solder extrusion on the interface of the I/O connections and the dielectric layer, thereby increasing product yield.

Abstract: In accordance with an embodiment of the present invention, a semiconductor device includes a leadframe having a plurality of leads and a die paddle and a semiconductor module attached to the die paddle of the leadframe. The semiconductor module includes a first semiconductor chip disposed in a first encapsulant. The semiconductor module has a plurality of contact pads coupled to the first semiconductor chip. The semiconductor device further includes a plurality of interconnects coupling the plurality of contact pads with the plurality of leads, and a second encapsulant disposed at the semiconductor module and the leadframe.

Abstract: One embodiment is directed towards a method of manufacturing a packaged circuit. The method includes partially etching an internal surface of a lead frame at dividing lines between future sections of the lead frame as first partial etch. One or more dies are attached to the internal surface of the lead frame and encapsulated. The method also includes partially etching an external surface of the lead frame at the dividing lines to disconnect different sections of lead frame as a second partial etch, wherein the second partial etch removes a laterally wider portion of the lead frame than the first partial etch of the internal surface; and partially etching the external surface of the lead frame as a third partial etch, wherein the third partial etch overlaps a portion of the second partial etch and extends deeper into the lead frame than the second partial etch.

Abstract: A semiconductor package and a method for fabricating the same are provided. A leadframe including a die pad and a plurality of peripheral leads is provided. A carrier, having a plurality of connecting pads formed thereon, is attached to the die pad, wherein a planar size of the carrier is greater than that of the die pad, allowing the connecting pads on the carrier to be exposed from the die pad. At least a semiconductor chip is attached to a side of an assembly including the die pad and the carrier, and is electrically connected to the connecting pads of the carrier and the leads via bonding wires. A package encapsulant encapsulates the semiconductor chip, the bonding wires, a part of the carrier and a part of the leadframe, allowing a bottom surface of the carrier and a part of the leads to be exposed from the package encapsulant.

Abstract: A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented.

Abstract: An electroless Cu layer is formed on each side of a packaging substrate containing a core, at least one front metal interconnect layer, and at least one backside metal interconnect layer. A photoresist is applied on both electroless Cu layers and lithographically patterned. First electrolytic Cu portions are formed on exposed surfaces of the electroless Cu layers, followed by formation of electrolytic Ni portions and second electrolytic Cu portions. The electrolytic Ni portions provide enhanced resistance to electromigration, while the second electrolytic Cu portions provide an adhesion layer for a solder mask and serves as an oxidation protection layer. Some of the first electrolytic Cu may be masked by lithographic means to block formation of electrolytic Ni portions and second electrolytic Cu portions thereupon as needed. Optionally, the electrolytic Ni portions may be formed directly on electroless Cu layers.

Abstract: A semiconductor package and it manufacturing method includes a lead frame having a die pad, and a source lead with substantially a V groove disposed on a top surface. A semiconductor chip disposed on the die pad. A metal plate connected to a top surface electrode of the chip having a bent extension terminated in the V groove in contact with at least one of the V groove sidewalls.

Abstract: A semiconductor package comprises a die attach pad and a support member at least partially circumscribing it. Several sets of contact pads are attached to the support member. The support member is able to be etched away thereby electrically isolating the contact pads. A method for making a leadframe and subsequently a semiconductor package comprises partially etching desired features into a copper substrate, and then through etching the substrate to form the support member and several sets of contact pads. Die attach, wirebonding and molding follow. The support member is etched away, electrically isolating the contact pads and leaving a groove in the bottom of the package. The groove is able to be filled with epoxy or mold compound.

Abstract: Some exemplary embodiments of an advanced direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a mold compound enclosing a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached on top of the lead frame portions as a flip chip, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations.

Abstract: Some exemplary embodiments of an advanced direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a mold compound enclosing a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached on top of the lead frame portions as a flip chip, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a mounting region; applying a mounting structure in the mounting region; mounting an integrated circuit die on the mounting structure; forming an encapsulation on the integrated circuit die and having an encapsulation cavity, the encapsulation cavity shaped by the mounting structure; forming a lead having a lead protrusion from the leadframe, the lead protrusion below a horizontal plane of the integrated circuit die; and removing the mounting structure for exposing the integrated circuit die.

Abstract: A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.

Abstract: A semiconductor package includes a baseplate having a die attach region and a peripheral region, a transistor die having a first terminal attached to the die attach region, and a second terminal and a third terminal facing away from the baseplate, and a frame including an electrically insulative member having a first side attached to the peripheral region of the baseplate, a second side facing away from the baseplate, a first metallization at the first side of the insulative member and a second metallization at the second side of the insulative member. The insulative member extends outward beyond a lateral sidewall of the baseplate. The first metallization is attached to the part of the first side which extends outward beyond the lateral sidewall of the baseplate. The first and second metallizations are electrically connected at a region of the insulative member spaced apart from the lateral sidewall of the baseplate.

Abstract: According to an embodiment, a semiconductor device includes a first frame, a semiconductor element fixed to the first frame, a second frame, a third frame and a resin package. The second frame faces the first frame and is away from the first frame, the second frame being electrically connected to the semiconductor element via a metal wire. The resin package covers the semiconductor element, the first frame, and the second frame. The first frame and the second frame are exposed in one major surface of the resin package. The third frame juxtaposed to one of the first frame and the second frame, the third frame being continuously exposed from the major surface of the resin package to a side surface in contact with the major surface.

Abstract: An integrated circuit package system is provided including an integrated circuit package system including an integrated circuit and a lead frame. The lead frame has a multi-surface die attach pad and the integrated circuit is mounted to the multi-surface die attach pad.

Abstract: An integrated circuit leadframe and a fabrication method for fabricating the integrated circuit leadframe include forming a leadframe having leads around a die pad that has a peripheral die pad rim. A discrete, alternately staggered surface configuration is formed in the die pad rim. The discrete, alternately staggered surface configuration creates space in the die pad for connecting and separating ground bond wire-bonds and down bond wire-bonds, and provides for locking encapsulant firmly to the die pad.

Abstract: A semiconductor package method for co-packaging high-side (HS) and low-side (LS) semiconductor chips is disclosed. The HS and LS semiconductor chips are attached to two opposite sides of a lead frame, with a bottom drain electrode of the LS chip connected to a top side of the lead frame and a top source electrode of the HS chip connected to a bottom side of the lead frame through a solder ball. The stacking configuration of HS chip, lead frame and LS chip reduces the package size. A bottom metal layer covering the bottom of HS chip exposed outside of the package body provides both electrical connection and thermal conduction.

Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

Abstract: A semiconductor encapsulation comprises a lead frame further comprising a chip carrier and a plurality of pins in adjacent to the chip carrier. A plurality of grooves opened from an upper surface of the chip carrier partially dividing the chip carrier into a plurality of chip mounting areas. A bottom portion of the grooves is removed for completely isolate each chip mounting area, wherein a width of the bottom portion of the grooves removed is smaller than a width of the grooves. In one embodiment, a groove is located between the chip carrier and the pins with a bottom portion of the groove removed for isolate the pins from the chip carrier, wherein a width of the bottom of the grooves removed is smaller than a width of the grooves.

Abstract: The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer edge portions of a back surface of the sealing body, and plural wires for connecting pads formed on the semiconductor chip and the leads with each other. End portions of the suspending leads positioned in an outer periphery portion of the sealing body are not exposed to the back surface of the sealing body, but are covered with the sealing body. Therefore, stand-off portions of the suspending leads are not formed in resin molding.

Abstract: To avoid shorts between adjacent die pads in mounting a multi-die semiconductor package to a printed circuit board (PCB), one of the die pads is embedded in the polymer capsule, while the other die pad is exposed at the bottom of the package to provide a thermal escape path to the PCB. This arrangement is particularly useful when one of the dice in a multi-die package generates more heat than another die in the package.

Abstract: Thermal transfer from a silicon-on-insulator (SOI) die is improved by mounting the die in a bump-on-leadframe manner in a semiconductor package, with solder or other metal bumps connecting the active layer of the SOI die to metal leads used to mount the package on a printed circuit board or other support structure.

Abstract: A chip package includes: a substrate having a first and a second surface; a device region and a pad disposed on the first surface; a hole extending from the second surface to the pad; an insulating layer located on a sidewall of the hole; a carrier substrate located on the second surface; a first redistribution layer located between the carrier substrate and the insulating layer and located in the hole to electrically contact with the pad, wherein an edge of the first redistribution layer is exposed on a sidewall formed by the carrier substrate and the insulating layer; a second redistribution layer located on the carrier substrate, extending towards the second surface, and contacting the exposed edge of the first redistribution layer; and a buffer layer located on or below the second surface of the substrate and located between the second redistribution layer and the substrate.

Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a plurality of leads, a chip, and a package body. The die pad includes: (1) a peripheral edge region defining, a cavity with a cavity bottom including a central portion; (2) an upper sloped portion; and (3) a lower sloped portion. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the central portion of the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body.

Abstract: A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.

Abstract: A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.

Abstract: An exemplary implementation of the present disclosure includes a programmable interposer having top and bottom interface electrodes and conductive particles interspersed within the programmable interposer. The conductive particles are capable of forming an aligned configuration between the top and bottom interface electrodes in response to application of an energy field to the programmable interposer so as to electrically connect the top and bottom interface electrodes. The conductive particles can have a conductive outer surface. Also, the conductive particles can be spherical. The conductive particles can be within a bulk material in an interface layer in the programmable interposer, and the bulk material can be cured to secure programmed paths between the top and bottom interface electrodes.

Abstract: A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package.

Abstract: An integrated circuit package system includes: forming an external interconnect; forming a terminal having a cavity adjacent to and downset from a portion the external interconnect; connecting a first integrated circuit with the external interconnect; and forming an encapsulation over the first integrated circuit with cavity filled with the encapsulation, the terminal extending from the encapsulation, and the external interconnect partially exposed from the encapsulation.

Abstract: In a hybrid integrated circuit device, a circuit board on which an island portion of a lead is fixedly attached and a control board on which a control element and the like are mounted are disposed in an overlapping manner. The circuit board and the control board are integrally encapsulated with an encapsulating resin. A transistor disposed on an upper surface of the circuit board and a control element mounted on an upper surface of the control board are also covered by the encapsulating resin. Thus, a module in which an inverter circuit and a control circuit are integrally encapsulated with resin is provided.

Abstract: Some exemplary embodiments of a direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached to a top side of the paddle portion and is enclosed by said mold compound, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations.

Abstract: A semiconductor package structure includes: a dielectric layer; a metal layer disposed on the dielectric layer and having a die pad and traces, the traces each including a trace body, a bond pad extending to the periphery of the die pad, and an opposite trace end; metal pillars penetrating the dielectric layer with one ends thereof connecting to the die pad and the trace ends while the other ends thereof protruding from the dielectric layer; a semiconductor chip mounted on the die pad and electrically connected to the bond pads through bonding wires; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer, and the dielectric layer. The invention is characterized by disposing traces with bond pads close to the die pad to shorten bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging encountered in prior techniques.

Abstract: There is provided a lead frame and a packaging method. The lead frame comprises a first plurality of die pads, a second plurality of leads extending from the first plurality of die pads, and a third plurality of tie elements, each of which connects one of the first plurality of die pads to another.

Abstract: A lead frame or semiconductor device and a method of manufacturing the same in which where the unit lead frame of each semiconductor device after dicing was located in a lead frame before dicing can be known without an additional manufacturing step. The lead frame includes a plurality of unit lead frames each having a die pad, suspension leads coupled to the die pad, and leads formed around the die pad. An identification mark including at least one of a penetrating groove, recess, and convex is formed in at least one of the die pad, suspension leads, and leads. The identification mark of a first unit lead frame and the identification mark of a second unit lead frame are different from each other at least either in location in the unit lead frame or in shape.

Abstract: When a metal ribbon is ultrasonic-bonded, a peripheral area of an island and hanging pins provided in the periphery of the island need to be clamped by use of clampers of a bonder to prevent the island from being lifted up. However, if no sufficiently-wide peripheral area of the island can be secured or no hinging pins can be provided due to the miniaturization of the device, there arises a problem that the island cannot be clamped. A protrusion, which protrudes toward a lead and has the same height as an end portion of the lead, is provided to an edge of the island opposed to the lead. Accordingly, when the protrusion and the end portion of the lead are simultaneously pressed by the damper, it is possible to prevent the island from being lifted up even when no hanging pin or no clamp area around the island is provided.

Abstract: A lead frame substrate, including: a metal plate having a first surface and a second surface; a semiconductor element mount portion and a semiconductor element electrode connection terminal that are formed on the first surface; an external connection terminal formed on the second surface and electrically connected to the semiconductor element electrode connection terminal; a conducting wire that connects the semiconductor element electrode connection terminal and the external connection terminal to each other; a resin layer formed on the metal plate; a hole portion that is partly formed in the second surface of the metal plate and does not penetrate the metal plate; and a plurality of protrusions that are formed on a bottom surface of the hole portion and protrude in a direction away from the metal plate, the protrusions having a height lower than a position of the second surface, not being in electrical conduction with the conducting wire, and being dispersed separately.

Abstract: A method of packaging a power semiconductor die includes providing a first lead frame of a dual gauge lead frame. The first lead frame includes a thick die pad. A tape is attached to a first side of the thick die pad and the power die is attached to a second side of the thick die pad. A second lead frame of the dual gauge lead frame is provided. The second lead frame has thin lead fingers. One end of the lead fingers is attached to an active surface of the power die such that the lead fingers are electrically connected to bonding pads of the power die. A molding compound is then dispensed onto a top surface of the dual gauge lead frame such that the molding compound covers the power die and the lead fingers.

Abstract: An object of the present invention is to improve the quality control of a semiconductor device. By forming an inscription comprising a culled or pixel skipping pattern of dimples on the upper surface of a die pad in a QFN, it is possible to confirm the inscription by X-ray inspection or the like even after individuation and specify a cavity of a resin molding die. Further, it is possible to specify the position of a device region in a lead frame. As a result, when a defect appears, it is possible to sort a defective QFN by appearance inspection and improve quality control in the assembly of a QFN.

Abstract: Disclosed is a multi-chip memory package with a small substrate by using a die pad having an opening to substitute the chip-carrying function of a conventional substrate so that substrate dimension can be reduced. A substrate is attached under the die pad. A first chip is disposed on the substrate located inside the opening. A second chip is disposed on the die pad. An encapsulant encapsulates the top surface of the die pad, the top surface of the substrate, the first chip, and the second chip. The dimension of the substrate is smaller than the dimension of the encapsulant. In a preferred embodiment, a plurality of tie bars physically connect to the peripheries of the die pad and extend to the sidewalls of the encapsulant to have a plurality of insulated cut ends exposed from the encapsulant.

Abstract: A high temperature, non-cavity package for non-axial electronics is designed using a glass ceramic compound with that is capable of being assembled and operating continuously at temperatures greater that 300-400° C. Metal brazes, such as silver, silver colloid or copper, are used to connect the semiconductor die, lead frame and connectors. The components are also thermally matched such that the packages can be assembled and operating continuously at high temperatures and withstand extreme temperature variations without the bonds failing or the package cracking due to a thermal mismatch.

Abstract: A trench portion (trench) is formed at each of four corner portions of a chip bonding region having a quadrangular planar shape smaller than an outer-shape size of a die pad included in a semiconductor device. Each trench is formed along a direction of intersecting with a diagonal line which connects between the corner portions where the trench portions are arranged, and both ends of each trench portion are extended to an outside of the chip bonding region. The semiconductor chip is mounted on the chip bonding region so as to interpose a die-bond material. In this manner, peel-off of the die-bond material in a reflow step upon mounting of the semiconductor device on a mounting substrate can be suppressed. Also, even if the peel-off occurs, expansion of the peel-off can be suppressed.

Abstract: Described herein are semiconductor device packages and redistribution structures including alignment marks and manufacturing methods thereof.

Abstract: Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. The lead frame can include a plurality of terminals with stamped features at edges of the terminals. The stamped features can include flattened portions that are thinner than other portions of the terminals and extend laterally beyond the edges of the terminals. Such stamped features can help mechanically interlock the terminals with the plastic molding of the package body. The stamped features can include patterns and/or other features that may further increase interlocking between the terminals and the package body.

Abstract: A semiconductor device includes a leadframe with a die pad and a first lead, a semiconductor chip with a first electrode, and a contact clip with a first contact area and a second contact area. The semiconductor chip is placed over the die pad. The first contact area is placed over the first lead and the second contact area is placed over the first electrode of the semiconductor chip. A plurality of protrusions extends from each of the first and second contact areas and each of the protrusions has a height of at least 5 ?m.