Devices Being Of Two Or More Types, E.g., Forming Hybrid Circuits (epo) Patents (Class 257/E25.029)
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Publication number: 20110156247Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package comprises a substrate, a first metal layer, a first dielectric layer, a first upper electrode, a first protective layer, a second metal layer and a second protective layer. The substrate has at least one via structure. The first metal layer is disposed on a first surface of the substrate, and comprises a first lower electrode. The first dielectric layer is disposed on the first lower electrode. The first upper electrode is disposed on the first dielectric layer, and the first upper electrode, the first dielectric layer and the first lower electrode form a first capacitor. The first protective layer encapsulates the first capacitor. The second metal layer is disposed on the first protective layer, and comprises a first inductor. The second protective layer encapsulates the first inductor.Type: ApplicationFiled: June 23, 2010Publication date: June 30, 2011Inventors: Chien-Hua Chen, Teck-Chong Lee
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Patent number: 7964976Abstract: A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. The plurality of layer portions include at least one layer portion of a first type and at least one layer portion of a second type. The layer portions of the first and second types each include a semiconductor chip. The layer portion of the first type further includes a plurality of electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the layer portion of the second type does not include any electrode connected to the semiconductor chip and having an end face located at the side surface of the main body on which the wiring is disposed. The wiring is connected to the end face of each of the plurality of electrodes.Type: GrantFiled: August 20, 2008Date of Patent: June 21, 2011Assignees: Headway Technologies, Inc., TDK Corporation, SAE Magnetics (H.K.) Ltd.Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Tatsuya Harada, Nobuyuki Okuzawa, Satoru Sueki, Hiroshi Ikejima
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Publication number: 20110089553Abstract: Provided are a stack-type solid-state drive (SSD) capable of reducing a size thereof by mounting semiconductor chips in a recess region formed in a substrate, and a method of fabricating the stack-type SSD. The stack-type SSD includes a substrate including one or more recess regions; one or more passive electronic elements mounted in the one or more recess regions; one or more control semiconductor chips mounted in the one or more recess regions; one or more non-volatile memory semiconductor chips mounted on a first surface of the substrate so as to overlap the one or more passive electronic elements, the one or more control semiconductor chips, or all the passive electronic elements and the control semiconductor chips; and an external connection terminal located on a side of the substrate.Type: ApplicationFiled: December 15, 2009Publication date: April 21, 2011Applicant: STS SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD.Inventors: Tae Hyun KIM, Gyu Han KIM
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Publication number: 20110084380Abstract: A semiconductor package onto which a plurality of passive elements is mounted. A substrate includes a first surface and a second surface. A semiconductor chip is on one of the first surface and the second surface of the substrate. A plurality of passive elements are on the substrate. The plurality of passive elements include a plurality of first passive elements and a plurality of second passive elements that are taller than the plurality of first passive elements. The plurality of first passive elements are on at least one of the first surface and the second surface, and at least two of the plurality of second passive elements are on the second surface.Type: ApplicationFiled: October 14, 2010Publication date: April 14, 2011Inventors: Heung-kyu Kwon, Hyung-Jun Lim, Byeong-yeon Cho
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Patent number: 7915707Abstract: An integrated-circuit device includes a rigid substrate island having a main substrate surface with a circuit region circuit elements and at least one fold structure. The fold structure is attached to the substrate island and is unfoldable from a relaxed, folded state to a strained unfolded state. The fold structure contains at least one passive electrical component. The fold structure further has in its folded state at least one surface with an area vector that includes a non-vanishing area-vector component in a direction parallel to the main substrate surface, which area-vector component is diminished or vanishes when deforming the fold structure from the folded into the unfolded state.Type: GrantFiled: August 7, 2007Date of Patent: March 29, 2011Assignee: Koninklijke Philips Electronics N.V.Inventors: Ronald Dekker, Antoon Marie Henrie Tombeur, Theodoros Zoumpoulidis
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Publication number: 20110068433Abstract: Method of forming a radio frequency integrated circuit (RFIC) is provided. The RFIC comprises one or more electronic devices formed in a semiconductor substrate and one or more passive devices on a dielectric substrate, arranged in a stacking manner. Electrical shield structure is formed in between to shield electronic devices in the semiconductor substrate from the passive devices in the dielectric substrate. Vertical through-silicon-vias (TSVs) are formed to provide electrical connections between the passive devices in the dielectric substrate and the electronic devices in the semiconductor substrate.Type: ApplicationFiled: September 24, 2009Publication date: March 24, 2011Applicant: QUALCOMM IncorporatedInventors: Jonghae Kim, Brian M. Henderson, Matthew M. Nowak, Jiayu Xu
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Patent number: 7897477Abstract: Provided is a method of fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a back side, forming a first circuit and a second circuit at the front side of the semiconductor substrate, bonding the front side of the semiconductor substrate to a carrier substrate, thinning the semiconductor substrate from the back side, and forming an trench from the back side to the front side of the semiconductor substrate to isolate the first circuit from the second circuit.Type: GrantFiled: January 21, 2009Date of Patent: March 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Chun Wang, Tzu-Hsuan Hsu
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Patent number: 7892948Abstract: The present invention provides a method for manufacturing an SOI wafer in which a thickness of an SOI layer is increased by growing an epitaxial layer on the SOI layer of the SOI wafer having an oxide film and the SOI layer formed on a base wafer, wherein the epitaxial growth is performed in such a manner that a reflectivity of a surface of the SOI wafer on which the epitaxial layer is grown in a wavelength region of a heating light at the start of the epitaxial growth falls within the range of 30% to 80%. As a result, in the method for manufacturing the SOI wafer in which a thickness of the SOI layer is increased by growing the epitaxial layer on the SOI layer of the SOI wafer having the oxide film and the SOI layer formed on the base wafer, a method for manufacturing a high-quality SOI wafer with less slip dislocation and others is provided.Type: GrantFiled: January 15, 2007Date of Patent: February 22, 2011Assignee: Shin-Etsu Handotai Co., Ltd.Inventor: Shinichiro Yagi
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Patent number: 7888709Abstract: The integrated circuit/transducer device of the preferred embodiment includes a substrate, a complementary-metal-oxide-semiconductor (CMOS) circuit that is fabricated on the substrate, and a capacitive micromachined ultrasonic transducer (cMUT) element that is also fabricated on the substrate. The CMOS circuit and cMUT element are fabricated during the same foundry process and are connected. The cMUT includes a lower electrode, an upper electrode, a membrane structure that support the upper electrode, and a cavity between the upper electrode and lower electrode.Type: GrantFiled: April 8, 2009Date of Patent: February 15, 2011Assignee: Sonetics Ultrasound, Inc.Inventors: David F. Lemmerhirt, Collin A. Rich
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Patent number: 7875953Abstract: An integrated circuit laminate with a metal substrate for use with high performance mixed signal integrated circuit applications. The metal substrate provides substantially improved crosstalk isolation, enhanced heat sinking and an easy access to a true low impedance ground. In one embodiment, the metal layer has regions with insulation filled channels or voids and a layer of insulator such as unoxidized porous silicon disposed between the metal substrate and a silicon integrated circuit layer. The laminate also has a plurality of metal walls or trenches mounted to the metal substrate and transacting the silicon and insulation layers thereby isolating noise sensitive elements from noise producing elements on the chip. In another embodiment, the laminate is mounted to a flexible base to limit the flexion of the chip.Type: GrantFiled: July 7, 2008Date of Patent: January 25, 2011Assignee: The Regents of the University of CaliforniaInventor: Ya-Hong Xie
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Publication number: 20110012253Abstract: A semiconductor package includes a substrate having contacts, and a discrete component on the substrate in electrical communication with the contacts. The package also includes a semiconductor die on the substrate in electrical communication with the contacts, and a die attach polymer attaching the die to the substrate. The die includes a recess, and the discrete component is contained in the recess encapsulated in the die attach polymer. A method for fabricating the package includes the steps of: attaching the discrete component to the substrate, placing the die attach polymer on the discrete component and the substrate, pressing the die into the die attach polymer to encapsulate the discrete component in the recess and attach the die to the substrate, and then placing the die in electrical communication with the discrete component. An electronic system includes the semiconductor package mounted to a system substrate.Type: ApplicationFiled: August 26, 2010Publication date: January 20, 2011Inventors: Chua Swee Kwang, Chia Yong Poo
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Patent number: 7868439Abstract: A chip package coupled to a circuit board includes a substrate and at least one chip. The substrate includes a plurality of first pads, a plurality of second pads and at least one first interconnecting structure. The first pads and the chip are located on a first surface of the substrate and the second pads are located on a second surface of the substrate. The first interconnecting structure is coupled with the chip, one of the first pads and one of the second pads for flexible design of various applications. A substrate of the chip package is also disclosed.Type: GrantFiled: August 23, 2006Date of Patent: January 11, 2011Assignee: Via Technologies, Inc.Inventors: Wen Yuan Chang, Chih-An Yang
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Patent number: 7829971Abstract: A semiconductor apparatus is disclosed. The semiconductor apparatus includes an SOI substrate including an active layer, a buried insulation film and a support substrate; a low potential reference circuit part located in the active layer and operable at a first reference potential; a high potential reference circuit part located in the active layer and operable at a second reference potential; a level-shifting element forming part located in the active layer and for providing a level-shift between the first and second reference potentials; and an insulation member insulating first and second portions of the support substrate from each other, wherein locations of the first and second portions respectively correspond to the low and high potential reference circuit parts.Type: GrantFiled: December 11, 2008Date of Patent: November 9, 2010Assignee: DENSO CORPORATIONInventors: Hiroki Sone, Akira Yamada, Satoshi Shiraki, Nozomu Akagi
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Patent number: 7821124Abstract: Semiconductor die packages and methods of making them are disclosed. An exemplary package comprises a leadframe having a source lead and a gate lead, and a semiconductor die coupled to the source and gate leads at a first surface of the leadframe. The source lead has a protruding region at a second surface of the leadframe. A molding material is disposed around the semiconductor die, the gate lead, and the source lead such that a surface of the die and a surface of the protruding region are left exposed by the molding material. An exemplary method comprises obtaining the semiconductor die and leadframe, and forming a molding material around at least a portion of the leadframe and die such that a surface of the protruding region is exposed through the molding material.Type: GrantFiled: December 20, 2007Date of Patent: October 26, 2010Assignee: Fairchild Semiconductor CorporationInventors: Rajeev Joshi, Chung-Lin Wu
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Publication number: 20100258901Abstract: A semiconductor device includes: a semiconductor substrate including an active element formation face on which an active element is formed; detection electrodes detecting a remaining amount of ink by being wet in the ink; an antenna transmitting and receiving information; a storage circuit storing information relating to the ink; and a control circuit controlling the detection electrodes, the antenna, and the storage circuit.Type: ApplicationFiled: June 28, 2010Publication date: October 14, 2010Applicant: SEIKO EPSON CORPORATIONInventor: Nobuaki HASHIMOTO
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Publication number: 20100244227Abstract: Provided are semiconductor packages and electronic systems including the same. A first memory chip may be stacked on a first portion of a substrate. A controller chip may be stacked on a second portion of the substrate, which is different from the first portion. At least one first bonding wire may directly connect the first memory chip with the controller chip. At least one second bonding wire may directly connect the first memory chip with the substrate, and may be electrically connected with the at least one first bonding wire.Type: ApplicationFiled: January 15, 2010Publication date: September 30, 2010Inventors: Kyung-man Kim, In-ku Kang, Ji-hyun Lee
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Publication number: 20100248399Abstract: A method for wafer-to-wafer bonding of a sensor readout circuitry separately fabricated with a silicon substrate to a photodiode device made of non-silicon materials grown from a separate substrate. In preferred embodiments the non-silicon materials are epitaxially grown on a silicon wafer. The bonding technique of preferred embodiments of the present invention utilizes lithographically pre-fabricated metallic interconnects to connect each of a number of pixel circuits on a readout circuit wafer to each of a corresponding number of pixel photodiodes on a photodiode wafer. The metallic interconnects are extremely small (with widths of about 2 to 4 microns) compared to prior art bump bonds with the solder balls of diameter typically larger than 20 microns. The present invention also provides alignment techniques to assure proper alignment of the interconnects during the bonding step.Type: ApplicationFiled: March 25, 2009Publication date: September 30, 2010Inventor: Tzu-Chiang Hsieh
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Patent number: 7804171Abstract: A technique for packaging multiple devices to form a multi-chip module. Specifically, a multi-chip package is coupled to an interposer to form the multi-chip module. The multi-chip package includes a plurality of integrated circuit chips coupled to a carrier. The chips are encapsulated such that conductive elements are exposed through the encapsulant. The conductive elements are electrically coupled to the chips. The interposer is configured such that vias are aligned with the conductive elements. Conductive material may be disposed into the vias to provide signal paths from the integrated circuit chips to conductive balls disposed on the backside of the interposer.Type: GrantFiled: August 27, 2004Date of Patent: September 28, 2010Assignee: Micron Technology, Inc.Inventors: Todd O. Bolken, Chad A. Cobbley
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Publication number: 20100230806Abstract: A semiconductor device is made by forming a plurality of conductive pillars vertically over a temporary carrier. A conformal insulating layer is formed over the conductive pillars. A conformal conductive layer is formed over the conformal insulating layer. A first conductive pillar, conformal insulating layer, and conformal conductive layer constitute a vertically oriented integrated capacitor. A semiconductor die or component is mounted over the carrier. An encapsulant is deposited over the semiconductor die or component and around the conformal conductive layer. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure includes an integrated passive device. The first interconnect structure is electrically connected to the semiconductor die or component and vertically oriented integrated capacitor. The carrier is removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first side of the encapsulant.Type: ApplicationFiled: March 13, 2009Publication date: September 16, 2010Applicant: STATS ChipPAC, Ltd.Inventors: Rui Huang, Heap Hoe Kuan, Yaojian Lin, Seng Guan Chow
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Patent number: 7795728Abstract: An electronic component includes a multi-layer substrate having an upper side and under side, and at least one integrated impedance converter. The electronic component also includes at least one chip component having external contacts. The at least one chip component is disposed on the upper side of the multi-layer substrate, and is electrically connected to the at least one integrated impedance converter.Type: GrantFiled: May 7, 2003Date of Patent: September 14, 2010Assignee: Epcos AGInventor: Andreas Przadka
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Patent number: 7763974Abstract: An integrated circuit for driving a semiconductor device, which is adaptable for demands, such as a higher output (larger current), a higher voltage, and a smaller loss, and has a small size, is produced at a low cost, and has high reliability. A power converter including such an integrated circuit is also provided. Circuit elements constituting a drive section of an upper arm drive circuit 212, a level shift circuit 20 including a current sensing circuit 210, a drive section of a lower arm drive circuit 222, and a drive signal processing circuit 224 are integrated and built in one high withstand voltage IC chip 200. Circuit elements constituting a final output stage buffer section 213 of the upper arm drive circuit 212 are built in a vertical p-channel MOS-FET chip 213p and a vertical n-channel MOS-FET chip 213n.Type: GrantFiled: February 13, 2004Date of Patent: July 27, 2010Assignee: Hitachi, Ltd.Inventors: Yoshimasa Takahashi, Naoki Sakurai, Masashi Yura, Masahiro Iwamura, Mutsuhiro Mori
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Publication number: 20100181638Abstract: Provided is a method of fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a back side, forming a first circuit and a second circuit at the front side of the semiconductor substrate, bonding the front side of the semiconductor substrate to a carrier substrate, thinning the semiconductor substrate from the back side, and forming an trench from the back side to the front side of the semiconductor substrate to isolate the first circuit from the second circuit.Type: ApplicationFiled: January 21, 2009Publication date: July 22, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Chun Wang, Tzu-Hsuan Hsu
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Publication number: 20100164094Abstract: Provided is a multi-chip package memory device. The multi-chip package memory device may include a transmission memory chip and a plurality of memory chips that are stacked on the transmission memory chip. The transmission memory chip may include a temporary storage unit, and may transmit a received command or received data to a corresponding memory chip, or to an external element. Each of the memory chips may include a memory core, and may delay the received command according to the properties of the memory chips and then may output delay commands. The transmission memory chip may store the received data in different portions of the temporary storage unit when the delay commands are respectively received.Type: ApplicationFiled: November 16, 2009Publication date: July 1, 2010Inventor: Hoe-Ju Chung
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Publication number: 20100164124Abstract: A method and apparatus are provided for multi-chip packaging. A multi-chip package (100) includes a substrate (105) and a plurality of semiconductor dice (110, 120, 130). A first semiconductor die (110) is physically coupled to an upper face of the substrate (105), the first semiconductor die (110) being a smallest one of the plurality of semiconductor dice (110, 120, 130).Type: ApplicationFiled: March 9, 2010Publication date: July 1, 2010Inventors: Yong DU, John YAN
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Publication number: 20100140810Abstract: A chip package includes a substrate, an integrated circuit proximate a top surface of the substrate, and a cap comprising encapsulant that encapsulates the integrated circuit on at least a portion of the top surface of the substrate. The chip package further includes at least one extension feature positioned on at least a portion of the top surface of the substrate. The at least one extension feature also comprises the encapsulant and extends from the cap to a perimeter of the substrate.Type: ApplicationFiled: December 8, 2008Publication date: June 10, 2010Applicant: STMicroelectronics Asia Pacific PTE Ltd.Inventor: Jing-en Luan
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Publication number: 20100127383Abstract: In the power semiconductor module, a wiring metal plate electrically connects between power semiconductor elements joined to the circuit pattern, and between the power semiconductor elements and the circuit pattern. Cylindrical main terminals are joined, substantially perpendicularly, to the wiring metal plate and the circuit pattern, respectively. A cylindrical control terminal is joined, substantially perpendicularly, to one of the power semiconductor elements.Type: ApplicationFiled: October 20, 2009Publication date: May 27, 2010Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Seiji OKA, Yoshiko Obiraki, Takeshi Oi
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Publication number: 20100127407Abstract: A two-sided substrateless multichip module including at least one die layer having at least one die. At least one bottomside interconnect layer is coupled to a bottom surface of the at least one die. At least one topside interconnect layer is coupled to a top surface of the at least one die. One or more embedded electrical connections is configured to provide an electrical interconnection between the at least one bottomside interconnect layer and the at least one die and/or the at least bottomside interconnect layer and the at least one topside interconnect layer and/or the at least one topside interconnect layer and the at least one die, wherein the at least one bottomside interconnect layer includes one or more electrical contacts on a bottom surface of the multichip module and the at least topside interconnect layer includes one or more electrical contacts on a top surface of the multichip module.Type: ApplicationFiled: November 25, 2008Publication date: May 27, 2010Inventors: John LeBlanc, Brad Gaynor, David Hagerstrom, Caroline Bjune
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Publication number: 20100102434Abstract: Provided are a semiconductor memory device and a method of driving the device which can improve a noise characteristic of a voltage signal supplied to a memory cell of the device. The semiconductor memory device includes a first semiconductor chip and one or more second semiconductor chips stacked on the first chip. The first chip includes an input/output circuit for sending/receiving a voltage signal, a data signal, and a control signal to/from an outside system. The one or more second semiconductor chips each include a memory cell region for storing data. The second semiconductor chips receive at least one signal through one or more signal paths that are formed outside the input/output circuit of the first chip.Type: ApplicationFiled: January 6, 2010Publication date: April 29, 2010Inventors: Sun-Won Kang, Seung-Duk Baek
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Publication number: 20100102440Abstract: A semiconductor package is disclosed including a plurality semiconductor die mounted on stacked and bonded layers of substrate, for example polyimide tape used in tape automated bonding processes. The tape may have a plurality of repeating patterns of traces and contact pads formed thereon. The traces each include aligned interconnect pads on the respective top and bottom surfaces of the substrate for bonding the traces of one pattern to the traces of another pattern after the patterns have been singulated from the substrate, aligned and stacked. Semiconductor die such as flash memory and a controller die are mounted on the traces of the respective patterns on the substrate. In order for the controller die to uniquely address a specific flash memory die in the stack, a group of traces on each substrate supporting the memory die are used as address pins and punched in a unique layout relative to the layout of the traces other substrates.Type: ApplicationFiled: December 29, 2009Publication date: April 29, 2010Inventors: Cheemen Yu, Chih-Chin Liao, Hem Takiar
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Publication number: 20100096629Abstract: The invention provides a multi-chip module. In one embodiment, the multi-chip module comprises a serial flash die and a primary die, and the primary die comprises a built-in self-test controller and a serial flash controller. The built-in self-test controller generates a write command to write first data to a memory location of the serial flash die, generates a read command to read second data from the memory location of the serial flash die, and compares the second data with the first data to determine whether the memory location is defective for generating failed address information about the serial flash die. The serial flash controller accesses the serial flash die according to the write command and the read command.Type: ApplicationFiled: October 20, 2008Publication date: April 22, 2010Applicant: MEDIATEK INC.Inventor: Yeow Chyi CHEN
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Publication number: 20100090325Abstract: In order to solve a problem of increased noise accompanying increased area of a return path in a stacked package structure, provided is a semiconductor device which is formed in a stacked package such as a PoP package, which realizes low noise without changing a package size. An additional power supply wiring that runs along a signal wiring between an upper PoP and a lower PoP is newly added in the lower PoP of a package having a PoP structure.Type: ApplicationFiled: October 9, 2009Publication date: April 15, 2010Applicant: ELPIDA MEMORY, INC.Inventors: Yutaka UEMATSU, Yukitoshi HIROSE
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Patent number: 7696615Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor chip included in the semiconductor device includes a pillar-shaped terminal and a pad-shaped terminal in a terminal region. The pillar-shaped terminal is exposed at a first surface of a chip substrate in the terminal region and the pad-shaped terminal is exposed at a second surface of the chip substrate in the terminal region, where the first surface and the second surface of the chip substrate in the terminal region face oppositely from each other.Type: GrantFiled: July 11, 2007Date of Patent: April 13, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Young Ko, Dae-Sang Chan, Wha-Su Sin
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Publication number: 20100078787Abstract: To provide a semiconductor device whose reliability is improved by increase in resistance to external stress and electrostatic discharge with reduction in thickness and size achieved. An IC chip provided with an integrated circuit and a resonant capacitor portion, an antenna provided over the IC chip, and a conductive blocking body provided so as to at least partially overlap the antenna with an insulating film interposed therebetween are included. A capacitor is formed with a layered structure of the antenna, the insulating film over the antenna, and the conductive blocking body over the insulating film.Type: ApplicationFiled: September 28, 2009Publication date: April 1, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Yuto YAKUBO
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Publication number: 20100078790Abstract: In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction.Type: ApplicationFiled: May 14, 2009Publication date: April 1, 2010Inventors: Kiyoto ITO, Makoto Saen, Yuki Kuroda
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Publication number: 20100078635Abstract: As the transfer between a processor LSI and a memory has been increasing year by year, there is a demand for increasing the traffic amount and reducing the power required for communication. With this being the condition, a method of stacking LSIs thereby reducing the communication distance is being contemplated. However, the inventors have found that the reduction of cost in the stacking process and the increase in the degree of freedom of selecting the memory LSI to be stacked are required for a simple stacking of processor LSIs and memory LSIs as so far practiced. An external communication LSI including a circuit for performing the communication with the outside of the stacked LSI at a high rate of more than 1 GHz; a processor LSI including a general purpose CPU etc.; and a memory LSI including a DRAM etc. are stacked in this order and those LSIs are connected with one another with a through silicon via to enable a high speed and high volume communication at a shortest path.Type: ApplicationFiled: May 14, 2009Publication date: April 1, 2010Inventors: Yuki Kuroda, Makoto Saen, Hiroyuki Mizuno, Kiyoto Ito
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Patent number: 7687896Abstract: A semiconductor device formed by mutually connecting a first semiconductor chip with second and third semiconductor chips arranged side by side, with the active surface of the first chip faced to those of the second and third chip. Both the second and third semiconductor chips have functional elements on their active surface. The first semiconductor chip has, in its active surface, a wiring for connecting the second semiconductor chip and the third semiconductor chip, and a terminal for external connection on its surface opposite to its active surface.Type: GrantFiled: June 13, 2006Date of Patent: March 30, 2010Assignee: Rohm Co. Ltd.Inventor: Kazutaka Shibata
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Patent number: 7687885Abstract: The present invention provides a technology for reducing the parasitic inductance of the main circuit of a power source unit. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETS, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad.Type: GrantFiled: May 30, 2007Date of Patent: March 30, 2010Assignee: Renesas Technology Corp.Inventors: Takayuki Hashimoto, Noboru Akiyama, Masaki Shiraishi, Tetsuya Kawashima
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Publication number: 20100072604Abstract: To provide a technique of supplying a voltage generated in any of a plurality of semiconductor chips to the other chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. In an example of the main technique, two chips are stacked with each other, first to third pads are disposed along corresponding sides of the respective chips, which are arranged close and in parallel to each other, and these pads are commonly connected to each other with first to third metal wires, respectively. In another example, fourth and fifth pads are disposed along a side different from a side along which the first to third pads are disposed, and further connected to each other with a fourth metal wire directly between the chips.Type: ApplicationFiled: June 23, 2009Publication date: March 25, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Mikihiko KOMATSU, Takao HIDAKA, Junko KIMURA
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Publication number: 20100059748Abstract: Application form of and demand for an IC chip formed with a silicon wafer are expected to increase, and further reduction in cost is required. An object of the invention is to provide a structure of an IC chip and a process capable of producing at a lower cost. In view of the above described object, one feature of the invention is to provide the steps of forming a separation layer over an insulating substrate and forming a thin film integrated circuit having a semiconductor film as an active region over the separation layer, wherein the thin film integrated circuit is not separated. There is less limitation on the shape of a mother substrate in the case of using the insulating substrate, when compared with the case of taking a chip out of a circular silicon wafer. Accordingly, reduction in cost of an IC chip can be achieved.Type: ApplicationFiled: November 6, 2009Publication date: March 11, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Koji DAIRIKI
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Patent number: 7670862Abstract: A method of manufacturing a silicon optoelectronic device, a silicon optoelectronic device manufactured by the method, and an image input and/or output apparatus having the silicon optoelectronic device are provided. The method includes: preparing an n-type or p-type silicon-based substrate; forming a polysilicon in one or more regions of the surface of the substrate; oxidizing the surface of the substrate where the polysilicon is formed, to form a silicon oxidation layer on the substrate, and forming a microdefect flection pattern at the interface between the substrate and the silicon oxidation layer, wherein the microdefect flection pattern is formed by the oxidation accelerated by oxygen traveling through boundaries of the grains in the polysilicon; exposing the microdefect flection pattern by etching the silicon oxidation layer; and forming a doping region by doping the exposed microdefect flection pattern with a dopant of the opposite type to the substrate.Type: GrantFiled: November 22, 2005Date of Patent: March 2, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: In-jae Song, Byoung-Iyong Choi
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Patent number: 7663247Abstract: A semiconductor integrated circuit device includes a semiconductor chip, a memory cell array arranged on the semiconductor chip and first and second decoder strings arranged along both ends of the memory cell array. The arrangement position of the first decoder string is deviated from the arrangement position of the second decoder string and a space caused by the deviation is arranged in the corner of the semiconductor chip.Type: GrantFiled: July 11, 2008Date of Patent: February 16, 2010Assignee: Kabuhsiki Kaisha ToshibaInventor: Takahiko Hara
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Publication number: 20100032828Abstract: One or more electronic components can be mounted on the back side of a semiconductor die. The components can be passive components, active components, or combinations thereof. The components can be soldered to signal routes on the back side of the die, the signal routes being attached to the die using a metallization layer or using one or more dielectric layer sections. Placing components on the back side of the die can allow for incorporation of the components without necessarily increasing the form factor of the die's package.Type: ApplicationFiled: October 12, 2009Publication date: February 11, 2010Inventors: Seng Guan Chow, Francis Heap Hoe Kuan
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Publication number: 20100019391Abstract: This application relates to a semiconductor device comprising a first chip comprising a first electrode on a first face of the first chip, and a second chip attached to the first electrode, wherein the second chip comprises a transformer comprising a first winding and a second winding.Type: ApplicationFiled: July 22, 2008Publication date: January 28, 2010Applicant: INFINEON TECHNOLOGIES AGInventor: Bernhard Strzalkowski
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Publication number: 20090321921Abstract: Provided are an embedded wiring board and a method of manufacturing the same. The embedded wiring board includes: a printed circuit board (PCB) including a first surface and a second surface, the first surface having a concave portion; through electrodes penetrating the PCB; a semiconductor device group embedded in the concave portion of the PCB, the semiconductor device group including bonding pads exposed in a direction of the first surface of the PCB; bumps disposed on the bonding pads, exposed in the direction of the first surface of the PCB; and a film substrate including a first surface and a second surface, the first surface including connection electrode patterns that are electrically connected to the bumps and the through electrodes, the film substrate having penetrated openings.Type: ApplicationFiled: June 30, 2009Publication date: December 31, 2009Inventor: TAEJOO HWANG
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Publication number: 20090278212Abstract: An integrated device including a sensor and the like formed on a ?-alumina layer epitaxially grown on a silicon substrate is provided at low cost. This integrated device includes: a silicon substrate; a first function area formed on a ?-alumina film epitaxially grown on a portion of the silicon substrate; a second function area formed on an area of the silicon substrate other than an area where the ?-alumina film is grown; and wiring means for connecting the first function area with the second function area.Type: ApplicationFiled: June 2, 2006Publication date: November 12, 2009Inventors: Makoto Ishida, Kazuaki Sawada, Daisuke Akai, Keisuke Hirabayashi
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Publication number: 20090273099Abstract: On a semiconductor chip in a semiconductor integrated circuit, a plurality of circuit cells each of which has a pad are formed along a first chip side of the semiconductor chip. Among the plurality of circuit cells, one or more circuit cells at least in the vicinity of an end portion on the first chip side are arranged having a steplike shift in a direction apart from the first chip side with decreasing distance from the center portion to the end portion on the first chip side.Type: ApplicationFiled: September 29, 2006Publication date: November 5, 2009Inventors: Hiroki Matsunaga, Akihiro Maejima, Jinsaku Kaneda, Hiroshi Ando, Eisaku Maeda
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Publication number: 20090261447Abstract: Signal lines (13) and (14) to be used for supplying a signal between an analog circuit and a digital circuit are provided in different regions from power-ground lines (11) and (12) to be used for supplying a power to the analog circuit and the digital circuit in such a manner that the signal lines (13) and (14) do not cross the power-ground lines (11) and (12). For example, the power-ground lines (11) and (12) are provided along an outer periphery of a semiconductor chip (10) and the analog circuit and the digital circuit are disposed on the inside of the power-ground lines (11) and (12), and the signal lines (13) and (14) are provided between the analog circuit and the digital circuit.Type: ApplicationFiled: February 25, 2009Publication date: October 22, 2009Applicant: NSC CO., LTD.Inventors: Takeshi Ikeda, Hiroshi Miyagi
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Publication number: 20090250729Abstract: The integrated circuit/transducer device of the preferred embodiment includes a substrate, a complementary-metal-oxide-semiconductor (CMOS) circuit that is fabricated on the substrate, and a capacitive micromachined ultrasonic transducer (cMUT) element that is also fabricated on the substrate. The CMOS circuit and cMUT element are fabricated during the same foundry process and are connected. The cMUT includes a lower electrode, an upper electrode, a membrane structure that support the upper electrode, and a cavity between the upper electrode and lower electrode.Type: ApplicationFiled: April 8, 2009Publication date: October 8, 2009Inventors: David F. Lemmerhirt, Collin A. Rich
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Publication number: 20090244860Abstract: A mounting structure comprises at least one semiconductor device having solder bumps on a lower surface thereof as outer terminals and a flexible wiring board with wiring formed thereon. The semiconductor device is wrapped in a flexible wiring board; the mounting structure is provided with outer electrodes on both of a side on which the outer terminals of the semiconductor device are formed and an opposite side thereto; at least one wiring layer is formed on the flexible wiring board; and a supporting member is affixed between a lower surface of the semiconductor device on which the outer terminals are formed and the flexible wiring board.Type: ApplicationFiled: March 26, 2009Publication date: October 1, 2009Applicant: NEC CORPORATIONInventors: Shinji Watanabe, Takao Yamazaki
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Publication number: 20090230486Abstract: A piezoelectric device includes an integrated circuit (IC) chip and a piezoelectric resonator element, a part of the piezoelectric resonator element being disposed so as to overlap with a part of the IC chip when viewed in plan. The IC chip includes: an inner pad disposed on an active face and in an area where is overlapped with the piezoelectric resonator when viewed in plan; an insulating layer formed on the active face; a relocation pad disposed on the insulating layer and in an area other than a part where is overlapped with the piezoelectric resonator element, the relocation pad being coupled to an end part of a first wire; and a second wire electrically coupling the inner pad and the relocation pad, the second wire having a relocation wire and a connector that penetrates the insulating layer, the relocation wire being disposed between the insulating layer and the active face.Type: ApplicationFiled: March 16, 2009Publication date: September 17, 2009Applicant: EPSON TOYOCOM CORPORATIONInventor: Kazuhiko SHIMODAIRA