Static Random Access Memory, Sram, Structure (epo) Patents (Class 257/E27.098)
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Patent number: 8294186Abstract: A semiconductor device capable of improving the driving power and a manufacturing method therefor are provided. In a semiconductor device, a gate structure formed by successively stacking a gate oxide film and a silicon layer is arranged over a semiconductor substrate. An oxide film is arranged long the lateral side of the gate structure and another oxide film is arranged along the lateral side of the oxide film and the upper surface of the substrate. In the side wall oxide film comprising these oxide films, the minimum value of the thickness of the first layer along the lateral side of the gate structure is less than the thickness of the second layer along the upper surface of the substrate.Type: GrantFiled: June 7, 2011Date of Patent: October 23, 2012Assignee: Renesas Electronics CorporationInventors: Toshifumi Iwasaki, Yoshihiko Kusakabe
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Publication number: 20120261768Abstract: A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a substrate having a first concentration of a first conductivity type (P-well). A gate region (500) having a length and a width is formed on the dielectric region. Source (512) and drain (504) regions having a second conductivity type (N+) are formed in the substrate on opposite sides of the gate region. A first impurity region (508) having the first conductivity type (P+) is formed adjacent the source. The first impurity region has a second concentration greater than the first concentration.Type: ApplicationFiled: May 23, 2012Publication date: October 18, 2012
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Patent number: 8278167Abstract: Methods for fabricating integrated circuits include fabricating a logic device on a substrate, forming an intermediate semiconductor substrate on a surface of the logic device, and fabricating a capacitor-less memory cell on the intermediate semiconductor substrate. Integrated circuits with capacitor-less memory cells formed on a surface of a logic device are also disclosed, as are multi-core microprocessors including such integrated circuits.Type: GrantFiled: December 18, 2008Date of Patent: October 2, 2012Assignee: Micron Technology, Inc.Inventor: Gurtej S. Sandhu
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Publication number: 20120235240Abstract: Dual orientation of finFET transistors in a static random access memory (SRAM) cell allows aggressive scaling to a minimum feature size of 15 nm and smaller using currently known masking techniques that provide good manufacturing yield. A preferred layout and embodiment features inverters formed from adjacent, parallel finFETs with a shared gate and different conductivity types developed through a double sidewall image transfer process while the preferred dimensions of the inverter finFETs and the pass transistors allow critical dimensions of all transistors to be sufficiently uniform despite the dual transistor orientation of the SRAM cell layout.Type: ApplicationFiled: March 15, 2011Publication date: September 20, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Abhisek Dixit
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Publication number: 20120228714Abstract: An SRAM cell includes a first PMOS pass transistor comprising a first gate electrode disposed on a first PMOS active region, a first NMOS pass transistor comprising a second gate electrode disposed on a first NMOS active region, a first PMOS pull-up transistor and a first NMOS pull-down transistor sharing a third gate electrode disposed on the first PMOS active region and the first NMOS active region and extending therebetween, a second PMOS pass transistor comprising a fourth gate electrode disposed on a second PMOS active region, a second NMOS pass transistor comprising a fifth gate electrode disposed on a second NMOS active region and a second pull-up transistor and a second pull-down transistor sharing a sixth gate electrode disposed on the second PMOS active region and the second NMOS active region and extending therebetween.Type: ApplicationFiled: March 5, 2012Publication date: September 13, 2012Inventors: Sunme Lim, Hanbyung Park, Ho-Kwon Cha
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Publication number: 20120193724Abstract: A static RAM cell may be formed on the basis of two double channel transistors and a select transistor, wherein a body contact may be positioned laterally between the two double channel transistors in the form of a dummy gate electrode structure, while a further rectangular contact may connect the gate electrodes, the source regions and the body contact, thereby establishing a conductive path to the body regions of the transistors. Hence, compared to conventional body contacts, a very space-efficient configuration may be established so that bit density in static RAM cells may be significantly increased.Type: ApplicationFiled: April 11, 2012Publication date: August 2, 2012Inventor: Frank Wirbeleit
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Patent number: 8217427Abstract: A memory circuit includes a plurality of bit line structures, a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells is selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures, and each of the cells in turn includes a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor. The at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of the bit line structures, and the at least first p-type field effect transistor is formed with a relatively thin buried oxide layer.Type: GrantFiled: October 2, 2007Date of Patent: July 10, 2012Assignee: International Business Machines CorporationInventors: Ching-Te K. Chuang, Fadi H. Gebara, Keunwoo Kim, Jente Benedict Kuang, Hung C. Ngo
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Patent number: 8212322Abstract: Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.Type: GrantFiled: March 9, 2010Date of Patent: July 3, 2012Assignee: International Business Machines CorporationInventors: Martin M. Frank, Arvind Kumar, Vijay Narayanan, Vamsi K. Paruchuri, Jeffrey Sleight
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Patent number: 8207579Abstract: A semiconductor device where a plurality of DMOS transistors formed in a distributed manner on a semiconductor substrate can operate without being destroyed and a method of manufacturing the same. The on/off threshold voltage of a DMOS transistor at the innermost position from among three or more DMOS transistors formed in a distributed manner on a semiconductor is greater than the on/off threshold voltage of a DMOS transistor at the outermost position.Type: GrantFiled: January 19, 2010Date of Patent: June 26, 2012Assignee: Lapis Semiconductor Co., Ltd.Inventor: Shinobu Takehiro
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Patent number: 8193050Abstract: A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.Type: GrantFiled: October 18, 2010Date of Patent: June 5, 2012Assignee: United Microelectronics Corp.Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Tian-Fu Chiang, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
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Patent number: 8188469Abstract: A test device includes a semiconductor substrate having a first test region and a second test region defined thereon, wherein a layout of the first test region includes first active regions separated from each other by isolation regions in the semiconductor substrate, second active regions formed between the first active regions, first gate lines formed on the semiconductor substrate, wherein each of the first gate lines has a first end adjacent to one of the first active regions and a second end adjacent to an end of one of the second active regions, respectively, first shared contacts each formed over a respective one of the second ends of the first gate lines and an upper part of one of the first active regions, and first nodes formed on the first shared contacts to be electrically connected to the first shared contacts, respectively.Type: GrantFiled: July 14, 2009Date of Patent: May 29, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Jin Lee, Gin-Kyu Lee
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Patent number: 8188550Abstract: A method of forming an IC is presented. The method includes providing a substrate having a plurality of transistors formed thereon. The transistors have gate stack, source and drain regions. An electrical strap is formed and in contact with at least a portion of at least one sidewall of the gate stack of a first transistor to provide a continuous electrical flowpath over a gate electrode of the first transistor and the source or drain region of a second transistor.Type: GrantFiled: September 30, 2008Date of Patent: May 29, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Lieyong Yang, Siau Ben Chiah, Ming Lei, Hua Xiao, Xiongfei Yu, Kelvin Tianpeng Guan, Puay San Chia, Chor Shu Cheng, Gary Chia, Chee Kong Leong, Sean Lian, Kin San Pey, Chao Yong Li
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Patent number: 8183639Abstract: A dual port static random access memory cell has pull-down transistors, pull-up transistors, and pass transistors. A first active region has a first pull-down transistor coupled to a true data node, a second pull-down transistor coupled to a complementary data node; a first pass transistor coupled to the true data node, and a second pass transistor coupled to the complementary data node. A second active region has the same size and shape as the first active region and has a third pull-down transistor coupled in parallel to the first-pull down transistor, a fourth pull-down transistor coupled in parallel to the second pull-down transistor; a third pass transistor coupled to the true data node, and a fourth pass transistor coupled to the complementary data node. A first pull-up transistor and a second pull-up transistor are located between the first and second active regions.Type: GrantFiled: October 7, 2010Date of Patent: May 22, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Pierre Malinge, Jack M. Higman, Sanjay R. Parihar
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Patent number: 8178909Abstract: An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other.Type: GrantFiled: September 23, 2011Date of Patent: May 15, 2012Assignee: LSI CorporationInventors: Ramnath Venkatraman, Carl Anthony Monzel, III, Subramanian Ramesh
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Patent number: 8169030Abstract: In a static memory cell composed of four MOS transistors, the transistors composing a memory cell are formed on a substrate and have a drain, gate, and source arranged vertically with the gate surrounding a columnar semiconductor layer. In this memory cell, the first diffusion layers (second diffusion layers) functioning as a first memory node (second memory node) are connected via a first silicide layer (second silicide layer) formed on their surfaces, whereby an SRAM cell having a small area is realized. Furthermore, a first anti-leak diffusion layer (second anti-leak diffusion layer) having the conductivity type opposite to the first well is formed between the first well and the first diffusion layer (second diffusion layer) having the same conductivity type as the first well so as to prevent leak to the substrate.Type: GrantFiled: September 14, 2010Date of Patent: May 1, 2012Assignee: Unisantis Electronics Singapore Pte Ltd.Inventors: Fujio Masuoka, Shintaro Arai
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Publication number: 20120091537Abstract: In accordance with an embodiment, a semiconductor device includes an SRAM cell on a substrate. The SRAM cell includes: first and second load transistors each having an n-type source region and a p-type drain region, first and second driver transistors each having a p-type source region and an n-type drain region, and first and second transfer transistors each having an n-type source region and a n-type drain region. The n-type source regions of the first and second load transistors, the n-type drain regions of the first and second driver transistors, and the n-type source regions and the n-type drain regions of the first and second transfer transistors are located in a region other than a region present between any two of the p-type drain regions of the first and second load transistors and the p-type source regions of the first and second driver transistors.Type: ApplicationFiled: September 16, 2011Publication date: April 19, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kanna Adachi, Shigeru Kawanaka, Satoshi Inaba
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Patent number: 8154086Abstract: It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in an E/R type 4T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using four MOS transistors and two load resistor elements, each of the MOS transistor constituting the memory cell is formed on a planar silicon layer formed on a buried oxide film, to have a structure where a drain, a gate and a source are arranged in a vertical direction, wherein the gate is formed to surround a pillar-shaped semiconductor layer, and each of the load resistor elements is made of polysilicon and formed on the planar silicon layer.Type: GrantFiled: February 11, 2010Date of Patent: April 10, 2012Assignee: Unisantis Electronics Singapore Pte Ltd.Inventors: Fujio Masuoka, Shintaro Arai
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Patent number: 8138551Abstract: A semiconductor device includes a semiconductor substrate, a first transistor including a first gate electrode, a first diffusion region, and a second diffusion region respectively formed above the semiconductor substrate, second transistor including a second gate electrode, the first diffusion region, and a third diffusion region respectively formed above the semiconductor substrate, and a node electrode formed above the first diffusion layer, and coupled thereto. The first gate electrode and the second gate electrode are formed separately at respective side walls of the node electrode.Type: GrantFiled: March 31, 2009Date of Patent: March 20, 2012Assignee: Renesas Electronics CorporationInventor: Tomohiro Hamajima
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Patent number: 8134213Abstract: Disclosed is a static random access memory (SRAM), which includes first and second access transistors composed of metal oxide semiconductor (MOS) transistors, first and second drive transistors composed of MOS transistors, and first and second p-channel thin film transistors (TFTs) used as pull-up devices. The SRAM includes a ground potential layer disposed as a common source of the first and second drive transistors, and formed by implanting a dopant into a semiconductor substrate, a power supply potential layer connected with sources of the first and second p-channel TFTs, and an insulating layer formed on the substrate and interposed between the ground potential layer and the power supply potential layer.Type: GrantFiled: December 28, 2006Date of Patent: March 13, 2012Assignee: Dongbu Electronics Co., Ltd.Inventor: Sung Hee Park
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Patent number: 8124954Abstract: A conductive bridging random access memory (CBRAM) device and a method of manufacturing the same are provided. The CBRAM device includes a first electrode layer, a dielectric layer, a solid electrolyte layer, a second electrode layer and a metal layer. The solid electrolyte layer is located on the first electrode layer. The second electrode layer is located on the solid electrolyte layer. The metal layer is located near the solid electrolyte layer. The dielectric layer is located between the solid electrolyte layer and the metal layer. Since the metal layer is disposed near the solid electrolyte layer in the CBRAM device, it can generate a positive electric field during an erase operation, so as to accelerate a break of mutually connected metal filaments.Type: GrantFiled: May 27, 2009Date of Patent: February 28, 2012Assignee: Industrial Technology Research InstituteInventors: Ching-Chiun Wang, Cha-Hsin Lin
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Patent number: 8120116Abstract: Shared contact holes SC1 and SC2 reach both gate electrode layers GE1 and GE2 and a drain region PIR. In a planar view, a sidewall E2 of gate electrode layers GE1 and GE2 is shifted toward a side of a sidewall E4 from a virtual extended line E1a of the sidewall E1. In a planar view, a center line of a line width D1 in a portion that shared contact holes SC1 and SC2 of gate electrode layers GE1 and GE2 reach is located while shifted with respect to a center line of a line width D2 in a portion located on channel formation regions CHN1 and CHN2 of gate electrode layers GE1 and GE2. Therefore, a semiconductor device and a photomask that can suppress an opening defect of the shared contact hole are obtained.Type: GrantFiled: December 22, 2008Date of Patent: February 21, 2012Assignee: Renesas Electronics CorporationInventor: Masahiko Takeuchi
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Publication number: 20120037996Abstract: Improved SRAMs are formed with significantly reduced local interconnect to gate shorts, by a technique providing bidirectional, self-aligned local interconnects, employing a gate hard mask over portions of the gates not connected to the local interconnects. Embodiments include forming a gate hard mask over gates, forming bidirectional trenches overlying portions of the gate electrodes and active silicon regions, etching the hard mask layer to expose regions of the gate electrodes that are to connect to local interconnects, and filling the trenches with conductive material to form self-aligned local interconnects.Type: ApplicationFiled: October 25, 2011Publication date: February 16, 2012Applicant: GLOBALFOUNDRIES Inc.Inventors: Richard T. Schultz, Donald R. Weiss
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Patent number: 8114730Abstract: A shared contact structure, semiconductor device and method of fabricating the semiconductor device, in which the shared contact structure may include a gate electrode disposed on an active region of a substrate and including facing first and second sidewalls. The first sidewall may be covered with an insulating spacer. The source/drain regions may be formed within the active region adjacent the first sidewall, and provided on the opposite side of the second sidewall. A corner protection pattern may be formed adjacent the source/drain regions and the insulating spacer, and covered by an inter-layer dielectric. A shared contact plug may be formed through the inter-layer dielectric, to be in contact with the gate electrode, corner protection pattern and source/drain regions.Type: GrantFiled: July 20, 2010Date of Patent: February 14, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Abraham Yoo, Hee-Sung Kang, Heon-Jong Shin
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Patent number: 8115243Abstract: A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to avoid difficulties with forming sub-lithographic structures via etching processes. The body has ultra-thin dimensions and provides controlled short channel effects with reduced need for high doping levels. Buried data/bit lines are formed in an upper surface of a substrate from which the transistors extend. The transistor can be formed asymmetrically or offset with respect to the data/bit lines. The offset provides laterally asymmetric source regions of the transistors. Continuous conductive paths are provided in the data/bit lines which extend adjacent the source regions to provide better conductive characteristics of the data/bit lines, particularly for aggressively scaled processes.Type: GrantFiled: February 14, 2011Date of Patent: February 14, 2012Assignee: Micron Technology, Inc.Inventor: Leonard Forbes
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Patent number: 8097518Abstract: There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration diffusion region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration diffusion region (22), and a bit line(30) that includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves as a source region and a drain region, and a manufacturing method therefor. Reduction of source-drain breakdown voltage of the transistor is suppressed, and a low-resistance bit line can be formed. Thus, a semiconductor device that can miniaturize memory cells and a manufacturing method therefor can be provided.Type: GrantFiled: October 6, 2010Date of Patent: January 17, 2012Assignee: Spansion LLCInventor: Masatomi Okanishi
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Publication number: 20120001270Abstract: A method of manufacturing an integrated circuit (IC), comprising: defining a plurality of continuous active areas; forming conducting lines extending over the active areas; and using the conducting lines as a mask, introducing dopant into the active areas. Connections are provided between doped regions and conducting lines to form first and second circuit portions, at least one active area being continuous between those portions. In that active area, connections are provided between doped regions and conducting lines to form a pair of diode-connected transistors in reverse bias to one another between the first and second circuit portions, connected so as to leave a shared, unconnected doped region between the pair. The present invention also relates to a corresponding IC.Type: ApplicationFiled: October 24, 2008Publication date: January 5, 2012Applicant: ICERA INC.Inventor: Trevor Monk Kenneth
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Patent number: 8084788Abstract: A semiconductor fabrication method involving the use of eSiGe is disclosed. The eSiGe approach is useful for applying the desired stresses to the channel region of a field effect transistor, but also can introduce complications into the semiconductor fabrication process. Embodiments of the present invention disclose a two-step fabrication process in which a first layer of eSiGe is applied using a low hydrogen flow rate, and a second eSiGe layer is applied using a higher hydrogen flow rate. This method provides a way to balance the tradeoff of morphology, and fill consistency when using eSiGe. Embodiments of the present invention promote a pinned morphology, which reduces device sensitivity to epitaxial thickness, while also providing a more consistent fill volume, amongst various device widths, thereby providing a more consistent eSiGe semiconductor fabrication process.Type: GrantFiled: October 10, 2008Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: Judson Robert Holt, Abhishek Dube, Eric C. T. Harley, Shwu-Jen Jeng, Jeremy J Kempisty, Hasan Munir Nayfeh, Keith Howard Tabakman
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Patent number: 8080837Abstract: A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.Type: GrantFiled: April 19, 2006Date of Patent: December 20, 2011Assignee: Micron Technology, Inc.Inventor: Chandra Mouli
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Patent number: 8071448Abstract: A disclosed semiconductor device includes multiple gate electrodes disposed on a semiconductor substrate; and multiple sidewall spacers disposed on sidewalls of the gate electrodes. The thickness of the sidewall spacers is larger on the sidewalls along longer sides of the gate electrodes than on the sidewalls along shorter sides of the gate electrodes.Type: GrantFiled: August 19, 2009Date of Patent: December 6, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Masaki Okuno
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Patent number: 8058690Abstract: An apparatus including a first diffusion formed on a substrate, the first diffusion including a pair of channels, each of which separates a source from a drain; a second diffusion formed on the substrate, the second diffusion including a channel that separates a source from a drain; a first gate electrode formed on the substrate, wherein the first gate electrode overlaps one of the pair of channels on the first diffusion to form a pass-gate transistor; and a second gate electrode formed on the substrate, wherein the second gate electrode overlaps one of the pair of channels of the first diffusion to form a pull-down transistor and overlaps the channel of the second diffusion to form a pull-up transistor, and wherein the pass-gate, pull-down and pull-up transistors are of at least two different constructions. Other embodiments are disclosed and claimed.Type: GrantFiled: January 29, 2009Date of Patent: November 15, 2011Assignee: Intel CorporationInventor: Peter L. D. Chang
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Patent number: 8058702Abstract: A phase change memory cell is disclosed, including a first electrode and a second electrode, and a plurality of recording layers disposed between the first and second electrodes. The phase of an active region of each of the recording layers can be changed to a crystalline state or an amorphous state by current pulse control and hence respectively has crystalline resistance or amorphous resistance. At least two of the recording layers have different dimensions such that different combinations of the crystalline and amorphous resistance result in at least three different effective resistance values between the first and second electrodes. The phase change memory cell can be realized with the same material of the recording layers and thus can be fabricated with simple and currently developed CMOS fabrication process technologies. Furthermore, the phase change memory is easy to control due to large current programming intervals.Type: GrantFiled: October 26, 2006Date of Patent: November 15, 2011Assignees: Nanya Technology Corporation, Winbond Electronics Corp.Inventor: Te-Sheng Chao
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Patent number: 8059452Abstract: An integrated circuit and methods for laying out the integrated circuit are provided. The integrated circuit includes a first and a second transistor. The first transistor includes a first active region comprising a first source and a first drain; and a first gate electrode over the first active region. The second transistor includes a second active region comprising a second source and a second drain; and a second gate electrode over the second active region and connected to the first gate electrode, wherein the first source and the second source are electrically connected, and the first drain and the second drain are electrically connected.Type: GrantFiled: May 4, 2010Date of Patent: November 15, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Jhon-Jhy Liaw
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Patent number: 8044489Abstract: A semiconductor device having a phase-change memory cell comprises an interlayer dielectric film formed of, for example, SiOF formed on a select transistor formed on a main surface of a semiconductor substrate, a chalcogenide material layer formed of, for example, GeSbTe extending on the interlayer dielectric film, and a top electrode formed on the chalcogenide material layer. A fluorine concentration in an interface between the interlayer dielectric film and the chalcogenide material layer is higher than a fluorine concentration in an interface between the chalcogenide material layer and the top electrode.Type: GrantFiled: February 28, 2006Date of Patent: October 25, 2011Assignee: Renesas Electronics CorporationInventor: Yuichi Matsui
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Patent number: 8035170Abstract: A semiconductor device according to an embodiment of the invention includes: a semiconductor substrate; device regions formed on the semiconductor substrate, the device regions having a length direction in a predetermined direction; a plurality of transistors having gate electrodes, respectively, the gate electrodes extending in a direction approximately perpendicular to the predetermined direction, the plurality of transistors having a source/drain region and a channel region having a channel direction approximately parallel to the predetermined direction in the device region; a plurality of SRAM cells disposed in an array, each of the plurality of SRAM cells including the plurality of transistors; and a dummy region made of the substantially same material as that of the device regions, the dummy region being formed between the outermost device regions of the SRAM cells adjacent to each other in the direction approximately perpendicular to the predetermined direction, the dummy region having a length directiType: GrantFiled: November 25, 2008Date of Patent: October 11, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Satoshi Inaba
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Patent number: 8035126Abstract: A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A base of the PNP of the PNPN device is electrically common to the emitter/collector of the FET and a base of the NPN of the PNPN device is electrically common to the channel region of the FET. The anode pin of the PNPN device may be used as a word line or a bit line. A method of forming the 1T SRAM device is also disclosed.Type: GrantFiled: October 29, 2007Date of Patent: October 11, 2011Assignee: International Business Machines CorporationInventors: Phung T. Nguyen, Robert C. Wong
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Publication number: 20110241121Abstract: An SRAM cell of a semiconductor device includes a load transistor, a driver transistor and an access transistor. First source/drains of the load, driver and access transistors are connected to a node. A power line, a ground line and a bit line are electrically connected to second source/drains of the load transistor, the driver transistor and the access transistor. The power line, the ground line and the bit line are disposed at substantially the same level to extend in a first direction. A word line is electrically connected to a gate of the access transistor to extend in a second direction perpendicular to the first direction. The word line is disposed at a different level from the level of the power line, the ground line and the bit line.Type: ApplicationFiled: January 19, 2011Publication date: October 6, 2011Inventors: OhKyum Kwon, Byungsun Kim, Taejung Lee
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Patent number: 8004042Abstract: In accordance with an embodiment of the present invention, a static random access memory (SRAM) cell comprises a first pull-down transistor, a first pull-up transistor, a first pass-gate transistor, a second pull-down transistor, a second pull-up transistor, a second pass-gate transistor, a first linear intra-cell connection, and a second linear intra-cell connection. Active areas of the transistors are disposed in a substrate, and longitudinal axes of the active areas of the transistors are all parallel. The first linear intra-cell connection electrically couples the active area of the first pull-down transistor, the active area of the first pull-up transistor, and the active area of the first pass-gate transistor to a gate electrode of the second pull-down transistor and a gate electrode of the second pull-up transistor.Type: GrantFiled: March 20, 2009Date of Patent: August 23, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lie-Yong Yang, Feng-Ming Chang, Chang-Ta Yang, Ping-Wei Wang
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Patent number: 7998851Abstract: A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.Type: GrantFiled: March 2, 2010Date of Patent: August 16, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hoon Son, Yu-Gyun Shin, Jong-Wook Lee, Sun-Ghil Lee, In-Soo Jung, Young-Eun Lee, Deok-Hyung Lee
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Patent number: 7999300Abstract: A memory cell includes a substrate, an access transistor and a storage capacitor. The access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion region located on a first and second opposing sides of the gate stack. The storage capacitor comprises a first capacitor plate comprising a portion embedded within the substrate below the first diffusion region, a second capacitor plate and a capacitor dielectric sandwiched between the embedded portion of the first capacitor plate. At least a portion of the first diffusion region forms the second capacitor plate.Type: GrantFiled: January 28, 2009Date of Patent: August 16, 2011Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Zhao Lun, James Yong Meng Lee, Lee Wee Teo, Shyue Seng Tan, Chung Woh Lai, Johnny Widodo, Shailendra Mishra, Jeffrey Chee
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Patent number: 7994582Abstract: In a stacked load-less static random access memory (SRAM) device in which a pair of transmission transistors is stacked on a pair of driving transistors, the stacked load-less SRAM device includes first and second transistors arranged in first and second active regions separately on a semiconductor substrate and third and fourth transistors arranged on first and second semiconductor layers over the first and second transistors. A first drain region of the first transistor, a third drain region of the third transistor, and a second gate of the second transistor are electrically connected through a first contact node. A second drain region of the second transistor, a fourth drain region of the fourth transistor, and a first gate of the first transistor are electrically connected through a second contact node.Type: GrantFiled: October 16, 2009Date of Patent: August 9, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Han-byung Park, Hoon Lim
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Patent number: 7977800Abstract: The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.Type: GrantFiled: October 8, 2008Date of Patent: July 12, 2011Assignee: Panasonic CorporationInventors: Tsutomu Oosuka, Hisashi Ogawa, Yoshihiro Sato
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Publication number: 20110156149Abstract: The present disclosure provides a semiconductor structure including a semiconductor substrate having a device region and a dummy region adjacent the device region; a plurality of active regions in the device region; and a plurality of dummy active regions in the dummy region, where each of the active regions has a first dimension in a first direction and a second dimension in a second direction perpendicular to the first direction, and the first dimension is substantially greater than the second dimension; and each of the dummy active regions has a third dimension in the first direction and a fourth dimension in the second direction, and the third dimension is substantially greater than the fourth dimension. The plurality of dummy active regions are configured such that thermal annealing effect in the dummy region is substantially equal to that of the device region.Type: ApplicationFiled: December 31, 2009Publication date: June 30, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Li-Ting Wang, Jiunn-Ren Hwang
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Publication number: 20110156160Abstract: A semiconductor device with a metal oxide semiconductor (MOS) type transistor structure, which is used for, e.g. a static random access memory (SRAM) type memory cell, includes a part that is vulnerable to soft errors. In the semiconductor device with the MOS type transistor structure, an additional load capacitance is formed at the part that is vulnerable to soft errors.Type: ApplicationFiled: March 10, 2011Publication date: June 30, 2011Inventor: Hironobu Fukui
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Patent number: 7965540Abstract: A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).Type: GrantFiled: March 26, 2008Date of Patent: June 21, 2011Assignee: International Business Machines CorporationInventors: Ethan H. Cannon, Toshiharu Furukawa, David Horak, Charles W. Koburger, III, Jack A. Mandelman
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Patent number: 7960719Abstract: The invention provides a semiconductor device where data can be written after the production and forgery caused by rewriting of data can be prevented, and which can be manufactured at a low cost using a simple structure and an inexpensive material. Further, the invention provides a semiconductor device having the aforementioned functions, where wireless communication is not blocked by the internal structure. The semiconductor device of the invention has an organic memory provided with a memory cell array including a plurality of memory cells, a control circuit for controlling the organic memory, and a wire for connecting an antenna. Each of the plurality of memory cells has a transistor and a memory element. The memory element has a structure where an organic compound layer is provided between a first conductive layer and a second conductive layer. The second conductive layer is formed in a linear shape.Type: GrantFiled: November 21, 2005Date of Patent: June 14, 2011Assignee: Semiconductor Energy Laboratotry Co., Ltd.Inventor: Kiyoshi Kato
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Publication number: 20110133285Abstract: A static random access memory (SRAM) cell includes a straight fin and a bended fin physically disconnected from the straight fin. The bended fin has a first portion and a second portion parallel to the straight fin. The distance between the first portion of the bended fin and the straight fin is smaller than the distance between the second portion of the bended fin and the straight fin. The SRAM cell includes a pull-down transistor including a portion of a first gate strip, which forms a first and a second sub pull-down transistor with the straight fin and the first portion of the bended fin, respectively. The SRAM cell further includes a pass-gate transistor including a portion of a second gate strip, which forms a first sub pass-gate transistor with the straight fin. The pull-down transistor includes more fins than the pass-gate transistor.Type: ApplicationFiled: September 24, 2010Publication date: June 9, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Jhon-Jhy Liaw
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Publication number: 20110115010Abstract: Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level.Type: ApplicationFiled: November 10, 2010Publication date: May 19, 2011Inventors: Sunil Shim, Sunghoi Hur, Hansoo Kim, Jaehoon Jang, Hoosung Cho
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Patent number: 7923756Abstract: A semiconductor device with a metal oxide semiconductor (MOS) type transistor structure, which is used for, e.g. a static random access memory (SRAM) type memory cell, includes a part that is vulnerable to soft errors. In the semiconductor device with the MOS type transistor structure, an additional load capacitance is formed at the part that is vulnerable to soft errors.Type: GrantFiled: May 31, 2008Date of Patent: April 12, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Hironobu Fukui
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Patent number: 7923840Abstract: Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a first barrier oxide layer on a semiconductor substrate; forming the electrically conductive path within the first barrier oxide layer; and forming a second barrier oxide layer on the first barrier oxide layer. The electrically conductive path allows reduction of SRAM area by forming a wiring path underneath the barrier oxide layer on the SOI substrate.Type: GrantFiled: January 10, 2007Date of Patent: April 12, 2011Assignee: International Business Machines CorporationInventors: Gregory Costrini, Ramachandra Divakaruni, Jeffrey P. Gambino, Randy W. Mann
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Publication number: 20110073958Abstract: A memory cell having N transistors including at least one pair of access transistors, one pair of pull-down transistors, and one pair of pull-up transistors to form a memory cell, wherein N is an integer at least equal to six, wherein each of the access transistors and each of the pull-down transistors is a same one of an n-type or a p-type transistor, and each of the pull-up transistors is the other of an n-type or a p-type transistor, wherein at least one of the pair of the pull down transistors and the pair of the pull up transistors are asymmetric.Type: ApplicationFiled: September 25, 2009Publication date: March 31, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Leland Chang, Jeffrey W. Sleight