Abstract: A method of manufacturing a semiconductor device, comprising: forming, on a semiconductor substrate a gate insulating film for a high-voltage transistor of a peripheral circuit; forming on the gate insulating film a gate electrode for the high-voltage transistor; removing the gate insulating film positioned on the semiconductor substrate on both side portions of the gate electrode; forming an impurity diffusion region in a surface of the semiconductor substrate; depositing a first silicon oxide film to extend over surfaces of the gate electrode and the impurity diffusion region; etching the first silicon oxide film to form a spacer such that the spacer is formed on a side wall portion of the gate electrode and also extends over the surface of the semiconductor substrate; and forming a silicon nitride film on a surface of the spacer.

Abstract: A non-volatile memory device 100 contains: an insulating substrate 10; a first electrode 20 provided on the insulating substrate 10; a second electrode 30 provided on the insulating substrate 10; and a gap 40 set between the first electrode 20 and the second electrode 30, in which a distance G between the first electrode 20 and the second electrode 30 is: 0 nm<G?50 nm.

Abstract: Disclosed are embodiments of an improved integrated circuit device structure (e.g., a static random access memory array structure or other integrated circuit device structure incorporating both P-type and N-type devices) and a method of forming the structure that uses DTI regions for all inter-well and intra-well isolation and, thereby provides a low-cost isolation scheme that avoids FET width variations due to STI-DTI misalignment. Furthermore, because the DTI regions used for intra-well isolation effectively create some floating well sections, which must each be connected to a supply voltage (e.g., Vdd) to prevent threshold voltage (Vt) variations, the disclosed integrated circuit device also includes a shared contact to a junction between the diffusion regions of adjacent devices and an underlying floating well section. This shared contact eliminates the cost and area penalties that would be incurred if a discrete supply voltage contact was required for each floating well section.

Abstract: A system for terminating a homogenous cell array is disclosed. A preferred embodiment comprises a plurality of homogenous cells arranged in rows and columns to form the homogenous cell array, wherein a first homogenous cell of each column is electrically differently connected than a rest of the homogenous cells of the column.

Abstract: In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-channel type MISFETs whose gate electrodes and drains are respectively cross-connected, is formed in a shape that protrudes from the surface of a silicon oxide film. A silicon nitride film used as a capacitive insulating film, and an upper electrode are formed on the wiring. A capacitance can be formed of the wiring, the silicon nitride film and the upper electrode.

Abstract: A gate structure of a semiconductor device includes a first low resistance conductive layer, a second low resistance conductive layer, and a first type conductive layer disposed between and directly contacting sidewalls of the first low resistance conductive layer and the second low resistance conductive layer.

Abstract: Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.

Abstract: An SRAM cell using a vertical MISFET is provided, wherein underside source/drain areas of a first access transistor, a first driving transistor and a first load transistor are connected together, and further connected to gates of a second driving transistor and a second load transistor. Underside source/drain areas of a second access transistor, the second driving transistor and the second load transistor are connected together, and further connected to gates of the first driving transistor and the first load transistor. A first arrangement of the first access transistor, the first driving transistor and the first load transistor, and a second arrangement of the second access transistor, the second driving transistor and the second load transistor are symmetric to each other.

Abstract: A metal line of a semiconductor device having a diffusion barrier including CrxBy and a method for forming the same is described. The metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate. The insulation layer is formed having a metal line forming region. A diffusion barrier including a CrxBy layer is subsequently formed on the surface of the metal line forming region and the insulation layer. A metal line is finally formed to fill the metal line forming region of the insulation layer on the diffusion barrier including a CrxBy layer.

Abstract: A memory cell has N?6 transistors, in which two are access transistors, at least one pair [say (N?2)/2] are pull-up transistors, and at least another pair [say (N?2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed.

Abstract: In a three-dimensional semiconductor memory device, the device includes a semiconductor substrate having a recessed region, an active pattern extending in a direction transverse to the recessed region, an insulating pillar being adjacent to the active pattern and extending in the direction transverse to the recessed region, and a lower select gate facing the active pattern and extending horizontally on the semiconductor substrate. The active pattern is disposed between the insulating pillar and the lower select gate.

Abstract: Hybrid carbon nanotube FET (CNFET), static ram (SRAM) and method of making same. A static ram memory cell has two cross-coupled semiconductor-type field effect transistors (FETs) and two nanotube FETs (NTFETs), each having a channel region made of at least one semiconductive nanotube, a first NTFET connected to the drain or source of the first semiconductor-type FET and the second NTFET connected to the drain or source of the second semiconductor-type FET.

Abstract: A SRAM bit cell and an associated method of producing the SRAM bit cell with improved performance and stability is provided. In one configuration, channel mobility of the transistors within the SRAM bit cell may be adjusted to provide improved stability. In order to adjust the channel mobility, a stress memorization technique may be used, a wide spacer may be used, germanium may be implanted on tensile stress silicon nitride, a compressive liner may be used or silicon germanium may be embedded in one or more of the devices in the cell. In another configuration, the gate capacitance of each device within the SRAM bit cell may be adjusted to achieve high SRAM yield. For instance, a thick gate oxide may be used, phosphorous pre-doping may be used or fluorine pre-doping may be used in one or more of the devices within the cell.

Abstract: A semiconductor memory device according to one embodiment includes: a semiconductor substrate having an active region divided by an element isolation region; a plurality of stacked-gate type memory cell transistors connected in series on the active region; select transistors connected to both ends of the plurality of memory cell transistors on the active region; and a bit line contact connected to a drain region belonging to the select transistor in the active region, a vertical cross sectional shape of a lower portion of the bit line contact in a channel width direction of the plurality of memory cell transistors being in a skirt shape.

Abstract: Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon nanotube according to the pattern of a one dimensional circuit layout. Electrical isolation may be provided by cutting a portion of the carbon nanotube, forming a reverse biased junction of a hole-induced region and an electron-induced region of the carbon nanotube, or electrically biasing a region through a dielectric layer between two device regions of the carbon nanotube. The carbon nanotubes may be arranged such that hole-inducing material layer and electron-inducing material layer may be assigned to each carbon nanotube to form periodic structures such as a static random access memory (SRAM) array.

Abstract: In a static memory cell comprising six MOS transistors, the MOS transistors have a structure in which the drain, gate and source formed on the substrate are arranged in the vertical direction and the gate surrounds the columnar semiconductor layer, the substrate comprises a first active region having a first conductive type and a second active region having a second conductive type, and diffusion layers constructing the active regions are mutually connected via a silicide layer formed on the substrate surface, thereby realizing an SRAM cell with small surface area. In addition, drain diffusion layers having the same conductive type as a first well positioned on the substrate are surrounded by a first anti-leak diffusion layer and a second anti-leak diffusion layer having a conductive type different from the first well and being shallower than the first well, and thereby controlling leakage to the substrate.

Abstract: A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.

Abstract: Both a compressive-stress-applying insulating film and a tensile-stress-applying insulating film cover an N-type MIS transistor formed at an SRAM access region of a semiconductor substrate. On the other hand, a tensile-stress-applying insulating film covers an N-type MIS transistor formed at an SRAM drive region of the semiconductor substrate.

Abstract: A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein each of the transistors comprises a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; and the first and second driving transistors each have a channel width larger than that of at least either each of the load transistors or each of the access transistors.

Abstract: A first transfer transistor includes a first diffusion layer connected to a first bit line, and a second diffusion layer connected to a first storage node, the first diffusion layer is provided in a substrate, the second diffusion layer is provided in a bottom part of a recess provided in the substrate, a channel region of the first transfer transistor is offset with respect to the second diffusion layer toward the first storage node, and the offset part functions as a resistor.

Abstract: There is provided a semiconductor device including a semiconductor substrate (10), a high concentration diffusion region (22) formed within the semiconductor substrate (10), a first low concentration diffusion region (24) that has a lower impurity concentration than the high concentration diffusion region (22) and is provided under the high concentration diffusion region (22), and a bit line (30) that includes the high concentration diffusion region (22) and the first low concentration diffusion region (24) and serves as a source region and a drain region, and a manufacturing method therefor. Reduction of source-drain breakdown voltage of the transistor is suppressed, and a low-resistance bit line can be formed. Thus, a semiconductor device that can miniaturize memory cells and a manufacturing method therefor can be provided.

Abstract: In general, in one aspect, a method includes forming a semiconductor substrate having N-diffusion and P-diffusion regions. A gate stack is formed over the semiconductor substrate. A gate electrode hard mask is formed over the gate stack. The gate electrode hard mask is augmented around pass gate transistors with a spacer material. The gate stack is etched using the augmented gate electrode hard mask to form the gate electrodes. The gate electrodes around the pass gate have a greater length than other gate electrodes.

Abstract: A microelectronic device including, on a substrate, at least one element such as a SRAM memory cell; one or more first transistor(s), respectively including a number k of channels (k?1) parallel in a direction forming a non-zero angle with the main plane of the substrate, and one or more second transistor(s), respectively including a number m of channels, such that m>k, parallel in a direction forming a non-zero angle, or an orthogonal direction, with the main plane of the substrate.

Abstract: A semiconductor memory device includes a plurality of memory cell arrays each includes a plurality of memory cells, the plurality of memory cell arrays being stacked on a semiconductor substrate to form a three-dimensional structure, a first well formed in the semiconductor substrate and having a first conductivity type, an element isolation insulating film including a bottom surface shallower than a bottom surface of the first well in the first well, and buried in the semiconductor substrate, a second well including a bottom surface shallower than the bottom surface of the first well in the first well, formed along a bottom surface of at least a portion of the element isolation insulating film, and made of an impurity having a second conductivity type, and a contact line electrically connected to the first well.

Abstract: A semiconductor device includes: a ferroelectric capacitor that is provided above a base substrate and includes a first electrode, a ferroelectric film provided on the first electrode and a second electrode provided on the ferroelectric film; a stopper film that covers a top surface of the second electrode of the ferroelectric capacitor; a hydrogen barrier film that covers a top surface and a side surface of the stopper film and a side surface of the ferroelectric capacitor; an interlayer dielectric film that covers the hydrogen barrier film and the base substrate; a contact hole that penetrates the interlayer dielectric film, the hydrogen barrier film and the stopper film and exposes the second electrode; a barrier metal that covers the second electrode exposed in the contact hole and an inner wall surface of the contact hole and is composed of a conductive material having hydrogen barrier property; and a plug conductive section that is embedded in the contact hole and conductively connects to the barrier me

Abstract: A semiconductor thin film is formed having a lateral growth region which is a collection of columnar or needle-like crystals extending generally parallel with a substrate. The semiconductor thin film is illuminated with laser light or strong light having equivalent energy. As a result, adjacent columnar or needle-like crystals are joined together to form a region having substantially no grain boundaries, i.e., a monodomain region which can substantially be regarded as a single crystal. A semiconductor device is formed by using the monodomain region as an active layer.

Abstract: A circuit array includes a plurality cells, wherein each cell has at least one group of odd fins. The cells may be arranged in a repeating pattern that includes mirror images of the pattern. A plurality of fin forming regions are provided about which the fins are formed for the dual fin and single fin transistors.

Abstract: A gate electrode is provided such that both ends thereof in a gate width direction are projected from an active region in plane view. Partial trench isolation insulation films are provided in a surface of an SOI substrate corresponding to lower parts of the both ends, and body contact regions are provided in the surface of the SOI substrate outside the both ends of the gate electrode in the gate width direction so as to be adjacent to the respective partial trench isolation insulation films. The body contact region and a body region are electrically connected through an SOI layer (well region) under the partial trench isolation insulation film. In addition, a source tie region in which P type impurity is doped in a relatively high concentration is provided in the surface of a source region in the vicinity of the center of the gate electrode in the gate width direction.

Abstract: A semiconductor memory device includes the first transistor having first and second source/drain diffusion regions positioned below a second bit line to sandwich the first word line therebetween, and the second source/drain diffusion region positioned between the first and second word lines and connected to a first bit line, a second transistor having second and third source/drain diffusion regions positioned below the second bit line to sandwich the second word line therebetween, a first resistive memory element formed below the second bit line above the first source/drain diffusion region, and having terminals connected to the second bit line and the first source/drain diffusion region, and a second resistive memory element formed below the second bit line above the third source/drain diffusion region, and having terminals connected to the second bit line and the third source/drain diffusion region.

Abstract: In accordance with an embodiment of the present invention, a static random access memory (SRAM) cell comprises a first pull-down transistor, a first pull-up transistor, a first pass-gate transistor, a second pull-down transistor, a second pull-up transistor, a second pass-gate transistor, a first linear intra-cell connection, and a second linear intra-cell connection. Active areas of the transistors are disposed in a substrate, and longitudinal axes of the active areas of the transistors are all parallel. The first linear intra-cell connection electrically couples the active area of the first pull-down transistor, the active area of the first pull-up transistor, and the active area of the first pass-gate transistor to a gate electrode of the second pull-down transistor and a gate electrode of the second pull-up transistor.

Abstract: According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device including: sequentially forming a first insulating film, a first electrode film, a second insulating film, and a second electrode film on a substrate; forming a groove that separates the second electrode film, the second insulating film and the first electrode film; forming an insulating film inside the groove so that an upper surface thereof is positioned between upper surfaces of the second electrode film and the second insulating film; forming an overhung portion on the second electrode film so as to overhang on the insulating film by performing a selective growth process; and forming a low resistance layer at the overhung portion and the second electrode film by performing an alloying process.

Abstract: A local interconnect is formed with a gate conductor line that has an exposed sidewall on an active area of a semiconductor substrate. The exposes sidewall comprises a silicon containing material that may form a silicide alloy upon silicidation. During a silicidation process, a gate conductor sidewall silicide alloy forms on the exposed sidewall of the gate conductor line and an active area silicide is formed on the active area. The two silicides are joined to provide an electrical connection between the active area and the gate conductor line. Multiple sidewalls may be exposed on the gate conductor line to make multiple connections to different active area silicides.

Abstract: Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.

Abstract: A method of processing a substrate of a device comprises the as following steps. Form a cap layer over the substrate. Form a dummy layer over the cap layer, the cap layer having a top surface. Etch the dummy layer forming patterned dummy elements of variable widths and exposing sidewalls of the dummy elements and portions of the top surface of the cap layer aside from the dummy elements. Deposit a spacer layer over the device covering the patterned dummy elements and exposed surfaces of the cap layer. Etch back the spacer layer forming sidewall spacers aside from the sidewalls of the patterned dummy elements spaced above a minimum spacing and forming super-wide spacers between sidewalls of the patterned dummy elements spaced less than the minimum spacing. Strip the patterned dummy elements. Expose portions of the substrate aside from the sidewall spacers. Pattern exposed portions of the substrate by etching into the substrate.

Abstract: A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A base of the PNP of the PNPN device is electrically common to the emitter/collector of the FET and a base of the NPN of the PNPN device is electrically common to the channel region of the FET. The anode pin of the PNPN device may be used as a word line or a bit line. A method of forming the 1T SRAM device is also disclosed.

Abstract: A shared contact structure, semiconductor device and method of fabricating the semiconductor device, in which the shared contact structure may include a gate electrode disposed on an active region of a substrate and including facing first and second sidewalls. The first sidewall may be covered with an insulating spacer. The source/drain regions may be formed within the active region adjacent the first sidewall, and provided on the opposite side of the second sidewall. A corner protection pattern may be formed adjacent the source/drain regions and the insulating spacer, and covered by an inter-layer dielectric. A shared contact plug may be formed through the inter-layer dielectric, to be in contact with the gate electrode, corner protection pattern and source/drain regions.

Abstract: To provide a semiconductor integrated circuit device capable of increasing a capacitor capacitance. A semiconductor integrated circuit device according to an embodiment of the present invention includes: a circuit element formed on a semiconductor substrate; and capacitors formed on the semiconductor substrate and including: a lower capacitance electrode formed of a lower wiring line connected to the circuit element; a capacitance insulating film covering an upper surface and a side surface of the lower wiring line; and an upper capacitance electrode formed on the capacitance insulating film, the lower capacitance electrode including at least one of a power supply line and a ground line formed of the lower wiring line.

Abstract: A memory array with a row of strapping cells is provided. In accordance with embodiments of the present invention, strapping cells are positioned between two rows of a memory array. The strapping cells provide a P+ strap between N+ active areas of two memory cells in a column and provide an N+ strap between P+ active areas of two memory cells in a column of the memory array. The strapping cells provide an insulating structure between the two rows of the memory array and create a more uniform operation of the memory cells regardless of the positions of the memory cells within the memory array. In an embodiment, a dummy N-well may be formed along the outer edge of the memory array in a direction perpendicular to the row of strapping cells. Furthermore, transistors may be formed in the strapping cells to provide additional insulation between the strapped memory cells.

Abstract: A full complementary metal-oxide semiconductor (CMOS) static random access memory (SRAM) may have a reduced cell size by arranging a word line of a pair of transistors arranged on the uppermost layer of the SRAM. First and second transistors may be arranged on first and second active regions. Third and fourth transistors may be arranged on first and second semiconductor layers formed over the first and second active regions. Fifth and sixth transistors may be arranged on the third and fourth semiconductor layers over the first and second semiconductor layers. A word line may be arranged in a straight line between the first and second gates of the first and second transistors and between the third and fourth gates of the third and fourth transistors.

Abstract: In a stacked load-less static random access memory (SRAM) device in which a pair of transmission transistors is stacked on a pair of driving transistors, the stacked load-less SRAM device includes first and second transistors arranged in first and second active regions separately on a semiconductor substrate and third and fourth transistors arranged on first and second semiconductor layers over the first and second transistors. A first drain region of the first transistor, a third drain region of the third transistor, and a second gate of the second transistor are electrically connected through a first contact node. A second drain region of the second transistor, a fourth drain region of the fourth transistor, and a first gate of the first transistor are electrically connected through a second contact node.

Abstract: A memory cell includes a substrate, an access transistor and a storage capacitor. The access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion region located on a first and second opposing sides of the gate stack. The storage capacitor comprises a first capacitor plate comprising a portion embedded within the substrate below the first diffusion region, a second capacitor plate and a capacitor dielectric sandwiched between the embedded portion of the first capacitor plate. At least a portion of the first diffusion region forms the second capacitor plate.

Abstract: Mask sets, layout design, and methods for forming contacts in devices are described. In one embodiment, a semiconductor device includes a plurality of contacts disposed over a substrate, the plurality of contacts being disposed as rows and columns on an orthogonal grid, each row of the plurality of contacts is spaced from an neighboring row of the plurality of contacts by a first distance, and each column of the plurality of contacts is spaced from an neighboring column of the plurality of contacts by a second distance.

Abstract: A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

Abstract: To provide a semiconductor device and a method of manufacturing the same capable of suppressing, when a plurality of MIS transistors having different absolute values of threshold voltage is used, the reduction of the drive current of a MIS transistor having a greater absolute value of threshold voltage. The threshold voltage of a second nMIS transistor is greater than the threshold voltage of a first nMIS transistor and the sum of the concentration of lanthanum atom and the concentration of magnesium atom in a second nMIS high-k film included in the second nMIS transistor is lower than the sum of the concentration of lanthanum atom and the concentration of magnesium atom in a first nMIS high-k film included in the first nMIS transistor.

Abstract: A semiconductor memory device has bit lines, capacitors, bit contacts and capacitor contacts, wherein the bit lines are provided over a semiconductor substrate, the bit lines are connected to the semiconductor substrate through the bit contacts, the capacitors are connected to the semiconductor substrate through the capacitor contacts, and wherein in two adjacent bit lines, pitch d2 (first pitch) representing a pitch of portions provided with the capacitor contacts is larger than pitch d3 (second pitch) representing a pitch of portions provided with the bit contacts, and distance d4 between two such bit lines in the portions provided with the bit contacts is larger than width d5 of the bit lines in the portions provided with the bit contacts.

Abstract: A FinFET SRAM transistor device includes transistors formed on fins with each transistor including a semiconductor channel region within a fin plus a source region and a drain region extending within the fin from opposite sides of the channel region with fin sidewalls having a gate dielectric formed thereon. Bilateral transistor gates extend from the gate dielectric. An asymmetrically doped FinFET transistor has source/drain regions doped with a first dopant type, but the asymmetrically doped FinFET transistor include at least one of the bilateral transistor gate electrode regions on one side of at least one of the fins counterdoped with respect to the first dopant type. The finFET transistors are connected in a six transistor SRAM circuit including two PFET pull-up transistors, two NFET pull down transistors and two NFET passgate transistors.

Abstract: An integrated circuit and methods for laying out the integrated circuit are provided. The integrated circuit includes a first and a second transistor. The first transistor includes a first active region comprising a first source and a first drain; and a first gate electrode over the first active region. The second transistor includes a second active region comprising a second source and a second drain; and a second gate electrode over the second active region and connected to the first gate electrode, wherein the first source and the second source are electrically connected, and the first drain and the second drain are electrically connected.

Abstract: A dynamic random access memory (DRAM) is provided. The DRAM comprises a substrate, a vertical transistor, a deep trench capacitor and a buried strap. The substrate has a trench and a deep trench located on one side of the trench thereon. The vertical transistor is disposed in the trench, a portion of which is disposed on the substrate. The deep trench capacitor is disposed in the deep trench, and comprises a bottom electrode, a capacitor dielectric layer and a top electrode. The vertical transistor comprises a gate structure disposed in the trench and above the substrate, a first doped region disposed in the substrate on sidewalls and bottom of the trench, and a second doped region disposed in the substrate on top of the trench. The buried strap is disposed in the substrate below the vertical transistor, and is adjoined to the first doped region and the top electrode.

Abstract: An SRAM semiconductor device includes: at least a first and a second field effect transistor formed on a same substrate, each of the transistors including a gate stack, each gate stack including a semiconductor layer disposed on a metal layer, the metal layer being disposed on a high-k dielectric layer located over a chemical region, wherein the metal layer of the first gate stack and the metal layer of the second gate stack have approximately a same work function, and wherein each channel region has approximately a same band gap.

Abstract: A semiconductor memory device is constructed to include a memory cell formed by a plurality of transistors, wherein each of gate wiring layers of all of the transistors forming the memory cell is arranged to extend in one direction.