Surface Channel Ccd (epo) Patents (Class 257/E29.237)
  • Patent number: 8461010
    Abstract: In conventional processes, a recombination rate of minority carrier accumulated between a diffusion layer of an anode and a diffusion layer of a cathode cannot be enhanced. An interlayer insulating film 20 is formed on a semiconductor substrate 10. An opening 22 (first opening), an opening 24 (second opening) and an opening 26 are formed in the interlayer insulating film 20. The opening 22 and the opening 26 are formed above respective the p-type diffusion layer 16 and the n-type diffusion layer 18. The opening 24 is formed above the gap region that is a region between the p-type diffusion layer 16 and the n-type diffusion layer 18. A contact plug 32, a contact plug 34 and a contact plug 36 are embedded in the opening 22, the opening 24 and the opening 26 respectively. Both regions of the semiconductor substrate 10 located under the opening 22 among and located under the opening 24 are doped with an impurity.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: June 11, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Masaharu Sato
  • Patent number: 8293591
    Abstract: A field effect transistor for detecting an analyte having a thiol group includes a substrate, a source region and a drain region formed apart from each other on the substrate, the source region and the drain region being doped such that a polarity of the source and drain region is opposite to a polarity of the substrate, a channel region disposed between the source region and the drain region, an insulating layer formed of an electrically insulating material and disposed on the channel region, a gold layer disposed on the insulating layer and a reference electrode disposed apart from the gold layer.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: October 23, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeo-young Shim, Kyu-tae Yoo, Kyu-sang Lee, Won-seok Chung, Yeon-ja Cho, Chang-eun Yoo
  • Patent number: 8053776
    Abstract: In a vertical diode, an N+-type layer, an N?-type layer, and a P+-type layer are stacked in this order on a lower electrode film, and an upper electrode film is provided thereon. The effective impurity concentration of the N?-type layer is lower than the effective impurity concentrations of the N+-type layer and the P+-type layer. At least one of the N+-type layer, the N?-type layer, and the P+-type layer is formed from a small grain size polycrystalline semiconductor whose each crystal grain does not penetrate each layer through its thickness.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: November 8, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takuo Ohashi
  • Patent number: 7605411
    Abstract: An HCCD includes a channel 21 that transfers electric charges in an X direction, a channel 25 that transfers the electric charges in a Z1 direction, a channel 23 that transfers the electric charges in a Z2 direction, and a channel 22 that connects the channels 23, 25 to the channel 21. The following relation is satisfied in impurity concentration of the channels: channel 21 channel 22 channel 23, 25. A fixed DC voltage is applied to branch electrodes 12a, 12b above the channel 22. The channel 22 has protrusion portions 19 that protrude inward from an outer circumference, which connects T1 and T2, and an outer circumference, which connects T3 and T4. The protrusion portions 19 causes charges below the transfer electrode 11b to move near the center of the channel 22 in a Y direction. Thereby, the travel distance of the charges in the channel 22 is reduced.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: October 20, 2009
    Assignee: Fujifilm Corporation
    Inventors: Hirokazu Shiraki, Makoto Kobayashi, Katsumi Ikeda
  • Publication number: 20080023797
    Abstract: In conventional processes, a recombination rate of minority carrier accumulated between a diffusion layer of an anode and a diffusion layer of a cathode cannot be enhanced. An interlayer insulating film 20 is formed on a semiconductor substrate 10. An opening 22 (first opening), an opening 24 (second opening) and an opening 26 are formed in the interlayer insulating film 20. The opening 22 and the opening 26 are formed above respective the p-type diffusion layer 16 and the n-type diffusion layer 18. The opening 24 is formed above the gap region that is a region between the p-type diffusion layer 16 and the n-type diffusion layer 18. A contact plug 32, a contact plug 34 and a contact plug 36 are embedded in the opening 22, the opening 24 and the opening 26 respectively. Both regions of the semiconductor substrate 10 located under the opening 22 among and located under the opening 24 are doped with an impurity.
    Type: Application
    Filed: July 25, 2007
    Publication date: January 31, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Masaharu SATO