Abstract: A multi-level voltage converter having a first switching circuit including a flying capacitor coupled in parallel with first switches coupled in series, the first switches configured to be driven by a first duty command having a first duty cycle; a second switching circuit including the flying and second switches coupled in series between input voltage terminals of an input voltage, the second switches configured to be driven by a second duty command having a second duty cycle; and a control circuit configured to balance a voltage of the flying capacitor by controlling an interleaved constant frequency modulator to generate the first and second duty cycle commands such that the first and second duty cycles are the same.

Abstract: A power supply system comprises: multiple switched-capacitor converters and a controller. The multiple switched-capacitor converters include at least a first switched-capacitor converter interleaved with a second switched-capacitor converter. During operation, the controller produces control signals. The control signals control the interleaved first switched-capacitor converter and the second switched-capacitor converter to produce an output voltage to power a load.

Abstract: A power semiconductor package includes a reference voltage terminal, a supply voltage terminal, a phase terminal, a first power transistor and a second power transistor. The first power transistor and the second power transistor are connected in series and form a low side switch and a high side switch of a half bridge circuit.

Abstract: A drive circuit for a serial communications system is provided. The drive circuit may include a mode controller, a pre-drive circuit, and a main drive circuit. The main drive circuit includes multiple mode control switches and at least one pair of differential switches. The mode controller is configured to: generate a mode control signal, and transmit the mode control signal to the main drive circuit. The pre-drive circuit is configured to: convert a differential digital signal into a differential control signal, and transmit the differential control signal to the main drive circuit. The main drive circuit controls on/off states of the multiple mode control switches according to the mode control signal, and works in corresponding working modes. The drive circuit controls the states of the mode control switches in the main drive circuit, so that the main drive circuit works in different working modes.

Abstract: An object of the present invention is to provide a semiconductor device that can enhance the safety when feeding to a USB device. Provided is a semiconductor device including: a first power source circuit that generates an output voltage supplied to a USB device coupled to a USB connector; an abnormality detection circuit that determines the state of a supply route of the output voltage generated by the first power source circuit; and a control circuit that controls supply of the output voltage from the first power source circuit to the USB device on the basis of a determination result of the abnormality detection circuit.

Abstract: A modular power conversion device includes at least one first-type energy storage device (ESD) configured to induce a first direct current (DC) voltage, and at least one active power link module (APLM) string coupled to the at least one first-type ESD. The at least one APLM string includes a plurality of APLMs coupled to each other. Each APLM of the plurality of APLMs has a plurality of switching devices including a first switching device and a second switching device coupled to each other in electrical series. Each APLM of the plurality of APLMs also has at least one second-type ESD coupled in electrical parallel with both of the first switching device and the second switching device. The at least one second-type ESD is configured to induce a second DC voltage.

Abstract: Voltage balancing and extracted output power circuit topologies use maximum power point and maximum power point tracking to provide voltage balancing and voltage and current adjustment to optimize extracted output power for corresponding DC voltage source strings (120a, 130a). The topologies used to control power generation include one or more voltage balancing circuits and/or power system optimizer circuits (102a) to reduce decreased power utilization and enable independent operating voltages of DC voltage source strings (120a, 130a) to provide voltage balancing and to deliver a maximum power independent of the voltage and current of other DC voltage source strings (120a, 130a). The current flowing in each DC voltage source string is controlled by the duty ratio of the corresponding switch (101a, 108a). The circuit topologies can include a plurality of voltage balancing/power system optimizer circuits (102a).

Abstract: A voltage dropping apparatus may include: a voltage dropping unit receiving an input voltage, outputting the input voltage in a first mode, and dropping a level of the input voltage in a second mode; a voltage output unit connected to the voltage dropping unit, receiving and outputting the input voltage in the first mode, and receiving and outputting the dropped voltage in the second mode; and a control unit receiving a mode signal and controlling a mode change of the voltage dropping unit and the voltage output unit based on a value of the mode signal.

Abstract: The present description relates to a gallium nitride transistor which includes at least one source/drain structure having low contact resistance between a 2D electron gas of the gallium nitride transistor and the source/drain structure. The low contact resistance may be a result of at least a portion of the source/drain structure being a single-crystal structure abutting the 2D electron gas. In one embodiment, the single-crystal structure is grown with a portion of a charge inducing layer of the gallium nitride transistor acting as a nucleation site.

Abstract: A control unit capable of accurately calculating a magnetization bias of a transformer is provided, thereby appropriately reducing the magnetization bias. The control unit acquires first and second currents that flow through a transformer during a period where either first or second switches individually turn ON. The control unit predicts an amount of magnetization bias in either positive side or negative side of the excitation current that flows through the transformer. The control unit reduces the magnetization bias of the transformer based on the predicted amount of magnetization bias.

Abstract: A transformation system capable of efficiently transforming electrical power from one dc voltage to a second dc voltage or of regulating power flow within a network of constant nominal voltage; in each case without intermediate magnetic transformation. The transformation system is based on periodic and resonant delivery of charge from the first of two dc nodes to a system of capacitors, electrical reconfiguration of those capacitors, then delivery of power to a second dc node.

Abstract: A circuit includes a charge pump to generate an output reference voltage. A first bootstrap refresh circuit receives the reference voltage from the charge pump and is coupled between first and second bootstrap nodes of a DC/DC converter. The first bootstrap refresh circuit supplies first charge current that is sourced from the first bootstrap node to the second bootstrap node based on a control signal indicating a first operating mode of the DC/DC converter. A second bootstrap refresh circuit receives the reference voltage from the charge pump and is coupled between the first and second bootstrap nodes of the DC/DC converter. The second bootstrap refresh circuit supplies second charge current from the second bootstrap node to the first bootstrap node based on the control signal indicating a second operating mode of the DC/DC converter.

Abstract: A voltage control apparatus includes a boost converter configured to convert an input voltage to a voltage equal to or higher than a first voltage in an operative state and directly output the input voltage in an inoperative state, a buck-boost converter coupled with the boost converter in parallel and configured to convert the input voltage to a second voltage lower than the first voltage, a memory, and a processor coupled to the memory and configured to keep the buck-boost converter in the operative state, set the boost converter to the inoperative state when the input voltage is equal to or higher than the first voltage, and change the boost converter to the operative state when the input voltage is lower than the first voltage.

Abstract: The present invention relates to a technique for implementing a bidirectional DC-DC converter applied to an energy storage system. The bidirectional DC-DC converter includes a magnetically coupled inductor and a charging/discharging voltage storage unit between a DC link power supply and a battery power supply, and implements a high gain through a two-step voltage transformation process when a charging process or discharging process is performed. Thus, the bidirectional DC-DC converter can reduce the construction cost of the battery cell, guarantee a high voltage available range, and reduce the influence of leakage inductance.

Abstract: A method and apparatus for switched mode power supply (SMPS) system includes circuitry configured to produce a voltage output based on an input voltage, the SMPS circuitry includes inductive, capacitive and switching elements configured to generate the voltage output. The switching elements include at least one set of cascode coupled devices, each set of cascode coupled devices including a high electron mobility transistor (HEMT) and one of a diode and a field effect transistor (FET) in a cascode coupling. A controller produces a signal to a gate terminal of the FET of the sets of cascode coupled devices to drive the HEMT switching rate to adjust the output voltage. The circuitry of the SMPS further includes circuitry to couple the substrate of at least one HEMT to a high voltage node of the SMPS system to reduce large voltage spikes or dv/dts.

Abstract: A reference voltage generation circuit includes a loading block suitable for generating a reference current and first and second mirroring currents obtained by mirroring the reference current based on a power source voltage, a biasing block suitable for generating a first bias voltage controlled corresponding to variations in the power source voltage and a second bias voltage controlled corresponding to variations in temperature based on the first mirroring current, a compensation block suitable for compensating for the reference current based on the first and second bias voltages, and an output load block suitable for generating a reference voltage which corresponds to the reference current based on the second mirroring current.

Abstract: Provided is a sensor device that suppresses a malfunction caused by a negative surge or a voltage drop. A sensor device includes a sensor element having an electrical characteristic varying according to a physical amount, a signal processing circuit configured to process an output signal of the sensor element, a transistor element interposed between a power source terminal and the signal processing circuit, a resistive element configured to connect a drain and a gate of the transistor element, or a collector and a base of the transistor element, and an element having threshold voltage for connecting the gate or the base of the transistor element to a GND. The element regulates current flowing from the resistive element in a direction of the GND, in a case in which supply voltage to the signal processing circuit falls below the threshold voltage.

Abstract: Electronic modules with small and flexible interfaces are disclosed. One example electronic module includes a power supply terminal configured to receive power for the electronic module and circuitry configured to carry out various functions. The functions carried out by the electronic module circuitry include simultaneously receiving both of the following via the power supply terminal: a power signal for carrying out a mission mode operation of the electronic module, and a data signal.

Abstract: A first switching element and a gate of a voltage-driven switching element are connected by a gate turn-on wiring through a first resistor. The gate of the voltage-driven switching element and a second switching element are connected by a gate turn-off wiring through a second resistor. A charge pump unit has a first capacitor, and a second capacitor configured to output a negative voltage. A resistor unit is arranged in at least one of a first wiring configured to connect the gate turn-on wiring and the first capacitor and a second wiring configured to connect the gate turn-off wiring and the first capacitor, and is configured to charge the first capacitor through the first wiring when the first switching element is turned on and to discharge the first capacitor through the second wiring when the second switching element is turned on.

Abstract: A semiconductor device PKG includes a semiconductor chip CP, a lead LD3, a wire BW5 electrically connecting a pad electrode PD2 of the semiconductor chip CP to the lead LD3, a wire BW3 electrically connecting a pad electrode PD3 of the semiconductor chip CP to the lead LD3, and a sealing body sealing them with a resin. The semiconductor chip CP includes internal circuits 5b and 5c, and a switch circuit unit SW. Signal transmission is possible between the internal circuit 5c and the pad electrode PD3. The switch circuit unit SW is a circuit capable of being set in a first state in which signal transmission is possible between the internal circuit 5b and the pad electrode PD2, and in a second state in which signal transmission is not possible between the internal circuit 5b and the pad electrode PD2. The switch circuit unit SW is fixed to the second state during operation of the semiconductor device PKG.

Abstract: A power switching circuit provides temperature compensation for an insulated gate power switching device. A timing circuit determines a switch timing signal comprising desired on and off switching times of the switching device. A temperature monitor quantifies a device temperature. A gate drive profile generator generates a switching device drive signal according to the switch timing signal and having a dv/dt phase and a di/dt phase. The drive signal has a profile during the di/dt phase that is adjusted in response to the device temperature, and the drive signal has a profile during the dv/dt phase that is not adjusted in response to the device temperature.

Abstract: An electronic lock with power failure control circuit includes a lock mechanism having a latchbolt movable between extended and retracted positions and an electrically powered lock actuator to lock and unlock the latchbolt. The power failure control circuit includes a microcontroller and the lock is connected to a primary power source and an auxiliary power source, preferably supercapacitors and charger that can be turned on by the microcontroller and off when the charger signals a full charge. A power monitor circuit detects low voltage on the primary power supply and sets a power failure interrupt causing the microcontroller to execute power failure instructions that control the actuator so that the lock is placed into a desired locked or unlocked final state during the power failure. Upon detection of the return of good power, the system resets the lock.

Abstract: A control chip for memory power sequence including input pins, a control circuit and output pins is provided. The control chip is compatible with a plurality of processor platforms. The input pins are configured to receive control signals corresponding to each of the processor platforms. The control circuit is configured to determine a selected processor platform among the processor platforms in which the control chip for memory power sequence is operated, and generate corresponding power switching signals according to the control signals of the selected processor platform. The output pins are configured to output the corresponding power switching signals to control a power sequence of a memory on the selected processor platform.

Abstract: A circuit includes a pulse generator coupled to a switch mode power supply. The switch mode power supply includes a switching component configured for transferring a charge to an energy storage component in response to pulses provided by the pulse generator. A pulse counter is coupled to the pulse generator or the switching component and configured to count pulses over a time period and thereby generate a pulse count. A converter coupled to the pulse counter is configured to generate a power measurement for the time period based on the pulse count. If the switch mode power supply has different modes of operation, a different counter may be used for each mode.

Abstract: An inverter based on a compound semiconductor uses a depletion mode transistor as the pull-up device, and a current source to bias the pull-up device. The current source is electrically coupled to a source terminal of the pull-up device. As a result, the current source continues to conduct current through the pull-up device, whether the inverter output is high or low, to ensure rapid response of the inverter.

Abstract: Disclosed herein is a power supply circuit for a gate driver. The power supply circuit for the gate driver includes a negative voltage generator configured to generate a negative voltage by receiving an input voltage, wherein the negative voltage generator includes a tank capacitor configured to be charged by receiving the input voltage through a charge path, a discharge switch configured to form a discharge path when the tank capacitor is discharged, and a negative voltage generation capacitor arranged on the discharge path and configured to generate the negative voltage by storing electric charges discharged from the tank capacitor when the tank capacitor is discharged.

Abstract: The invention provides a voltage regulator with multiple output ranges. The voltage regulator includes a voltage divider that has at least a first resistor and a second resistor. The resistance ratio of the first resistor to the second resistor is 1:(X?1). The input of the regulator is connected to the first resistor, and the output is connected to the second resistor. A voltage source may provide a reference voltage Vref to a connecting point between the first resistor and the second resistor. At least one working circuit is connected to the output to provide the output voltage as Vout=Vin?X(Vin?Vref), wherein Vin is the input voltage. As another option, the at least one working circuit may be deactivated and the output may be coupled to ground.

Abstract: An electronic open-circuit current measuring circuit is configured to measure a current delivered between a current source and a load during an open circuit condition. The electronic open-circuit current measuring circuit includes an electronic voltage drop component electrically connected between a first buffer output and an electrical voltage difference calculating circuit. The voltage drop component is configured to reduce a first voltage level of the first buffered output voltage below a second voltage level of the second buffered output voltage in response to an open circuit condition.

Abstract: A power supply for an electronic circuit enables a low effort retention mode. During a normal mode a circuit module is supplied a first voltage sufficient for a controlled circuit to operate. During the low effort retention mode the circuit module is supplied with a second voltage lower than the first voltage. The second voltage is sufficient for flop-flops to retain their state but not sufficient to guarantee proper circuit operation. The second voltage is produced by a voltage drop (droop) from the first voltage. The preferred embodiment includes a System On Chip and one external voltage regulator and an on-chip droop circuit for each circuit module.

Abstract: A proportional-to-absolute-temperature (“PTAT”) circuit includes a bias component; first, second, third, and fourth transistors; an output transistor; and a first resistive component. A first terminal of the bias component is coupled to a voltage supply node. The first and second transistors are connected to a second terminal of the bias component. The third and fourth transistors have different current densities. The first transistor is coupled to the third transistor. The second transistor is coupled to the fourth transistor. The fourth transistor and the first resistive component are coupled to a voltage common node. The output transistor has a control terminal coupled to the second and fourth transistors, a first current terminal connected to an output node, and a second current terminal coupled to the third transistor and the first resistive component. The PTAT circuit is configured to generate at least a portion of a PTAT current at the output node.

Abstract: A circuit including: a three-level buck converter having: a plurality of input switches and an inductor configured to receive a voltage from the plurality of input switches, the plurality of input switches coupled with a first capacitor and configured to charge and discharge the first capacitor; a second capacitor at an output of the buck converter; and a switched capacitor at an input node of the inductor, wherein the switched capacitor is smaller than either the first capacitor or the second capacitor.

Abstract: A voltage generating apparatus according to an embodiment of the present invention includes a voltage regulator determining a pass voltage at a pass node by comparing an output voltage at an output node with a reference voltage, and generating the output voltage by transferring an external power supply voltage to the output node in response to the pass voltage at the pass node, and a voltage stabilizer controlling a first current flowing from the pass node and a second current flowing from the output node in response to the output voltage.

Abstract: According to one embodiment, a rectifying circuit includes a transistor, a rectifying element and a resistor. The transistor includes a control electrode, a first electrode and a second electrode. The rectifying element includes an anode electrode and a cathode electrode. The cathode electrode is electrically connected to the first electrode. The resistor includes one end and one other end. The One end of the resistor is electrically connected to the control electrode. The one other end of the resistor is electrically connected to the anode electrode.

Abstract: A power supply circuit and a display device are provided. The power supply circuit includes: a load, a DC power supply; a DC booster circuit; a load feedback circuit configured to generate a converted voltage in accordance with the current passing through the load, integrate the converted voltage to generate an integrated voltage and generate a first triggering signal in accordance with the integrated voltage; and a control circuit configured to generate a second triggering signal in according with the boosted voltage, a DC power supply voltage and a reference voltage, generate a switching signal for controlling the operation of the DC booster circuit in accordance with the first triggering signal and the second triggering signal, and output the switching signal to the DC booster circuit.

Abstract: An electronic circuit for a power tool includes a plurality of high-side and low-side switches connected in series between terminals of a power source and coupled to a load, a bootstrap circuit comprising a plurality of bootstrap capacitors arranged to provide sufficient amount of drive voltage to turn ON and OFF the plurality of high-side switches, and a control unit configured to turn ON and OFF the plurality of low-side switches in succession to sequentially charge the bootstrap capacitors.

Abstract: A stacked semiconductor device includes a first pair of vertically stacked self-aligned nanowires, a second pair of vertically stacked self-aligned nanowires, and a gate upon a semiconductor substrate, the gate surrounding portions of the first pair of vertically stacked self-aligned nanowires and the second pair of vertically stacked self-aligned nanowires. First epitaxy may merge the first pair of vertically stacked self-aligned nanowires and second epitaxy may merge second pair of vertically stacked self-aligned nanowires. The stacked semiconductor device may be fabricated by forming a lattice-fin upon the semiconductor substrate and the gate surrounding a portion of the lattice-fin. The vertically stacked self-aligned nanowires may be formed by selectively removing a plurality of layers from the lattice-fin.

Abstract: A DC conversion circuit in the disclosure includes a buck-boost converter and a resonant stage circuit. The buck-boost converter has two input ends, a negative output end and a positive output end. The buck-boost converter receives a first DC signal via its two input ends, and outputs a second DC signal via its two output ends. The resonant stage circuit has two input ends and two output ends. The resonant stage circuit receives the second DC signal via its two input ends, converts the second DC signal into energy for power charging, and outputs the energy to a load via its two output ends. Then, the resonant stage circuit converts the energy, which is used for power charging, to form a negative voltage by a resonance effect, and outputs the energy to the load via its two output ends.

Abstract: A protection and attenuation circuit for sensitive AC loads is described. The circuit provides AC power protection and attenuation utilizing high-efficiency switch-mode techniques to attenuate an AC power signal by incorporating a bidirectional, transistorized switch driven from a pulse width modulation signal, PWM. The circuit monitors characteristics of the AC power signal driving a known load and characteristics of the load or other elements and determines the duty cycle of the pulse width modulated signal, PWM, based upon the duration and amplitude of the over-voltage, over-current, over-limit or other event.

Abstract: Disclosed are compensation circuits for a switching power supply. In one embodiment, a compensation circuit can include: (i) a transconductance amplifier configured to receive a reference signal and a feedback signal, and to generate an amplifier output signal according to a difference between the reference signal and the feedback signal; (ii) a switching circuit configured to receive the amplifier output signal, where the switching circuit is controllable by a control signal from a switch control circuit; and (iii) a charging circuit coupled to the switching circuit, where the charging circuit is configured to be charged by the amplifier output signal in response to the control signal, and to generate a compensation signal therefrom.

Abstract: Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nanowire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor.

Abstract: A voltage balancing circuit includes (n?1)-number of voltage stabilization circuits configured between k-th reference nodes of n-number of groups of resistances and k-th output nodes of the n-number of groups of main circuit capacitors respectively where 2?k?n. The k-th voltage stabilization circuit is configured in such a manner that the first transistor is connected via a first resistance to a (k?a)-th output node serving as the source node and the second transistor is connected via a second resistance further connected to a (k+b)-th output node serving as the destination node, where 2?k?n, 1?a?k?1 and 1?b?n+1?k.

Abstract: The present invention provides a buck converter with single stage. The buck converter includes a buck device, a semiconductor component coupled to the buck device, a first resonance circuit coupled to the semiconductor component for adjusting operation time constant, and a second resonance circuit coupled to the first resonance circuit for suppressing ripple. The present invention controls the actuation time of circuit architecture change through LC resonance circuit timing means, automatically changes circuit architecture without active element, is balanced automatically without control energy, and simplifies circuit design. The present invention is characteristic of negative voltage source, which overcomes problems of load voltage potential barrier, and realizes a circuit design of sharing the energy storage and the filtering elements, so as to achieve fast input response, low output ripple and long service life.

Abstract: In some embodiments, a normally on high voltage switch device (“normally on switch device”) incorporates a trench gate terminal and buried doped gate region. In other embodiments, a surface gate controlled normally on high voltage switch device is formed with trench structures and incorporates a surface channel controlled by a surface gate electrode. The surface gate controlled normally on switch device may further incorporate a trench gate electrode and a buried doped gate region to deplete the conducting channel to aid in the turning off of the normally on switch device. The normally on switch devices thus constructed can be readily integrated with MOSFET devices and formed using existing high voltage MOSFET fabrication technologies.

Abstract: The present invention relates to reference voltage regulating methods and circuits for a constant current driver. In one embodiment, a method can include: setting a reference voltage circuit matching with a current output channel of a constant current source; setting a first resistor of the reference voltage circuit to follow an ideal equivalent resistor of the current output channel, and maintaining a proportion of the first resistor and the ideal equivalent resistor to be no less than a predetermined value M; setting a first current of the reference voltage circuit to follow an ideal output current of the current output channel, and maintaining a proportion of the first current and the ideal output current to be no less than 1/M; and setting a product of the first current and the first resistor to be a reference voltage of the reference voltage circuit.

Abstract: In one implementation, a modular power converter having a reduced switching loss includes a package, a field-effect transistor (FET) including a gate terminal, a drain terminal, and a source terminal, and fabricated on a semiconductor die situated inside the package, and a driver circuit inside the package. The driver circuit is configured to drive the gate terminal of the FET. The driver circuit is further configured to sample a drain-to-source voltage (VDS) of the FET directly from the drain terminal and the source terminal, thereby enabling the reduced switching loss.

Abstract: An apparatus may be provided. The apparatus may comprise a first circuit portion, a second circuit portion, and a third circuit portion. The first circuit portion may comprise a voltage supply having an input voltage level (Vin) and a first switch. The second circuit portion may comprise a plurality of parallel paths. The third circuit portion may comprise a second switch and a third switch. The plurality of parallel paths may supply a portion of the input voltage level when the first switch is open, the second switch is closed, and the third switch is open.

Abstract: A DC-DC converter includes a voltage conversion circuit boosting a voltage of a DC power supply and supplying the voltage to a load, a bypass circuit provided in parallel to the voltage conversion circuit, a drive circuit turning on and off a switching element of the bypass circuit, and a controller outputting a control signal for controlling the voltage conversion circuit and the drive circuit. A diode is connected in parallel to the switching element so as to be oriented toward a forward direction with respect to the DC power supply. A temperature detector of the drive circuit detects temperature of the diode. The drive circuit maintains the switching element in the on state irrespective of the control signal of the controller when the temperature detector detects a temperature greater than or equal to a predetermined value.

Abstract: A power control system includes a first switch configured to receive electrical power from a power source and selectably provide the electrical power to a load. A current limiter is intermediate the first switch and the load. A second switch is also configured to receive electrical power from the power source and selectably provide electrical power to the load. The power control system includes a soft-start operating mode wherein the first switch is activated to provide the electrical power to the load, current provided to the load being limited by the current limiter. The second switch is also activated to provide the electrical power to the load, the second switch being activated a predetermined period of time after activation of the first switch. The first and second switches are also deactivated while the voltage of the power source exceeds a predetermined level.

Abstract: A low voltage bandgap reference circuit includes a positive temperature coefficient circuit unit, a negative temperature coefficient circuit unit and a load unit, wherein the positive temperature coefficient circuit unit comprises a first differential operational amplifier, a first, second and third transistor, a first resistor, a first and second diode, and the negative temperature coefficient circuit unit includes a second differential operational amplifier, a fourth, fifth and sixth transistor, a second resistor and a third diode. The low voltage bandgap reference circuit provides a current having a positive temperature coefficient characteristics and a current having a negative temperature coefficient characteristics to flow through the load in order to generate a stable reference voltage less affected by the temperature. Therefore, it avoids the problems of the low voltage bandgap reference circuit that can not be activated at low voltage.

Abstract: A matrix converter includes: a power convertor that includes a plurality of bidirectional switches configured to control a conducting direction using a plurality of switching elements; a command generator configured to generate a control command for a PWM control on the plurality of switching elements; and a commutation controller configured to perform a commutation control on the plurality of bidirectional switches in a case where the control command changes. In a case where the control command changes during execution of the commutation control, the commutation controller executes a handover step for handover to a next commutation control and then executes the next commutation control from a step in a course of the next commutation control.