Abstract: A reference voltage generation circuit of the disclosure includes a first amplifier circuit and a second amplifier circuit. The first amplifier circuit includes a first input stage including two npn transistors or two NMOS transistors having base terminals or gate terminals to which a variable voltage and a predetermined lower limit voltage are inputted. A first output stage includes a pnp transistor or a PMOS transistor having an emitter terminal or a source terminal connected to an output terminal of a reference voltage. A first amplifier stage controls the first output stage for equalizing the higher one of the variable voltage and the lower limit voltage with the reference voltage.

Abstract: The present application discusses low voltage band-gap voltage reference circuit and methods. In an example the circuit can include a current mirror, an operational amplifier adopting an N-Metal-Oxide-Semiconductor (NMOS) input pair structure, a band-gap output circuit, an adaptive adjustment circuit; and two branches of Bipolar Junction Transistor (BJT). The current mirror can be configured to receive an output signal of the operational amplifier and to provide a current to the two branches of BJT. The operational amplifier can be configured to differentially input voltages at the upper ends of the two branches of BJT, to generate the output signal to the current mirror, and to equalize the voltages at the upper ends of the two branches of BJT using a deep negative feedback.

Abstract: A bandgap reference circuit including two sets of bipolar junction transistors (BJTs). A first set of two or more BJTs configured to electrically connect in a parallel arrangement. The first set of BJTs is configured to produce a first proportional to absolute temperature (PTAT) signal. A second set of two or more BJTs configured to electrically connect in a parallel arrangement. The second set of BJTs is configured to produce a second PTAT signal. A circuitry configured to electrically connect to the first set of BJTs and the second set of BJTs. The circuitry is configured to combine the first PTAT signal and the second PTAT signal to produce a reference voltage.

Abstract: A method includes generating a first current, wherein the first current flows through a first resistor and a first bipolar transistor. A first end of the first resistor is serially connected to an emitter-collector path of the first bipolar transistor, and a second end of the resistor is connected to an input of an operational amplifier. A second current is generated to flow through a second resistor that is connected to the input of the operational amplifier. An emitter of a second bipolar transistor is connected to a base of the first bipolar transistor, wherein a base and a collector of the second bipolar transistor are connected to VSS. The first and the second currents are added to generate a third current, which is mirrored to generate a fourth current proportional to the third current. The fourth current is conducted through a third resistor to generate an output reference voltage.

Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

Abstract: A start-up circuit for activating a bandgap voltage generation circuit is disclosed. The bandgap voltage generation circuit includes a bandgap input end, a first bandgap output end and a second bandgap output end. The start-up circuit includes a comparator having a first input end coupled to the first bandgap output end, a second input end coupled to the second bandgap output end, and an output end for outputting an output voltage, a first transistor including a gate coupled to the bandgap input end, a first source/drain coupled to a first system voltage, where a voltage of the gate is generated according to the output voltage, and a first resistor having an end coupled to a second source/drain of the first transistor, another end coupled to a second system voltage.

Abstract: This document discusses, among other things, apparatus and methods configured to accurately identify accessories coupled to mobile electronic devices over a wide range of temperature, In an example, an apparatus can include a reference voltage generator configured to provide a reference voltage, a comparator configured to compare the reference voltage to a voltage across an accessory-resistor, a current supply configured to be coupled to the accessory resistor and to provide the voltage to the comparator using the accessory resistor. The current supply can include a first sense resistor having a first temperature dependency and a second sense resistor having a second temperature dependency. In an example, the second temperature dependency can be configured to compensate for at least a portion of the first temperature dependency. In an example, at least one of the first or second temperature dependencies can be configured to control a temperature dependency of the apparatus.

Abstract: A start-up circuit in a switch-mode power converter that employs a Zener diode to provide a reference voltage to reduce the power consumption and the size of the start-up circuit. The start-up circuit also includes a coarse current source and a coarse reference voltage signal generator for producing current and reference voltage for initial startup operation of a bandgap circuit. The reference signal and current from coarse current source and the reference voltage signal generator are subject to large process, voltage and temperature (PVT) variations or susceptible to noise from the power supply, and hence, these signals are used temporarily during start-up and replaced with signals from higher performance components. After bandgap circuit becomes operational, the start-up receives voltage reference signal from the bandgap circuit to more accurately detect undervoltage lockout conditions.

Abstract: A semiconductor device including an internal voltage generator circuit that provides an internal voltage having a different level depending on the operation speed is provided. The semiconductor device includes an internal voltage generator circuit configured to receive operation speed information to generate an internal voltage having a different level depending on the operation speed; and an internal circuit operated using the internal voltage.

Abstract: A reference voltage generator generates a reference voltage having a stable voltage level insensitive to a temperature variation. A reference voltage generator includes a current generating unit configured to generate a reference current proportional to temperature increase, a voltage adjusting unit configured to adjust a reference voltage corresponding to a current level of the reference current, and a start-up driving unit configured to drive and amplify the reference voltage while the voltage adjusting unit operates.

Abstract: A voltage regulator includes a driver transistor, a feedback voltage generator, a reference voltage generator, a first differential amplifier, and a differential gain controller. The driver transistor is connected between input and output terminals to conduct a current therethrough according to a control signal applied to a gate terminal thereof. The feedback voltage generator is connected to the output terminal to generate a feedback voltage. The reference voltage generator generates a reference voltage. The first differential amplifier has an output thereof connected to the gate terminal of the driver transistor, and a pair of differential inputs thereof connected to the feedback voltage generator and the reference voltage generator, respectively, to generate the control signal at the output thereof. The differential gain controller is connected to the output of the first differential amplifier to control the differential gain according to a difference between the input and output voltages.

Abstract: The present invention discloses a circuit for generating a dual-mode proportional to absolute temperature (PTAT) current. The circuit includes a voltage stabilizing circuit to provide a voltage reference, and a load current control circuit comprising a first transistor to provide a first load current based on the voltage reference, a second transistor to provide a second load current based on the voltage reference, a first switch to control whether to allow the first load current to flow therethrough in response to different predetermined temperatures, and a second switch to control whether to allow the second load current to flow therethrough in response to the different predetermined temperatures. A resultant current resulting from at least one of the first load current or the second load current has different current magnitudes at the different predetermined temperatures.

Abstract: A temperature corrected voltage bandgap circuit is provided. The circuit includes first and second diode connected transistors. A first switched compare circuit is coupled to the one transistor to inject or remove a first current into or from the transistor. The first current is selected to correct for curvature in the output voltage of the bandgap circuit at one of hotter or colder temperatures.

Abstract: An improved reference voltage (Vref) generator useable, for example, in sensing data on single-ended channels is disclosed. The Vref generator can be placed on the integrated circuit containing the receivers, or may be placed off chip. In one embodiment, the Vref generator comprises an adjustable-resistance voltage divider in combination with a current source. The voltage divider is referenced to I/O power supplies Vddq and Vssq, with Vref being generated at a node intervening between the adjustable resistances of the voltage divider. The current source injects a current into the Vref node and into a non-varying Thevenin equivalent resistance formed of the same resistors used in the voltage divider. So constructed, the voltage generated equals the sum of two terms: a first term comprising the slope between Vref and Vddq, and a second term comprising a Vref offset.

Abstract: An improved voltage reference generator is provided. The voltage reference generator comprises: a first transistor having a gate electrode biased to place the first transistor in a weak inversion mode; and a second transistor connected in series with said first transistor and having a gate electrode biased to place the second transistor in a weak inversion mode, where the threshold voltage of the first transistor is smaller than the threshold voltage of the second transistor and the gate electrode of the second transistor is electrically coupled to a drain electrode of the second transistor and the source electrode of the first transistor to form an output for a reference voltage.

Abstract: A bandgap circuit includes a bias current generating circuit and a complementary start-up circuit. The bias current generating circuit includes a first node and a second node and is arranged to generate a bias current in response to a voltage provided at the first node or a voltage provided at the second node. The complementary start-up circuit is arranged to start-up the bias current generating circuit and includes a first start-up circuit coupled to the first node and a second start-up circuit coupled to the second node. The first and second start-up circuits operate complementarily, so that the second start-up circuit provides the voltage to the second node when the first start-up circuit is unable to provide the voltage to the first node, and the first start-up circuit provides the voltage to the first node when the second start-up circuit is unable to provide the voltage to the second node.

Abstract: A reference voltage supply circuit is provided. The reference voltage supply circuit includes a first amplifier for amplifying a first input voltage and a fed back first reference voltage, a second amplifier for amplifying a second input voltage and a fed back second reference voltage, a reference voltage generator for generating the first reference voltage and the second reference voltage according to output signals of the first and second amplifiers and feeding the first and second reference voltages back to the first and second amplifiers, and a glitch remover turned on/off according to an input pulse signal to conduct or cut off current flowing between a power supply terminal and the ground.

Abstract: Disclosed herein are a constant voltage generating circuit and a constant voltage generating method. According to an embodiment of the present invention, the constant voltage generating circuit includes a voltage distribution unit performing voltage drop on a variable input power, a reference voltage and register bit generation unit outputting a band gap reference voltage and register bit, a comparison control unit comparing an input voltage dropped in the voltage distribution unit and the band gap reference voltage output from the reference voltage and register bit generation unit, and controlling the reference voltage and register bit generation unit or a constant voltage generation unit in accordance with the compared result, and a constant voltage generation unit receiving the variable input power by an operation of a switch corresponding to the register bit to thereby output a constant voltage, in accordance with the control of the comparison control unit.

Abstract: Provided is a voltage reference circuit which is able to obtain high PSRR without a variation in power-supply voltage and an influence of noise. A voltage reference circuit for performing voltage-current conversion on forward voltages of PN junction elements and on a difference therebetween to generate a voltage so as not to depend on a temperature is constituted by an amplifier for controlling a temperature characteristic of a voltage of an output terminal, a source follower circuit for supplying a power to the amplifier, and a PMOS transistor which is controlled by the amplifier and which controls a current to flow into the PN junction elements.

Abstract: A two-wire load control device (such as, a dimmer switch) is operable to control the amount of power delivered from an AC power source to an electrical load (such as, a high-efficiency lighting load) and has substantially no minimum load requirement. The dimmer switch includes a bidirectional semiconductor switch, which is operable to be rendered conductive each half-cycle and to remain conductive independent of the magnitude of a load current conducted through semiconductor switch. The dimmer switch comprises a control circuit that conducts a control current through the load in order to generate a gate drive signal for rendering the bidirectional semiconductor switch conductive and non-conductive each half-cycle. The control circuit may provide a constant gate drive to the bidirectional semiconductor switch after the bidirectional semiconductor switch is rendered conductive each half-cycle.

Abstract: A constant current circuit includes a depletion type MOS transistor, a first current mirror circuit, and a second current mirror circuit. The first and second current mirror circuits each include first and second MOS transistors where a gate of the first and second MOS transistors is connected to a drain of the first MOS transistor. A third MOS transistor has a gate connected to one terminal of a resistor and to the drain of the first MOS transistor of the first current mirror circuit, a source connected to a ground terminal, and a drain connected to an output terminal of the second current mirror circuit.

Abstract: A bandgap reference circuit is compensated for temperature dependent curvature in its output. A voltage across a diode with a fixed current is subtracted from a voltage across a diode with a proportional to absolute temperature (PTAT) current. The resultant voltage is then magnified and added to a PTAT voltage and a diode's voltage that has a complementary-to-absolute temperature (CTAT) characteristic, resulting in a curvature corrected bandgap voltage.

Abstract: A band-gap reference circuit is compensated for temperature dependent curvature in its output. A voltage across a diode with a fixed current is subtracted from a voltage across a diode with a proportional to absolute temperature (PTAT) current. The resultant voltage is then magnified and added to a PTAT voltage and a diode's voltage that has a complementary-to-absolute temperature (CTAT) characteristic, resulting in a curvature corrected hand-gap voltage. This allows for the band-gap reference circuit to be trimmed at a single temperature. This allows the circuit to be made with only a single trimmable parameter, which, in the exemplary circuits, is a resistance value.

Abstract: A band gap reference circuit includes an output circuit configured to output a reference voltage based on a reference current generated by a voltage difference between a forward voltage of a PN junction of a first semiconductor device and a forward voltage of a PN junction of a second semiconductor device, and a adder/subtractor circuit configured to add or subtract a correction current with respect to the reference current.

Abstract: A bandgap reference circuit is compensated for temperature dependent curvature in its output. A voltage across a diode with a fixed current is subtracted from a voltage across a diode with a proportional to absolute temperature (PTAT) current. The resultant voltage is then magnified and added to a PTAT voltage and a diode's voltage that has a complementary-to-absolute temperature (CTAT) characteristic, resulting in a curvature corrected bandgap voltage.

Abstract: A constant current flowing through a first depletion transistor whose gate and source are connected to each other is caused to flow through a second depletion transistor having the same threshold as the first depletion transistor, to thereby generate a first voltage between a gate and a source of the second depletion transistor. The constant current of the first depletion transistor and a constant current flowing through a third depletion transistor whose gate and source are connected to each other are caused to flow through a fourth depletion transistor. A threshold of the fourth depletion transistor is the same as that of the third depletion transistor but different from that of the first depletion transistor, and hence a second voltage is generated between a gate and a source of the fourth depletion transistor. A reference voltage is generated based on a voltage difference between the first and second voltages.

Abstract: An electronic reference-signal generation system includes a supply invariant bandgap reference system that generates one or more bandgap reference signals that are substantially unaffected by bulk error currents. In at least one embodiment, the bandgap reference generates a substantially invariant bandgap reference signals for a range of direct current (DC) supply voltages. Additionally, in at least one embodiment, the bandgap reference system provides substantially invariant bandgap reference signals when the supply voltage varies due to alternating current (AC) voltages. In at least one embodiment, the bandgap reference system generates a bandgap reference voltage VBG, a “proportional to absolute temperature” (PTAT) current (“iPTAT”) and a “zero dependency on absolute temperature” (ZTAT) current (“iZTAT”) that are substantially unaffected by variations in the supply voltage and unaffected by a bulk error current.

Abstract: An adjustable shunt regulator circuit has two current paths in parallel, with each current path having a bipolar transistor therein with the bases of the bipolar transistors of the two current paths connected in common. One of the current paths has a high impedance node. A MOS transistor has a gate connected to the high impedance node, and a source and a drain. A resistor divide circuit is connected in parallel to the source and drain of the MOS transistor and provides the output of the regulator circuit. The resistor divide circuit has a first resistor connected in series with a second resistor at a first node. A feedback connects the first node to the bases of the bipolar transistors connected in common of the two current paths.

Abstract: A system for uniform power regulation of an integrated circuit is disclosed. In each of a plurality of regions, the system includes a comparison circuit having a first input coupled to receive a reference voltage and a second input coupled to receive a feedback voltage. The comparison circuit provides a gating voltage to a driver circuit that is coupled to a first supply voltage. The driver circuit is configured to provide a regulated voltage responsive to the gating voltage. A feedback adjustment circuit is configured to trim the regulated voltage by a region-specific trim value and output the trimmed regulated voltage as the feedback voltage on the output.

Abstract: An integrated circuit device has a primary voltage regulator and an ultra-low power secondary voltage regulator. The ultra-low power secondary voltage regulator supplies voltage to certain circuits used for providing data retention and dynamic operation, e.g., a real time clock and calendar (RTCC) when the integrated circuit device is in a low power sleep mode. The primary voltage regulator provides power to these same certain circuits when the integrated circuit is in an operational mode.

Abstract: An initial voltage generation circuit includes a reference voltage generator, a reference voltage selector, at least one initial voltage level regulator, and a plurality of stabilization capacitors. The reference voltage generator generates a plurality of reference voltage candidate groups. The reference voltage selector includes a plurality of selection switch groups and a plurality of switch control circuits. Each selection switch group includes a plurality of parallel switches. Each switch control circuit corresponds to a selection switch group for generating a switch signal to control the selection switch group to output a reference voltage candidate of a corresponding reference voltage candidate group. Each initial voltage level regulator generates an inner reference voltage according to a power-up signal, and a stabilization capacitor corresponding to the initial voltage level regulator is used for stabilizing the inner reference voltage.

Abstract: A semiconductor device of the present invention includes an output transistor connected between a power supply terminal and an output terminal; a detection transistor generating a detection current that is proportional to a current flowing through the output transistor; a detection voltage generation unit generating a detection voltage based on a detection current; a protection transistor drawing a current from a control terminal of the output transistor to the output terminal according to the detection voltage; and a limited current generation circuit that generates a limited current that is obtained by converting a limit setting current that sets a current flowing through the output transistor in a protection state according to a variation of a threshold voltage of the protection transistor and a variation of the detection voltage with respect to the detection current, and supplies the limited current to a first terminal of the protection transistor.

Abstract: A circuit including a first circuit, a second circuit, and a calibration circuit. The first circuit is configured to generate a first reference voltage potential. The second circuit is configured to generate a second reference voltage potential based on a calibration signal. The calibration circuit is configured to generate the calibration signal, to adjust the second reference voltage potential, based on the first reference voltage potential and the second reference voltage potential. The calibration circuit includes a comparing circuit configured to compare the first reference voltage potential and the second reference voltage potential, and a counter configured to increment a counter value based on the comparison of the first reference voltage potential and the second reference voltage potential and generate the calibration signal based on the counter value.

Abstract: A semiconductor integrated circuit includes constant current circuit, starter circuit and power supply start-up circuit. In the constant current circuit, first current mirror circuit includes first and second transistors, and second current mirror circuit includes third and fourth transistors that are connected to first and second nodes. In the starter circuit, a potential of first node controls sixth transistor, seventh transistor is connected to third node, gate electrode of the seventh transistor is at ground potential, a capacitance element is connected to fourth node, and a potential of fourth node controls fifth transistor, which supplies start-up current to the constant current circuit via second node. In the power supply start-up circuit, source electrode of eighth transistor is fixed at power supply voltage, gate electrode is at ground potential, and drain electrode supplies power to the other circuits.

Abstract: Voltage generators may generate a level of a high target voltage with respect to a low external power supply voltage. A reference voltage generator includes a clamp regulator which is driven by a first power supply voltage supplied from an external source and receives a first voltage to generate a clamp voltage, and a level amplifier which is driven by a second power supply voltage that is higher than the first power supply voltage and receives the clamp voltage to generate a reference voltage. The clamp voltage may be set to have a voltage level which results in a successful restore operation with respect to a memory cell array in a dynamic random access memory (DRAM).

Abstract: An internal voltage generating circuit includes a drive signal generating unit, a drive signal controlling unit, and a driving unit. The drive signal generating unit is configured to compare an internal voltage with first and second reference voltages and generate a first pull-up drive signal and a first pull-down drive signal. The drive signal controlling unit is configured to buffer the first pull-up drive signal and the first pull-down drive signal and generate a second pull-up drive signal and a second pull-down drive signal, wherein the second pull-up drive signal and the second pull-down drive signal are deactivated when the first pull-up drive signal and the first pull-down drive signal are activated. The driving unit is configured to drive the internal voltage in response to the second pull-up drive signal and the second pull-down drive signal.

Abstract: An electronic circuit includes a switchable circuit domain that operates in a RUN mode and a STANDBY mode and receives a supply current from a core power supply. A power regulator is connected between the core power supply and the switchable circuit domain to regulate the supply current provided to the switchable circuit domain when the electronic circuit is in the RUN mode. A capacitor is connected between the power regulator and ground and is charged by a refresh circuit when the electronic circuit is in the STANDBY mode. The refresh circuit maintains a voltage across the capacitor when the electronic circuit is in the standby mode, which reduces the time for the electronic circuit to transition from the STANDBY mode to the RUN mode.

Abstract: A semiconductor device includes a voltage generating circuit, a first switch, and a charging circuit. The voltage generating circuit generates a voltage for output and has a function to adjust a magnitude of the voltage to be generated. A first switch has a first conduction terminal and a second conduction terminal that are brought into conduction with each other in an ON state, and the first conduction terminal is connected to an output node of the voltage generating circuit via a first line. The charging circuit charges a second line connected to the second conduction terminal of the first switch.

Abstract: Provided is a reference voltage generator having flat temperature characteristics. The reference voltage generator includes: a depletion mode MOS transistor (10) of a first conductivity type, which is connected to function as a current source and allows a constant current to flow; and an enhancement mode MOS transistor (20) of the first conductivity type, which has a diode connection, has a mobility substantially equal to a mobility of the depletion mode MOS transistor (10), and generates a reference voltage (VREF) based on the constant current. The depletion mode NMOS transistor (10) and the enhancement mode NMOS transistor (20) have substantially equal mobilities, and thus have substantially equal temperature characteristics so that the temperature characteristics of the reference voltage (VREF) become flat.

Abstract: Method and system for developing low noise bandgap references. A stacked ?VBE generator is disclosed for generating ?VBE. The stacked ?VBE generator includes an error amplifier configured to generate an output based on an error signal provided by a first stack of the ?VBE generator. The first stack of the ?VBE is coupled to a first sub-circuit and the error amplifier to form a closed loop. The first sub-circuit is coupled to a power supply and ground and configured to provide a source current between the power supply and the ground. The stacked ?VBE generator also includes a second sub-circuit coupled to the output of the error amplifier, the first and second stacks, and the ground, as well as a second stack of the ?VBE generator, which is coupled to the first stack and the second sub-circuit. The ?VBE is measured at outputs of the first and second stacks and equals the sum of individual ?VBEs of the first and second stacks.

Abstract: A gradation voltage generating circuit includes a resistor ladder circuit and a constant current circuit. The resistor ladder circuit has a plurality of resistors. The constant current circuit is electrically connected to the resistor ladder circuit. The constant current circuit is configured to supply a constant current to the resistor ladder circuit such that the resistor ladder circuit produces a plurality of reference potentials that is configured to be directly supplied to a source driver.

Abstract: A voltage reference circuit comprises a plurality of ?VBE cells, each comprising four bipolar junction transistors (BJTs) connected in a cross-quad configuration and arranged to generate a ?VBE voltage. The plurality of ?VBE cells are stacked such that their ?VBE voltages are summed. A last stage is coupled to the summed ?VBE voltages and arranged to generate one or more VBE voltages which are summed with the ?VBE voltages to provide a reference voltage. This arrangement serves to cancel out first-order noise and mismatch associated with the two current sources present in each ?VBE cell, such that the voltage reference circuit provides ultra-low 1/f noise in the bandgap voltage output.

Abstract: A reference voltage circuit for generating a reference voltage to be referred when a pixel signal is digitally converted, includes ramp voltage generating means for generating a ramp voltage which drops from a predetermined initial voltage at a certain gradient, a transistor for forming, together with the ramp voltage generating means, a current mirror circuit, and gain change means for changing a current value of a current flowing from a predetermined power supply via the transistor to change the gradient of the ramp voltage generated by the ramp voltage generating means.

Abstract: The load driving device disclosed in the specification includes a controller to generate a first control signal based on an input signal, a first output transistor to supply an output current to a load according to the first control signal, a first dividing circuit to output a first divided voltage by dividing a voltage across a first primary electrode and a second primary electrode of the first output transistor by a first transistor and a second transistor connected in serial, a first voltage generating circuit to output a first reference voltage, and a first comparator to supply a first over current detection signal to the controller based on the first reference voltage and the first divided voltage.

Abstract: A reference voltage generating circuit with extremely low temperature dependence is provided. The reference voltage generating circuit includes a BGR circuit which generates a bandgap reference voltage; a bandgap current generating circuit which generates a bandgap current according to the bandgap reference voltage; a PTAT current generating circuit which generates a current proportional to the absolute temperature; and a linear approximate correction current generating circuit which compares the current generated by the PTAT current generating circuit and the bandgap current to generate a correction current, and the BGR circuit adds, to the bandgap reference voltage, a correction voltage generated based on the correction current.

Abstract: A voltage generating circuit of semiconductor integrated circuit includes: a voltage controller that detects the level of an external supply voltage and outputs a voltage control signal; a voltage supplier that outputs the external supply voltage or a first internal voltage in response to the voltage control signal; and a first reference voltage generator that is supplied with an output voltage of the voltage supplier and generates a first reference voltage.

Abstract: An embodiment of a circuit includes first and second branches, an amplifier, a compensation circuit, and a bias unit. The first and second branches are respectively operable to generate first and second currents. The amplifier has a first amplifier input node coupled to the first branch, a second amplifier input node coupled to the second branch, an amplifier output node coupled to the first and second branches, and a first compensation node. The compensation unit is operable to provide a first offset-compensation signal to the first compensation node. And the first bias unit is operable to provide first and second bias signals to the first and second input nodes, respectively, such that the amplifier is operable to cause the first current to approximately equal the second current.

Abstract: In accordance with an embodiment, a reference voltage generator includes a first current generator and a second current generator. The first current generator is configured to produce a first current proportional to a current through a first diode connected in series with the first resistance coupled between a first voltage and a second voltage, such that the first current is produced according to a first proportionality constant. The second current generator is configured to produce a second current proportional to a current through a second diode connected in series with the second resistance coupled between the first voltage and the second voltage, such that the second current is produced according to a second proportionality constant. The reference voltage generator further includes a reference resistor coupled to the first and second current generators and to and output of the reference voltage generator.

Abstract: A current calibration method and the associated control circuit are provided. The method includes: providing a predetermined voltage to the differential output for obtaining an accurate current passing through the panel resistor during a calibration procedure and, providing a driving current to the differential output according to the accurate current during a normal operation procedure.

Abstract: A reference potential generation circuit is provided. The reference potential generation circuit includes first to third input terminals, first and second output terminals, a low-pass filter including first to third terminals, and a linear regulator including first to fourth terminals. In the reference potential generation circuit, the first terminal of the low-pass filter is electrically connected to the second input terminal. The second terminal of the low-pass filter is electrically connected to the first input terminal or the third input terminal The third terminal of the low-pass filter is electrically connected to the first terminal of the linear regulator. The second terminal of the linear regulator is electrically connected to the first input terminal and the first output terminal. The third terminal of the linear regulator is electrically connected to the second output terminal. The fourth terminal of the linear regulator is electrically connected to the third input terminal.