Abstract: A high performance field programmable gate array is described with one or more signal processing engines coupled to a programmable logic fabric. Each signal processing engine includes a signal processing unit for performing specifying tasks and a bus-based configurable connection box for routing a bus-based input to a bus-based output. The signal processing unit has a floating point unit (FPU)/multiply accumulate (MAC) for computation and register files for storing information. The programmable logic fabric is coupled to the one or more signal processing engines for routing of information between the signal processing engines.

Abstract: An electrically programmable multiple selectable function integrated circuit module has a plurality of optionally selectable function circuits, which receive and manipulate a plurality of input data signals. The outputs of the plurality of optionally selectable function circuits are either interconnected to each other or connected to a plurality of output connectors to transmit manipulated output data signals to external circuitry. The electrically programmable multiple selectable function integrated circuit module has at least one configuration connector, which may be multiplexed with input control and timing signals, connected to a function configuration circuit to receive electrical configuration signals indicating the activation of a program mode and which of the optionally selectable function circuits are to be elected to manipulate the input data signals.

Abstract: An integrated circuit (IC) includes self-calibrating programmable digital logic circuitry. The IC includes at least one programmable digital logic cell, wherein the first programmable digital logic cell provides (i) a plurality of different accessible circuit configurations or (ii) a voltage level controller. A self-calibration system is provided that includes at least one reference device, a measurement device for measuring at least one electrical performance parameter that can affect a processing speed of the first programmable digital logic cell or at least one parameter that can affect the electrical performance parameter using the reference device to obtain calibration data. A processing device maps the calibration data or a parameter derived therefrom to generate a control signal that is operable to select from the plurality of different accessible circuit configurations or a voltage level output to change the processing speed of the programmable digital logic cell.

Abstract: An ePLX unit includes a logic unit having an SRAM and a MUX, and a switch unit having an SRAM and a TG for establishing wiring connection in the logic unit. When a composite module is set in the first mode, an Add/Flag control unit uses the SRAMs as a data field and a flag field, respectively, to autonomously control the read address of each of the data field and the flag field in accordance with a control flag stored in the flag field. Furthermore, when the composite module is set in the second mode, the Add/Flag control unit writes configuration information into each of the SRAMs to reconfigure a logic circuit. Consequently, the granularity of the circuit configuration can be rendered variable, which allows improvement in flexibility when configuring a function.

Abstract: Methods and systems to improve performance in an Integrated Circuit (IC) are presented. The method includes performing a timing analysis for a circuit design of an IC. The modules in the circuit design use a standard voltage bias by default. In one embodiment, the timing analysis is performed by a circuit design tool. The method then identifies a critical path in the timing analysis, where a signal propagating through the critical path does not meet timing requirements for the circuit design. The method then selects a module of the IC in the critical path to apply a high speed voltage bias to the body of transistors in the module, resulting in a smaller propagation delay thorough the selected module than if the standard voltage bias were applied to the selected module, thus allowing the circuit design to meet the timing requirements.

Abstract: A design structure for a computer-aided design system for generating a functional design model of an integrated circuit design (having nets comprising wires) determines critical parameters for coupling noise between the wires of the nets and acceptable limits for the critical parameters. Further, methods herein include designing a ring oscillator to have stages, each of the stages measuring only one of the critical parameters. This ring oscillator is then included within an integrated circuit design and associated design structure. The embodiments herein produce an integrated circuit according to this integrated circuit design and operate the ring oscillator within the integrated circuit to measure the critical parameters of the integrated circuit and produce test results. These test results are output to determine whether the test results are within the acceptable limits.

Abstract: Power regulator circuitry for programmable memory elements on programmable logic device integrated circuits is provided. The programmable memory elements may each include a storage element formed from cross-coupled inverters and an address transistor. Address drivers may be used to supply address signals to the address transistors. The power regulator circuitry may include an address power supply circuit that produces a time-varying address power supply voltage to the address drivers and storage element power supply circuits that provide time-varying storage element power supply voltages to the cross-coupled inverters in the storage elements. Unity gain buffers may be used to distribute a reference voltage from a bandgap voltage reference to the power supply circuits. The power supply circuits may use voltage dividers and p-channel metal-oxide-semiconductor control transistors.

Abstract: There is provided a method for routing a plurality of signals in a processor array, the processor array comprising a plurality of processor elements interconnected by a network of switches, each signal having a respective source processor element and at least one destination processor element in the processor array, the method comprising (i) identifying a signal from the plurality of unrouted signals to route; (ii) identifying a candidate route from the source processor element to the destination processor element, the candidate route using a first plurality of switches; (iii) evaluating the candidate route by determining whether there are offset values that allow the signal to be routed through the first plurality of switches; and (iv) attempting to route the signal using one of the offset values identified in step (iii).

Abstract: Integrated circuits are provided with circuitry such as multiplexers that can be selectively configured to route different adjustable power supply voltages to different circuit blocks on the integrated circuits. The circuit blocks may contain memory elements that are powered by the power supply voltages and that provide corresponding static output control signals at magnitudes that are determined by the power supply voltages. The control signals from the memory elements may be applied to the gates of transistors in the circuit blocks. Logic on an integrated circuit may be powered at a given power supply voltage level. The memory elements may provide their output signals at overdrive voltage levels that are elevated with respect to the given power supply voltage level. Memory elements associated with circuit blocks that contain critical paths can be overdriven at voltages that are larger than memory elements associated with circuit blocks that contain noncritical paths.

Abstract: A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.

Abstract: A programming interface device for a programmable logic circuit comprises a series of parallel logic block chains each having first and second connection means, the first and second connection means being disposed at opposite ends of each chain. The programming interface device comprises first and second interfacing means for interfacing with the first and second connection means of each logic block chain, respectively and at least one programming circuit, each programming circuit arranged to configure a plurality of serially connected logic blocks. Finally, the programming interface comprises programmable connection means for connecting the connection means of each logic block chain to either the connection means of another logic block chain or directly to one of the at least one programming circuits, such that the parallel logic block chains can be configured in parallel, series or in any combination thereof.

Abstract: A method of configuring an integrated circuit (IC) can include receiving configuration data within a master die of the IC. The IC can include the master die and a slave die. A master segment and a slave segment of the configuration data can be determined. The slave segment of the configuration data can be distributed to the slave die of the IC.

Abstract: Structures and methods to facilitate channel bundling are disclosed. In one embodiment, signal distribution circuitry includes a data path with at least two registers coupled to adjacent sets of data channels in a bundle of data channel sets. In another embodiment, self-switch circuits allow channels in a bundle of channel-sets to switch from bundle-wide signals to locally generated signals after the bundle-wide signals have been synchronously distributed to all channel sets in the bundle. In a particular embodiment, signal distribution circuitry is used to distribute a divided clock signal. In another particular embodiment, signal distribution circuitry is used to distribute enable signals for first-in first-out circuits (“FIFOs”) located in channels of each data channel set in a channel set bundle. In a particular aspect of an embodiment, FIFO read and write operations across a channel set bundle are initiated such that a difference between read and write pointer signals is the same in each channel set.

Abstract: Various techniques are described for high resolution time measurement using a programmable device, such as an FPGA. The timing may be triggered by any event, depending on the applications of use. Once triggering has occurred, a START pulse begins propagating through the FPGA. The pulse is able to propagate through the FPGA in a staggered manner traversing multiple FPGA columns to maximize the amount of time delay that may be achieved while minimizing the overall array size, and thus minimizing the resource utilization, of the FPGA. The FPGA timing delay is calibrated by measuring for the linear and non-linear differences in delay time of each unit circuit forming the staggered delay line path for the timing circuit. The FPGA is able to achieve nanosecond and sub-nanosecond time resolutions and thus may be used in applications such as various time of flight systems.

Abstract: A method and system for providing a logic device are described. The logic device includes a plurality of magnetic input/channel regions, at least one magnetic sensor region, and at least one sensor coupled with the at least one magnetic sensor region. Each of the magnetic input/channel regions is magnetically biased in a first direction. The magnetic sensor region(s) are magnetically biased in a second direction different from the first direction such that at least one domain wall resides in the magnetic input/channel regions if the logic device is in a quiescent state. The sensor(s) output a signal based on a magnetic state of the magnetic sensor region(s). The input/channel regions and the magnetic sensor region(s) are configured such that the domain wall(s) may move into the magnetic sensor region(s) in response to a logic signal being provided to at least a portion of the magnetic input regions.

Abstract: A power supply controller having final test and trim circuitry. In one embodiment, a power supply controller for switched mode power supply includes a selector circuit, a trim circuit, a shutdown circuit and a disable circuit. The trim circuit includes a programmable circuit connection that can be selected by the selector circuit by toggling a voltage on an external terminal such as for example a power supply terminal, a control terminal or a function terminal of the power supply controller. The programmable circuit connection in the trim circuit can be programmed by applying a programming voltage to the external terminal. The shutdown circuit shuts down the power supply controller if the temperature rises above an over temperature threshold voltage. The shutdown circuit includes adjustment circuitry that can be used to test the shutdown circuit. The adjustment circuitry can adjust and reduce the over temperature threshold of the power supply controller.

Abstract: An integrated circuit device such as a structured ASIC includes a mask-programmable portion and a post-fabrication-programmable portion. The mask-programmable portion includes circuitry that is able to read information from the post-fabrication-programmable portion and use that information to affect operation of other componentry of the mask-programmable portion. Signal timing is an example of the kind of operation that may be affected by the above-mentioned information, which may allow post-fabrication timing tuning of the device.

Abstract: The invention relates to an electrical circuit arrangement comprising a plurality of reconfigurable circuit cells, each reconfigurable circuit cell comprising —a plurality of nodes, —a plurality of links connectable to the nodes, —at least one circuit element, wherein the reconfigurable circuit cells are each configured to form either a node or a link of the electrical circuit arrangement.

Abstract: Provided is a cross-point latch and a method of operating the cross-point latch. The cross-point latch includes a signal line, two control lines crossing the signal line, and unipolar switches disposed at crossing points between the signal line and the control lines.

Abstract: Embodiments of the invention provides a method, device, and system for programming an electromigration fuse (eFuse) using a radio frequency (RF) signal. A first aspect of the invention provides a method of testing circuitry on a semiconductor chip, the method comprising: receiving a radio frequency (RF) signal using at least one antenna on the semiconductor chip; powering circuitry on the semiconductor chip using the RF signal; activating a built-in self test (BIST) engine within the circuitry; determining whether a fault exists within the circuitry using the BIST; and programming an electromigration fuse (eFuse) to alter the circuitry in response to a fault being determined to exist.

Abstract: A semiconductor apparatus has a plurality of chips stacked therein, and generation timing of read control signals for controlling read operations of the plurality of stacked chips is controlled such that times after a read command is applied to when data are outputted from respective chips are made to substantially correspond to one another.

Abstract: Various techniques are described for high resolution time measurement using a programmable device, such as an FPGA. The timing may be triggered by any event, depending on the applications of use. Once triggering has occurred, a START pulse begins propagating through the FPGA. The pulse is able to propagate through the FPGA in a staggered manner traversing multiple FPGA columns to maximize the amount of time delay that may be achieved while minimizing the overall array size, and thus minimizing the resource utilization, of the FPGA. The FPGA timing delay is calibrated by measuring for the linear and non-linear differences in delay time of each unit circuit forming the staggered delay line path for the timing circuit. The FPGA achieves nanosecond and sub-nanosecond time resolutions and is used in applications such as various time of flight systems.

Abstract: A mixed signal integrated circuit includes a digital logic array and an analog cell array. Each cell of the analog cell array shares a common architecture and is fully programmable. An analog cell includes mirror NFETs, cascode NFETs, differential pair NFETs, differential pair PFETs, cascode PFETs and mirror PFETs. An analog cell may also include special purpose components, such as low value resistors, high value resistors and PFETs.

Abstract: A high performance field programmable gate array is described with one or more signal processing engines coupled to a programmable logic fabric. Each signal processing engine includes a signal processing unit for performing specifying tasks and a bus-based configurable connection box for routing a bus-based input to a bus-based output. The signal processing unit has a floating point unit (FPU)/multiply accumulate (MAC) for computation and register files for storing information. The programmable logic fabric is coupled to the one or more signal processing engines for routing of information between the signal processing engines.

Abstract: A logic gate 40 according to the present invention has a magnetoresistive element 1, a magnetization state control unit 50 and an output unit 60. The magnetoresistive element 1 has a laminated structure having N (N is an integer not smaller than 3) magnetic layers 10 and N?1 nonmagnetic layers that are alternately laminated. A resistance value R of the magnetoresistive element 1 varies depending on magnetization states of the N magnetic layers 10. The magnetization state control unit 50 sets the respective magnetization states of the N magnetic layers 10 depending on N input data. The output unit 60 outputs an output data that varies depending on the resistance value R of the magnetoresistive element 1.

Abstract: A columnar programmable device (PD) design converted to a columnar application specific integrated circuit-like (ASIC-like) design is described. A user design is instantiated in a PD having a columnar architecture associated with the columnar PD design. The columnar architecture has adjacent columns of circuitry, and one or more of the columns of circuitry as associated with instantiation of the user design in the PD are identified. At least a portion of one or more of the identified columns are swapped with application specific circuitry for implementing all or part of the user design for converting the columnar PD design to the columnar ASIC-like design.

Abstract: There is provided an input/output multiplexer capable of reducing a layout area in designing a device by disposing first and second multiplexers at either side of a specific data input/output (I/O) pad. An apparatus for multiplexing data inputted or outputted to a global input/output (I/O) line includes a first multiplexer for multiplexing the data and supplying a first multiplexed data to the global I/O line and a second multiplexer for multiplexing the first multiplexed data supplied to the global I/O line, wherein the first and second multiplexers are formed at either side of the global I/O line.

Abstract: Provided is a logic gate device capable of performing multiple logic operations by using a single logic gate circuit. The multi-functional logic gate device includes a pull-up switching unit having input switches of a first group being respectively connected to multiple input terminals and selection switches of the first group connected to either a selection terminal or a logically inverted selection terminal, the pull-up switching unit electrically connecting the input switches of the first group in series or in parallel between a power source and an output terminal according to logic levels of the selection terminal and the inverted selection terminal.

Abstract: Disclosed is a method of minimizing clock uncertainty using a multi-level de-skewing technique. The method includes the steps of obtaining a chip wherein at least a portion of the chip has a regular array of buffers on multiple levels, the buffers being driven by first drivers and the first drivers being driven by second drivers; grouping the buffers in a first direction to create clusters with the same number of buffer inputs, wherein if there are not the same number of buffer inputs in each cluster, then adding dummy buffers to the cluster with a deficient number of buffer inputs; wiring outputs of the first drivers together in a second direction, wherein the first and second directions are orthogonal; and wiring outputs of the second together in the second direction.

Abstract: A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.

Abstract: In the electronic circuit device with stacked plural components of the same function, this invention enables to select an arbitrary component among plural components by a control element, without setting pre-determined identification information in each component. By installing a sequential logic circuit in each component, and changing a state of the sequential logic circuit by control data transmitted from the component stacked in a preceding stage or the control element, the state of the controlled component is set to a state that accepts a selection made by the control element.

Abstract: Method and apparatus for processing scalable content having a base layer and at least one enhancement layer is described. In one example, static logic having decoder logic and system monitor logic is provided. Programmable logic having a plurality of reconfigurable slots is also provided. The decoder logic includes a base layer processor for processing the base layer of the scalable content. The system monitor logic is configured to dynamically reconfigure at least one of the plurality of reconfigurable slots with at least one enhancement block for processing the at least one enhancement layer of the scalable content.

Abstract: Some embodiments provide a configurable integrated circuit (IC) comprising multiple deskew circuits for delaying data passage. Each of the deskew circuits comprises a stepwise delay circuit with multiple outputs and an input selection circuit with multiple inputs. Multiple outputs connect to multiple inputs. In some embodiments the configurable IC is a subcycle reconfigurable IC. In some such embodiments each of the deskew circuits further includes a space-time load control circuit for commanding the stepwise delay circuit to load during a selected subcycle. In some embodiments the multiple deskew circuits send data to a trigger circuit. In some such embodiments the trigger circuit triggers a trace buffer to stop recording a data stream. In some such embodiments the trigger circuit triggers the trace buffer to stop after a programmable delay.

Abstract: A multi-chip module (MCM) includes a first die and a second die. The first die supports a plurality of predetermined functions. The second die is coupled to the first die and comprises at least an option pad configured for a bonding option. The first die performs a predetermined function according to a bonding status of the option pad of the second die.

Abstract: A configurable circuit of the present invention includes a plurality of logic blocks (4), and a programmable bus which can program connections of plurality of logic blocks (4). The programmable bus includes a plurality of wires (11—x) arranged for each of signal transmission ranges corresponding to plurality of logic blocks (4), direct wire connection switch (711—x) which can program whether to directly connect or disconnect the wires between the adjacent signal transmission ranges, input selector (30—x) which can program a connection with any one of the plurality of wires, and programmable switch (40—x) which can program whether to make a connection with the wire corresponding to the adjacent signal transmission range for each of the plurality of wires. A plurality of programmable switches (40—x) are arranged for at least one of plurality of logic blocks (4).

Abstract: An antifuse circuit includes a terminal, an antifuse, and a select transistor. The antifuse is coupled to the terminal and has an associated program voltage. The select transistor is coupled to the antifuse and has a gate terminal coupled to receive a first select signal. The select transistor operates in a snapback mode of operation in response to an assertion of the first select signal and the program voltage at the terminal.

Abstract: A device including a PLD with at least one interface logic block connection for passing data between (i) a bus arranged for receiving data from an external processor and (ii) at least one I/O register connected with a JTAG interface of the PLD, wherein said interface logic block includes logic for translating data on the bus into a data format for the I/O register. A processor programmable PLD appliance comprising (a) a programmable PLD having a JTAG programming interface supporting real-time re-programming of the PLD while the PLD functions as programmed; and (b) an I/O register interfacing an I/O register and connected with the JTAG programming interface, wherein a PLD logic design implementation of the I/O register is externally accessible through an interface logic block of the PLD, and wherein the interface logic block includes a PLD path between (i) an external processor interface and (ii) the PLD-implemented I/O register.

Abstract: Integrated circuits are provided that have memory elements. The memory elements may be organized in an array. Data such as programmable logic device configuration data may be loaded into the array using read and write control circuitry. Each memory element may store data using a pair of cross-coupled inverters. Power supply circuitry may be used to power the cross-coupled inverters. A positive power supply signal and a ground power supply signal may be provided to the inverters by the power supply circuitry. Each memory element may have an associated clear transistor. A clear control signal may be asserted to turn on the clear transistor when clearing the memory elements. A given one of the inverters in each memory element may be momentarily weakened with respect to the clear transistor in that memory element by using the power supply circuitry to temporarily elevate the ground power supply signal.

Abstract: A semiconductor integrated circuit device 1 includes a plurality of basic cells 5 each having therein a logic transistor 2 that performs logical operations, and a power switching transistor 3 that can interrupt leakage current when the logic transistor 2 is not operated. The semiconductor integrated circuit device 1 further includes a wiring 6 that connects virtual power nodes 4 as the connection points between the logic transistors 2 and the power switching transistors 3, between individual basic cells 5a and 5b included in a plurality of basic cells 5. Here, a basic cell includes a power switching transistors 3 that can interrupt leakage current when the logic transistors 2 are not operated, in addition to the logic transistors 2. Thereby, switching transistors 3 can be disposed in the optimal positions of the cells 5, and basic cells 5 having a small restriction in disposition and wide scope of application can be provided.

Abstract: Provided is a programmable logic block of a field-programmable gate array (FPGA). The programmable logic block includes a pull-up access transistor connected to a power source, an up-phase-change memory device connected to the pull-up access transistor, a down-phase-change memory device connected to the up-phase-change memory device, an output terminal between the up-phase-change memory device and the down-phase-change memory device, and a pull-down access transistor connected to the down-phase-change memory device and a ground. The resistance values of the up-phase-change memory device and the down-phase-change memory device are individually programmed.

Abstract: A power-up and power-down circuit for an integrated circuit includes a voltage regulator set for a first voltage. A first I/O pad is coupled internally to an input to the voltage regulator and to first internal circuits. The second voltage is externally coupled to the first I/O pad. A second I/O pad is coupled internally to an output of the voltage regulator configured to drive the base of an external transistor. A third I/O pad of the integrated circuit is coupled internally to a reference-voltage input of the voltage regulator. A fourth I/O pad is coupled to a feedback input of the voltage regulator. A fifth I/O pad of the integrated circuit is coupled internally to logic circuitry that controls power-up and power down of the integrated circuit from internal signals including internal signals from a real-time clock circuit disposed on the integrated circuit.

Abstract: A method and system of providing a language interpretation service is disclosed. A language interpretation number, such as an 811 number, can be provided. The language interpretation number can be used to place a telephone call to a language interpretation service for language assistance. A language interpretation telephone call is received at the language interpretation service provider from a caller speaking a first language. The caller places the language interpretation telephone call by dialing the language interpretation number. The caller has at least one business need. The first language is identified so as to provide the customer with an interpreter that can interpret between a first language and a second language. The interpreter can be associated with the language interpretation service provider. The interpreter can telephonically engage an agent representing a business entity that can service the at least one business need of the caller.

Abstract: An integrated circuit with a configurable portion, such as an input/output port, that can be placed in a default configuration prior to actual configuration of the integrated circuit. An external terminal that serves as an output during normal operation is coupled, after power-on of the integrated circuit, to a comparator that senses the voltage level at that external terminal. If the external terminal is at a particular level, a multiplexer is controlled to ignore the state of the normal configuration memory, and to place the configurable input/output port into a default protocol.

Abstract: A method is presented that may be used to provide a Configurable Logic device, which may be Field Programmable with volume flexibility. A method of fabricating an integrated circuit may include the steps of: providing a semiconductor substrate and forming a borderless logic array, and it may also include the step of forming a plurality of antifuse configurable interconnect circuits and/or a plurality of transistors to configure at least one antifuse. The programming transistors may be fabricated over the at least one antifuse.

Abstract: A programmable logic integrated circuit device adapted to enter a low-power mode is described. The integrated circuit device includes a programmable logic block, a first low-power mode control circuit programmed into a portion of the programmable logic block, a second low-power mode control circuit, and a low-power enable input coupled to the first low-power mode control circuit and the second low-power mode control circuit. This arrangement allows the programmable logic integrated circuit device to transition into and out of low-power mode in response to a single signal from system control logic, so that the system control logic can be designed without detailed understanding of the inner workings of the programmable logic integrated circuit device or its programmed design.

Abstract: Modifying a layout of an integrated circuit (IC) based on a function of an interconnect therein and a related circuit and design structure are disclosed. In one embodiment, a method includes identifying a function of an interconnect in the layout from data of the layout embodied in a computer readable medium; and modifying the layout to form another layout that accommodates the function of the interconnect. A design structure embodied in a machine readable medium used in a design process, according to one embodiment, may include a circuit including a high voltage interconnect positioned in a dielectric layer, the high voltage interconnect positioned such that no fill is above or below the high voltage interconnect.

Abstract: A novel conservative gate especially suiting a Quantum Dot Cellular Automata (QCA) majority voter-based design. The input-to-output mapping of the novel conservative QCA (CQCA) gate is: P=A; Q=AB+BC+AC [MV(A,B,C)]; R=A?B+A?C+BC [MV(A?,B,C)], where A, B, C are inputs and P, Q, R are outputs, respectively. A method of transferring information in a quantum-dot cellular automata device is also provided.

Abstract: A power supply controller having final test and trim circuitry. In one embodiment, a power supply controller for switched mode power supply includes a selector circuit, a trim circuit, a shutdown circuit and a disable circuit. The trim circuit includes a programmable circuit connection that can be selected by the selector circuit by toggling a voltage on an external terminal such as for example a power supply terminal, a control terminal or a function terminal of the power supply controller. The programmable circuit connection in the trim circuit can be programmed by applying a programming voltage to the external terminal. The shutdown circuit shuts down the power supply controller if the temperature rises above an over temperature threshold voltage. The shutdown circuit includes adjustment circuitry that can be used to test the shutdown circuit. The adjustment circuitry can adjust and reduce the over temperature threshold of the power supply controller.

Abstract: A generator of synchronization pulses intended for at least two registers, including a first input intended to receive a clock signal and at least one output intended to deliver the pulses on the clock input of said registers, and at least one second input intended to receive a signal for forcing the output, independently from the clock signal, to make said registers transparent.

Abstract: Power regulator circuitry for programmable memory elements on programmable logic device integrated circuits is provided. The programmable memory elements may each include a storage element formed from cross-coupled inverters and an address transistor. Address drivers may be used to supply address signals to the address transistors. The power regulator circuitry may include an address power supply circuit that produces a time-varying address power supply voltage to the address drivers and storage element power supply circuits that provide time-varying storage element power supply voltages to the cross-coupled inverters in the storage elements. Unity gain buffers may be used to distribute a reference voltage from a bandgap voltage reference to the power supply circuits. The power supply circuits may use voltage dividers and p-channel metal-oxide-semiconductor control transistors.