Abstract: A master-slave device communication circuit includes a master device, a bus, and a slave device having a bus switch connected to the master device via the bus, and a status detecting circuit. The status detecting circuit includes a power input terminal and a detecting signal output terminal. A power terminal of the master device is connected to the power input terminal of the status detecting circuit. The detecting signal output terminal is connected to the bus switch and a trigger pin of the master device. When the master device supplies power to the slave device via the power terminal thereof, the detecting signal output terminal transmits a control signal to control the bus switch to turn on the bus and trigger the master device to communicate with the slave device after a delay time.

Abstract: Improvement of quantization errors that arise in a delay line with finite resolution. A direct digital synthesizer (DDS), which contains a numerically controlled oscillator (NCO) and a digital-to-phase converter (DPC), is placed in the feedback loop of a phase locked loop (PLL). The DDS is used as a fractional divider of the voltage controlled oscillator (VCO) frequency, such that the reference frequency of the DDS is made variable. Alignment of the edges provided by the DDS delay line may then be adjusted. Mismatch errors in the DDS delay line are reduced by utilizing independently tunable delay elements.

Abstract: A controllable delay line includes an anti-jitter unit, a dependent current source, a first current mirror, a second current mirror, a regulation capacitor, a compensation capacitor and an output buffer unit. The anti-jitter unit receives a first bias voltage and produces a second bias voltage based on the first bias voltage. When the voltage source used in the controllable delay line has a variation, the second bias voltage varies therewith. The regulation capacitor is used for reducing the variation of the voltage difference between the voltage source and a node voltage of the first current source. The compensation capacitor is used for reducing the influence of a transition of the input signal of the output buffer unit on the node voltage, so as to lower the jitter amount of the output signal of the output buffer unit.

Abstract: A delay line including a sequence of identical delay cells with improved gain and in built duty cycle distortion control and a method thereof is disclosed. Each delay cell of the sequence includes a current source, four transistors, and a load capacitor. A gate of the current source receives a voltage bias that controls a delay of the delay cell. A drain of the first transistor is connected to the drain of the current source. The first and second transistor gates receive an input clock signal. The second transistor drain is connected to the source of the current source. The third transistor gate and the load capacitor are also connected to the drain of the current source. The fourth transistor drain is connected to the third transistor drain. The fourth transistor gate is coupled to an output of a second consecutive delay cell for duty cycle distortion control.

Abstract: An output driver controls impedance using a mode register set. The output driver includes a main driving circuit that outputs and drives a main signal based on a data signal to a predetermined transmission line, an auxiliary driving circuit that outputs and drives an auxiliary signal to the transmission line, and a mode register set. The mode register set generates an impedance control signal group, a driving width control signal group and a delay control signal group. The amount of an auxiliary impedance (SIM), and the driving width and driving time point of an auxiliary signal (XSDR) can be controlled using the impedance control signal group, the driving width control signal group and the delay control signal group. Therefore, in accordance with the output driver of the present invention, the amount of output impedance (OIM), a pre-emphasis width and a pre-emphasis time point can be readily controlled, and the efficiency of the transmission of an output signal to a reception system is improved.

Abstract: The present invention provides a delay circuit in which normal CMOS type inverters and modified inverters added with delay PMOSs on the power supply voltage VDD terminal side are alternately cascade-connected. A correction circuit that supplies a control signal to the gates of the delay PMOSs is provided in association with the delay circuit. The correction circuit comprises a PMOS diode-connected in the forward direction, and resistors that connect the drain of the PMOS to the ground voltage VSS terminal side. The correction circuit outputs the control signal from an internal node provided between the resistors. Thus, when a power supply voltage rises, the voltage of the control signal also rises. Hence, gate-to-source voltages of the delay PMOSs are kept constant, and drain currents remain unchanged and a delay time is kept constant as well.

Abstract: A delay circuit (12) includes a resistor (R1), a capacitor (C), and a discharging circuit (14). The discharging circuit includes a PNP transistor (Q1) and an NPN transistor (Q2). The capacitor has one terminal connected to one terminal of the resistor, and the other terminal connected to ground. The PNP transistor has a base connected to the other terminal of the resistor, a collector, and an emitter connected to a voltage source. The NPN transistor has a base connected to the collector of the PNP transistor, an emitter connected to ground, and a collector connected to the one terminal of the resistor.

Abstract: A delay circuit respectively delays rising and falling edges of an input signal. The delay circuit comprises first and second delay lines, a control circuit, and first and second logic circuits. The first delay line delays the first input signal the first delay time to output the first delay output signal. The second delay line delays the first input signal the second delay time to output the second delay output signal. The control circuit outputs the control signal according to the first input signal. The first logic circuit receives the first delay output signal and outputs the first output signal according to the control signal and the first input signal. The second logic circuit receives the second delay output signal and outputs the second output signal according to the control signal and the first input signal. The first and second delay times are different.

Abstract: An oscillator includes an oscillating block for generating a control signal in response to an enable signal, wherein the control signal is periodically toggled and a feedback block for receiving the control signal to generate the enable signal in response to an oscillator enable signal wherein the enable signal operates so that the control signal is maintained to complete a last cycle period after an inactivation timing of the oscillator enable signal.

Abstract: A time delay logic comprises a first stage with an inverter, a capacitor connected to the input terminal of the inverter, a constant current generator and an electronic switch controlled by an input pulse. The capacitor begins to charge at a predetermined edge of the input pulse and brings the input terminal of the inverter from a first voltage (ground) to the switching threshold voltage of the inverter, so that on the output terminal of the inverter there is obtained a pulse having an edge that, as referred to the predetermined edge of the input pulse, has a delay time that depends on the inverter threshold. The circuit comprises a second stage, coupled with the first, that is a dual circuit of the circuit of the first stage and has an inverter equal to the one of the first stage.

Abstract: A measure control delay includes a measuring delay line and a signal generating delay line, each of which include a plurality of series-connected delay units. A digital signal is applied to an initial delay unit in the measuring delay line and it sequentially propagates through the delay units until a second digital signal is received. These outputs are applied to control inputs to the signal generating delay line to control the number of delay units through which a clock signal propagates before being output from a final delay unit. Each of the delay units in the measuring delay line includes a pair of series connected NOR gates. A NOR gate to which the digital signal is initially applied is coupled to a second NOR gate as a flip-flop so that the output of the NOR gate remains constant after the digital signal has been applied to the measuring delay line.

Abstract: Delay lines include an adjustable delay cell that adjusts a speed at which an input signal to the adjustable delay cell is transmitted through the adjustable delay cell responsive to a control signal. A plurality of set delay cells are coupled in series with the adjustable delay cell that delay transmission through the set delay cells of an input signal to the respective set delay cells an amount that does not vary responsive to the control signal. Delay cells that have an adjustable delay time are also provided.

Abstract: This disclosure relates to a cell-placeable variable-frequency digitally controlled oscillator (DCO) that consumes approximately the same current in a fast process corner as in the case of a slow process corner. By modulating the effective channel length of transistors in inverters, a fast process DCO may be slowed down to a desired frequency at nearly the same current consumption as that of a slow process DCO.

Abstract: A delay circuit comprises a plurality of delay blocks connected in series, and a driving portion adapted to logically combine signals transmitted by the plurality of delay blocks to generate a delay circuit output signal. Each of the plurality of delay blocks delays an output signal from an immediately previous delay block and transmits a resulting delayed output signal to a next delay block when a delay operation is enabled based on a corresponding control signal. However, where the delay operation of a delay block is disabled based on the corresponding control signal, the delay block transmits the output signal of the immediately previous delay block to the driving portion.

Abstract: A clock signal generation system and method to distribute at least one clock signal to a plurality of points on a circuit board using a plurality of digitally programmable delay circuits each of which delays the clock signal by a desired amount so as to synchronize arrival of the clock signal when distributed to each of the plurality of points on the circuit. Each digitally programmable delay circuit comprises a plurality of circuit stages connected in series with each other. Each circuit stage comprises a plurality of transistors of a first type (e.g., P-type) connected in parallel with each other, and a plurality of transistors of a second type (e.g., N-type) connected in parallel with each other. In each circuit stage, one or more of the plurality of transistors of the first type are selected to delay a rising edge, and one or more of the plurality of transistors of a second type are selected to delay a falling edge.

Abstract: A DLL-based programmable clock generator using a threshold-trigger delay element and an edge combiner is proposed. A threshold-trigger delay element with full swing complementary output signals consumes no dc power. It exhibits small delay error resulting reduced out jitter. It also increases the linearity of delay time versus control voltage. The circular edge combiner can multiply the input signal at a lower supply voltage. The rise and fall time of output signal are more symmetrical. It also present the multiplication factor of the clock generator can be easy to choose with the increasing of the number of delay elements.

Abstract: In a delay circuit, when a first conductivity-type transistor (M6) becomes conductive on the basis of one level of its input signal, a first current path is formed through a source side transistor (M4), the first conductivity-type transistor (M6), and a second drive transistor (M9) between a source power line and a sink power line, and its output signal being the delayed inverse of the one level of the input signal is output from a connection point of another source side transistor (M5) and a sink side transistor (M11), and when a second conductivity-type transistor (M7) becomes conductive on the basis of the other level of the input signal, a second current path is formed through a first drive transistor (M3), the second conductivity-type transistor (M7), and another sink side transistor (M10), and the output signal being the delayed inverse of the other level of the input signal is output from the connection point.

Abstract: A measure control delay includes a measuring delay line and a signal generating delay line, each of which include a plurality of series-connected delay units. A digital signal is applied to an initial delay unit in the measuring delay line and it sequentially propagates through the delay units until a second digital signal is received. These outputs are applied to control inputs to the signal generating delay line to control the number of delay units through which a clock signal propagates before being output from a final delay unit. Each of the delay units in the measuring delay line includes a pair of series connected NOR gates. A NOR gate to which the digital signal is initially applied is coupled to a second NOR gate as a flip-flop so that the output of the NOR gate remains constant after the digital signal has been applied to the measuring delay line.

Abstract: A delay line including analog delay elements each having a selectively adjusted coarse and fine delay portion is described. The coarse delay portion receives an input clock signal and generates a ramp signal having a slope based on a predetermined coarse delay setting. The fine delay portion generates a threshold voltage based on a predetermined fine delay setting. A comparator compares the coarse delay ramp signal voltage with the fine delay threshold voltage and generates an output clock signal when the ramp signal voltage surpasses the fine delay threshold voltage. The coarse delay is linearly adjustable based on a 32-bit binary input signal and the fine delay is binary-weight adjusted based on a 5-bit binary input signal. Both the coarse and fine delay portions are controlled by delay line control circuitry which compares a feedback version of the output clock signal with the input clock signal and provides control signals to increment or decrement coarse and fine delay in the delay line.

Abstract: A circuit for generating stable signal edges includes an output driver circuit having a current path for varying a charge on a capacitor in response to an input signal and constant current generation circuitry for maintaining a constant current through the current path of the output driver circuit and varying the charge on the capacitor to produce an output signal with a stable edge.

Abstract: The method provides wide-range delay value adjustment without making changes in cell size and metal wiring, even when a process variation occurs. Threshold values of some or all of the transistors which form the delay gate inserted into the signal path are varied to control the delay value of the delay gate, so that the delay value of the signal path is adjusted.

Abstract: One use for delay adjustment circuit (32), coarse-grain delay offset circuit (34), and fine-grain delay synthesis circuit (36) may be as part of a delay replication circuit (30) used to replicate the frequency versus voltage behavior of an integrated circuit (29). Also, a circuit (30) and method for determining optimal power and frequency metrics of integrated circuit (29) is also described. In addition, a method for determining programmable coefficients to replicate frequency and supply voltage correlation is described.

Abstract: A delay circuit generates an output signal by delaying an input signal, and includes a ferroelectric capacitor having a first end and a second end, a means for inverting a polarization of the ferroelectric capacitor by producing an electric potential difference between the first end and the second end based on an electric potential of the input signal and a generation means for generating the output signal by delaying the input signal based on a change in an electric potential of the second end caused by the polarization inversion.

Abstract: A ring oscillator with a plurality of delay stages having selectable active loads for selecting an R-C time constant that defines a delay through the delay stage. The ring oscillator oscillation frequency is a function of the selected R-C time constant, a selectable bias level, and the number of delay stages in the ring oscillator. In one embodiment, a MOSFET device gate-to-source capacitance is used with at least one selectable resistive device to form the R-C time constant. In an alternate embodiment, a plurality of parallel coupled resistive devices and parallel coupled capacitive devices are selectively coupled to the active load circuit to set the delay through the delay stage. The resistive devices are formed to be one of a resistor configured MOSFET device and a traditional resistive element. The capacitive devices are formed to be one of a capacitor configure MOSFET device and a traditional capacitive element.

Abstract: A ring oscillator that uses active negative capacitance at one or more stages of the ring oscillator to adjust the frequency of oscillation. By using a negative capacitance generator, negative capacitance may be placed in shunt with each stage of the ring, thereby reducing the effective input capacitance. Tuning of the ring oscillation frequency is accomplished without changing the bias point of each stage. The ring oscillation frequency may be increased, rather than reduced as in current approaches.

Abstract: PMOS transistors P1-Pn and PMOS transistors P1?-Pn? are respectively connected in series between a supply voltage terminal VD and output terminals OUTB, while NMOS transistors N1-Nn and NMOS transistors N1?-Nn? are respectively connected in series between the output terminals OUTB and a ground terminal G. Input terminals S1-Sn are respectively connected to the gates of the PMOS transistors P1?-Pn? and NMOS transistors N1-Nn, and they are respectively connected to the gates of the PMOS transistors P1-Pn and NMOS transistors N1?-Nn? through corresponding inverters IV1-IVn.

Abstract: A semiconductor integrated circuit device includes a differential output driver circuit arranged at each I/O portion, and a delay element. The differential output driver circuit receives a pair of differential signals generated by a circuit on the input stage. An output signal from the differential output driver circuit is transmitted through the first and second signal lines. Each of the first and second signal lines includes a global interconnection, bump, and transmission line. The delay element is inserted in at least one of the first and second signal lines. The delay element delays signals passing through the signal lines so as to make the delays of the signals substantially equal to each other, compensating for the signal delay time generated by the line length difference.

Abstract: The present invention relates to an integrated circuit device and method of adjusting capacitance of a node of an integrated circuit In one embodiment, the device comprises a first digital input, a first parasitic capacitance block, a first output, a second digital input, a second parasitic capacitance block and a second output. The first parasitic capacitance block includes an inverter, a variable capacitance element, and a wire capacitance element. The first parasitic capacitance block has a capacitance that is a function of the first digital input. The first output is responsive to the first parasitic capacitance block, and the second output is responsive to the second parasitic capacitance block.

Abstract: A semiconductor integrated circuit device includes a differential output driver circuit arranged at each I/O portion, and a delay element. The differential output driver circuit receives a pair of differential signals generated by a circuit on the input stage. An output signal from the differential output driver circuit is transmitted through the first and second signal lines. Each of the first and second signal lines includes a global interconnection, bump, and transmission line. The delay element is inserted in at least one of the first and second signal lines. The delay element delays signals passing through the signal lines so as to make the delays of the signals substantially equal to each other, compensating for the signal delay time generated by the line length difference.

Abstract: A balancing circuit and method of operation thereof for use with a circuit having first and second complementary drivers exhibiting different current gain characteristics. In one embodiment, the balancing circuit includes a sensing subcircuit that provides a correction signal indicating a first current gain characteristic of the first driver. The balancing circuit also includes a compensation subcircuit that generates a current gain compensation signal to the first driver to substantially match a second current gain characteristic of the second driver based on the correction signal.

Abstract: A delay adjustment circuit for a delay locked loop, comprises a delay rough adjustment circuit unit (to which input clock signal CLK-IN, and delay control signals A1 to A6 are transmitted) for selectively obtaining outputs of roughly adjusted delays A and B of two systems having a delay difference indicating a maximum delay value of fine interval delay quantity adjustment from selected ones of selection circuits S1, S3 and S5 of an odd-number stage and selection circuits S2, S4 and S6 of an even-number stage connected to delay elements D1 to D3. Furthermore, a delay fine adjustment circuit unit (to which delay control signals B1 to B4, and enable signal ENABLE are transmitted) including delay elements FA and FB for receiving outputs of roughly adjusted delays A and B, and selectively carrying out fine interval delay quantity adjustments of the two systems by opposite operations.

Abstract: A circuit for providing substantially a constant delay of an electrical signal that compensates for voltage, temperature and process variations includes an inverter. A delay cell has an output that is coupled to the inverter. The delay cell includes a charge transistor coupled to a capacitor. A control circuit has an output that is coupled to a gate of the charge transistor. The output has a voltage that is proportional to a trip voltage of the inverter. The delay cell also has a discharge transistor. The control circuit contains a second output that is coupled to a gate of the discharge transistor. The second output has a voltage that is also proportional to the trip voltage of the inverter.

Abstract: A delay circuit includes a first inverter connected to a supply voltage, and has an input for receiving an input signal. A delay regulating transistor is connected between the first inverter and a first voltage reference, and has a control terminal for receiving a biasing voltage. A capacitor is connected between an output of the first inverter and the first voltage reference. A second inverter is connected to the output of the first inverter for outputting a delayed output signal. An auxiliary current path is in parallel to the delay regulating transistor for allowing a portion of a discharge current from the capacitor to flow therethrough. The portion of the discharge current is proportional to the supply voltage. The auxiliary current path includes a diode connected to the first inverter, and a second transistor connected between the diode and the first voltage reference. The second transistor has a control terminal for receiving the biasing voltage.

Abstract: In one embodiment, a digital circuit element has a propagation delay that is substantially constant over a range of supply voltages applied to the digital circuit element. In another embodiment, a digital circuit element may include an input node, an output node, and at least one gate coupling the input node and the output node. A plurality of possible voltage transition curves may be associated with a corresponding change of a first voltage at the input node over time, each voltage transition curve being determined by a corresponding supply voltage and the curves intersecting within a relatively narrow range of voltages. The gate may be operable to change a second voltage at the output node in response to the first voltage reaching a threshold voltage of the gate, and the threshold voltage may be set within the relatively narrow range of voltages in which the voltage transition curves intersect in order to reduce the dependence of the propagation delay on the supply voltage.

Abstract: An inverter circuit includes a first transistor connected between an input terminal and a gate of a second transistor, a second transistor connected between power supply voltage and an output terminal, a third transistor connected between an input terminal and a gate of a fourth transistor and a fourth transistor connected between a ground and the output terminal.

Abstract: A compensation circuit includes at least one of an n-channel device connected to oppose a high-to-low transition and a p-channel device connected to oppose a low-to high transition. The n-channel and p-channel devices may be diodes, transistors, or transistors connected to function as diodes. The n-channel and p-channel devices may be connected to a large variety of devices and circuits, such as phase locked loops, delay locked loops, clock circuits, or any circuit which requires two balanced paths, one through n-channel devices and one through p-channel devices, to compensate for process variations. Methods for balancing a circuit path and compensating for process variations are also disclosed.

Abstract: The present invention is directed to a transition delay circuit. The transition delay circuit includes a delay circuit which is responsive to an input signal. The transition delay circuit produces an output signal at a common node. The transition delay circuit also includes a first MOS capacitor connected between the input signal and the common node and a second MOS capacitor connected between the input signal and the common node. A method for delaying an input signal to a buffer circuit is also disclosed.

Abstract: A clock control circuit for reducing jitter has at least one averaging circuit for generating, and outputting from an output terminal, a signal having a time difference obtained by internally dividing a time difference between first and second signals input respectively from first and second input terminals. First and second clock signals are supplied respectively to the first and second input terminals of the timing averaging circuit, and a clock in which a time difference between pulses of the first and second clock signals is averaged is generated.

Abstract: A digital driver circuit with one or more CMOS inverters intended as input stages, whereby for the MOS FETs of the inverters the channel width/length (W/L) ratio increases from stage to stage. The digital driver circuit includes an intermediate stage with two further CMOS inverters, connected between a supply voltage Vcc and ground. The driver circuit also includes an output stage having two MOS FETs with the drain terminals of both the MOS FETs of the output stage connected both to each other and to the output of the circuit, the W/L ratio of both MOS FETs exceeding that of the MOS FETs of the intermediate stage. The switch-over of the two MOS FETs of the output stage, occurring with changes of the digital input signal at the input of the circuit, is offset in time with respect to each other, thereby reducing current peaks.

Abstract: A system and method for maintaining desired circuit component attributes is shown. According to a preferred embodiment, a high frequency circuit component, such as a MMIC, is retained in a circuit using a degradeable material, such as silver filled epoxy, wherein a portion of the degradeable material remains exposed. A protective coating of resin is applied to the exposed portion of the degradeable material by preferably depositing a predetermined amount of protective material, such as an epoxy resin, a void near the exposed portion of the degradeable material. The protective material preferably migrates to fully cover the exposed portion of the degradeable material without covering the circuit component. Accordingly, the circuit component is protected from substantial changes in operation characteristics due to the protective material and likewise is protected from changes in operation characteristics due to degradation of the degradeable material resulting from exposure.

Abstract: A system and method for eliminating pulse width variations in digital delay lines partitions a delay line into two substantially identical blocks of delay inverters, inserting a first inverter between the two blocks and a second substantially identical inverter at the output of the second block. The requirement for matching device characteristics at the individual delay inverter level is eliminated and the only requirement is that the parasitic loading of the inverter between the blocks and the inverter on the output of the second block be the same. Consequently, the layout of the delay inverters in a single block may be made in the most efficient manner possible and the same identical layout can be used for the first and second blocks.

Abstract: An object of the present invention is to simply and rapidly adjust a delay time of a delayed clock signal in accordance with a change in frequency of an input clock signal. The present invention comprises: a pulse generating circuit for generating a pulse signal PULSE with a trailing edge of an input clock signal as a reference; an inverter chain consisting of a plurality of inverters; a pair of inverter chains for sequentially delaying output signals from the pulse generating circuit; a plurality of NOR gates for adjusting a delay time of each inverter in the inverter chain; and a plurality of NAND gates for similarly adjusting a delay time of each inverter in the inverter chain. Since the delay time of the delayed clock signal in a next cycle is set based on the pulse signal generated based on a trailing edge of the input clock signal, even if a cycle of the input clock signal varies, the delay time of the delayed clock signal can be rapidly changed in accordance with this variation.

Abstract: A voltage ramp/threshold variable pulse delay circuit implemented on an IC varies the R instead of the C, which may be fixed. A variable R is formed by a plurality of FET's arranged in parallel. The FET's are sized according to a weighting scheme, which may be binary, and the amount of R produced is determined by which combination of FET's is switched ON, rather than by analog variations in their drive level. If the plurality of sized parallel FET's is made up of individual FET's all of the same polarity, then an undesirable reduction in voltage comparison range will obtain, which may produce an objectionable reduction in available pulse delay if VDD is reduced such that it is no longer many times larger than FET threshold voltage. That reduction in voltage comparison range can be eliminated by replacing each such individual FET with a pair of similarly sized FET's in parallel, the members of which pair are of opposite polarities.

Abstract: A system is described for providing pulses to test a semiconductor device, such as a memory device. The system includes several voltage sources, each voltage source being coupled to an output terminal through a pass gate. A control logic circuit provides a control signal to each of the pass gates to render the pass gates conductive in a sequence. A voltage generated by each voltage source is coupled to the output terminal in a sequence to generate a series of pulses at the output terminal. Each of the voltage sources may be a programmable digital-to-analog converter receiving a voltage control signal and generating a voltage based on the voltage control signal.

Abstract: A compensation circuit includes at least one of an n-channel device connected to oppose a high-to-low transition and a p-channel device connected to oppose a low-to high transition. The n-channel and p-channel devices may be diodes, transistors, or transistors connected to function as diodes. The n-channel and p-channel devices may be connected to a large variety of devices and circuits, such as phase locked loops, delay locked loops, clock circuits, or any circuit which requires two balanced paths, one through n-channel devices and one through p-channel devices, to compensate for process variations. Methods for balancing a circuit path and compensating for process variations are also disclosed.

Abstract: A delay locked loop includes a delay circuit capable of generating an output clock and further capable of generating a GATE signal in response to an aliased condition. A phase detector is coupled to the delay circuit and is capable of comparing a phase difference between a reference clock and the output clock from the delay circuit and generating a pump up signal if the output clock is lagging the reference clock. The phase detector is capable of generating a pump down signal if the output clock is leading the reference clock. A charge pump is coupled to the phase detector and is capable of generating a control voltage for controlling the delay provided to the output clock and capable of pulling up the control voltage in response to the GATE signal.

Abstract: In the delay circuit of an inverter chain, the change in the output node of an inverter circuit is suppressed until the voltage of the output node or the output signal of another inverter circuit located downstream by an odd number of stages is inverted in logic. Thus, the delay circuit having a constant delay time regardless of the operating environment such as the power-supply voltage and the operating temperature can be implemented.

Abstract: A first delay line for forward pulses and a second delay line for backward pulses are composed of unit delay elements. A state holding section determines the input position of a backward pulse on the second delay line according to the transfer position of a forward pulse transferred along the first delay line. In the unit delay elements constituting the first and second delay lines, the accuracy of synchronization can be improved by increasing the current driving capability of the transistors related to the rising of the pulse signal.

Abstract: The present invention is directed to a transition delay circuit. The transition delay circuit includes a delay circuit which is responsive to an input signal. The transition delay circuit produces an output signal at a common node. The transition delay circuit also includes a first MOS capacitor connected between the input signal and the common node and a second MOS capacitor connected between the input signal and the common node. A method for delaying an input signal to a buffer circuit is also disclosed.

Abstract: A variable frequency ring oscillator is controlled by a control signal and has an odd number of cascaded inverting gates. The inverting gates each have input terminals receiving an input signal. Except for the first of the cascaded inverting gates, each input signal on a gate is the output from the preceding inverting gate. The input terminal of the first of the inverting gates receives the output of the last of the inverting gates. At least one inverting gate is a cell having a gain variable as a function of a control signal. An output signal ext of the circuit is an inversion of an input signal inp and has a hysteresis that is a function of a control signal cont. The term “hysteresis” as used herein signifies, for example, a variable frequency signal remaining substantially in its current state for a certain length of time after which the variable frequency signal changes state with a magnitude that is a function of a control signal, upon change of state of an input signal.