Abstract: A method, and associated apparatus, for eliminating pulse width variations in digital delay lines. The method includes partitioning the delay line into two substantially identical blocks of delay inverters and inserting a first inverter between the two blocks and a second substantially identical inverter at the output of the second block. The requirement for matching device characteristics at the individual delay inverter level is eliminated, and the parasitic loading of the inverter between the blocks and the inverter on the output of the second block is the same. Since the rising edge input to the first block becomes a falling edge input to the second block as it propagates through the delay line, the rising and falling input edges will encounter an identical set of transitions as they propagate through the two blocks.

Abstract: A voltage regulation device is for a reference cell of a dynamic random access memory arranged in lines and columns and including a plurality of memory cells. The device includes at least one capacitor of a predetermined capacitance which can be discharged during memory access.

Abstract: A RC delay time stabilizing circuit of the present invention includes an inverter which inverts a periodic input signal, a RC delay unit which is charged/discharged in accordance with an output from the inverter, a pull-up MOS transistor connected between a source voltage terminal and an output terminal of the RC delay unit and having a gate for receiving the input signal, and an output unit which generates an output signal having an identical delay time in accordance with output levels of the inverter and the RC delay unit. Such RC delay time stabilizing circuit of the present invention decreases the charging time of the RC delay unit when a periodic signal is inputted, thus being able to maintain the same delay time in each cycle of the input signal.

Abstract: The present invention is directed to a transition delay circuit. The transition delay circuit includes a delay circuit which is responsive to an input signal. The transition delay circuit produces an output signal at a common node. The transition delay circuit also includes a first MOS capacitor connected between the input signal and the common node and a second MOS capacitor connected between the input signal and the common node. A method for delaying an input signal to a buffer circuit is also disclosed.

Abstract: A voltage controlled oscillator is provided in the form of two ring oscillators 30 and 32. Each oscillator stage 14 includes an invertor 16, a level change accelerating circuit 18 and a level change decelerating circuit 20. The level change accelerating circuit 18 is responsive to an input control signal Vctrl to increase the oscillator frequency by decreasing the propagation delay through the invertor 16. The level change decelerating circuit 20 is responsive to the input control signal Vctrl to decrease the oscillator frequency by increasing the propagation delay through the invertor 16. Pairs of opposing invertors 34, 36, 38, 40 and 42 disposed between output signal lines of corresponding oscillator stages 14 in the two ring oscillators 30 and 32 serve to lock the two ring oscillators in antiphase.

Abstract: An odd number of inverter circuits are connected with each other so as to form a ring. A first current-control element is provided between an oscillation signal line which is used for connecting adjacent inverter circuits and a power-source-potential point, a current flowing through the first current-control element varying by a first control signal. A second current-control element is provided between the oscillation signal line and a ground point, a current flowing through the second current-control element varying by a second control signal.

Abstract: A technique for compensating for supply voltage variations in a delay circuit by utilizing a bias circuit to maintain the delay substantially constant with respect to the supply voltage. The bias circuit generates a bias current having a fixed component and a variable component, in which the variable component varies proportionately to variations in the supply voltage to maintain the delay substantially constant.

Abstract: According to the present invention, by setting the logic state of one or more delay signals to appropriate values, the resistive value of a plurality of power supply delay elements throughout an integrated circuit having distributed circuit blocks may be modified to produce desired delay times or pulse width adjustments throughout the integrated circuit. Setting delay signals to desired logic states may be accomplished by a variety of means including forcing test pads to a logic level, blowing fuses, or entering into a test mode.

Abstract: Voltage controlling/oscillating device comprises a terminal for setting the delay rate in the delay unit and the delay interpolator. Clock signal whose phase is inverted by the inverting gate is inputted into a first input terminal of the delay interpolator and into the delay unit. The delay unit delays the signal by d1 and inputs into second input terminal of the delay interpolator. Oscillation frequency control voltage is fed into a terminal of the delay interpolator through an oscillation frequency control terminal of the device. Delay control voltage is fed into a terminal of the device in order to control a propagation delay rate in the delay unit and the delay interpolator. The delay rate in a delay unit and a delay interpolator can be adjusted by a delay control voltage.

Abstract: Disclosed is a delay circuit for delaying at least the timing of a rising edge or the timing of a falling edge of an input signal alternating between first and second levels. The delay circuit includes (1) a charge pump in which first and second field-effect transistors of different channels are serially connected; (2) a capacitor connected in parallel with the first field-effect transistor; (3) a charging current control circuit for passing a charging current into the capacitor via the second field-effect transistor of the charge pump when the input signal is at the first level; (4) a discharge current control circuit for releasing a discharge current from the capacitor via the first field-effect transistor when the input signal is at the second level; and (5) a discrimination circuit for outputting a signal of a prescribed logic level based upon a terminal voltage of the capacitor.

Abstract: A delay circuit based on gate delay enables precise adjustment of a delay value. The delay circuit is composed of a plurality of p-channel transistors and n-channel transistors connected in series which are provided with capabilities that differ, ranging from the transistors closer to a power supply to the transistors closer to an output end so as to change the output drive capability and the input capacity independently, thereby improving the adjustment accuracy of the delay value of the circuit.

Abstract: A system is described for providing pulses to test a semiconductor device, such as a memory device. The system includes several voltage sources, each voltage source being coupled to an output terminal through a pass gate. A control logic circuit provides a control signal to each of the pass gates to render the pass gates conductive in a sequence. A voltage generated by each voltage source is coupled to the output terminal in a sequence to generate a series of pulses at the output terminal. Each of the voltage sources may be a programmable digital-to-analog converter receiving a voltage control signal and generating a voltage based on the voltage control signal.

Abstract: The present invention is directed to a transition delay circuit. The transition delay circuit includes a delay circuit which is responsive to an input signal. The transition delay circuit produces an output signal at a common node. The transition delay circuit also includes a first MOS capacitor connected between the input signal and the common node and a second MOS capacitor connected between the input signal and the common node. A method for delaying an input signal to a buffer circuit is also disclosed.

Abstract: A time delay circuit that produces a constant delay and is independent of supply voltage. The time delay circuit has a current mirror circuit, a voltage shift circuit, an inverter and a capacitor. The inverter will trip at a predetermined voltage level. A capacitor is coupled to the current mirror circuit and to the inverter for generating a portion of the delay time. A voltage shift circuit is coupled to the inverter for approximately mirroring a voltage shift in the current mirror circuit thereby allowing the time delay circuit to be voltage independent.

Abstract: A voltage controlled ring oscillator (VCRO) that can operate at low voltage and provide a variable periodic output. A plurality of transistors form a ring oscillator and a selected transistor in the ring oscillator has a body which can float with respect to ground potential. The selected transistor has a threshold voltage which is controllable by a voltage applied to the transistor body. A control input is coupled to the transistor body such that the body of the transistor can be charged by the control input. Charging the body alters the threshold voltage of the transistor and thereby controls the oscillation frequency of the oscillator.

Abstract: A ring oscillator using CMOS technology having three logic gates, including a threshold amplifier, where the transistors that set the voltage rise threshold and the voltage drop threshold in the amplifier are controlled by a bias control circuit so that the ratio of voltage rise threshold to the voltage supply diminishes and the ratio of the voltage drop threshold to the voltage supply increases, when the supply voltage falls.

Abstract: The present invention provides an analog PLL circuit able to shorten a lockin time during which oscillating frequency and phase of a voltage controlling oscillator settle.An analog PLL circuit according to the present invention comprises a divider, a phase comparator, a charge pump, a low pass filter, a voltage controlling oscillator, and a divider. The voltage controlling oscillator has a ring oscillator composed of a plurality of logic inverting elements capable of changing the delay amount. During the reset period, the initial voltage is inputted to the voltage controlling oscillator via the analog switch, and the initial delay amount is set to each of the logic inverting elements. After the reset period finishes, at the point when the rising edge of the standard input signal is firstly inputted, the output of the D flip-flop becomes high level and the ring oscillator begins the oscillating operation.

Abstract: An RC equivalent delay circuit includes an input node, an output node, a feedback node, and an intermediate node; a first inverter having an input coupled to the input node and an output coupled to the intermediate node; a second inverter having an input coupled to the intermediate node and an output coupled to the feedback node; a third inverter having an input coupled to the feedback node and an output coupled to the output node; and one or two switches having a first input coupled to the input node, a second input coupled to the feedback node, and an output coupled to the intermediate node.

Abstract: An improved ring oscillator (10, 70) includes a first, second and third current starved inverters (12, 14, 16) coupled in a ring, a first fast inverter (40) coupled between the second and third current starved inverters (14, 16), and a second fast inverter (45) coupled between the third and first current starved inverters (14, 16). An output buffer (30) coupled to the ring provides an output periodic waveform.

Abstract: A controlled delay circuit having a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.

Abstract: The present invention provides an technique for compensating a operation speed variation based on a principle that a circuit operation speed is adjusted by reflecting a delay time of an internal circuit itself that is an object of the operation speed fluctuation compensation.An internal circuit (1 in FIG. 1) has a critical path with an output terminal pair that outputs the identical logical values till its each operation is finished, and data in a complementary signal format as soon as its each operation is finished. A logical gate (2 in FIG. 1) can detect its operation end by sensing the signal transition into a complementary signal format at the output terminal pair of the internal circuit.

Abstract: A CMOS delay circuit for differential signals is provided. By adjusting the amplitude of clamping voltages, the delay period may be adjusted to a desired level. By using a single constant current source to charge both output nodes, current consumption is reduced.

Abstract: This invention relates to an asymmetrical delay network connected between first and second voltage references and having an input terminal for receiving a trigger signal, and an output terminal. The network is of the type which includes at least one charge control transistor and at least one delay capacitor, connected in series with each other between the first and second voltage references. In particular, the charge control transistor has a control terminal connected to a generator of a constant current, and the output terminal delivers a delay signal which is synchronized to a first edge of the trigger signal. The invention also concerns a constant pulse generator including at least a first and a second of such asymmetrical delay networks.

Abstract: Signal-controlled oscillator structures are provided that are substantially insensitive to temperature, supply voltages and fabrication processes. They include a plurality of time-delay stages that are serially connected in a closed feedback ring and each of the stages includes an amplifier, at least one capacitor and at least one signal-controlled impedance element that couples the capacitor to the amplifier. Accordingly, the frequency of the oscillator is a function of a control signal applied to the impedance elements of the stages. In an oscillator embodiment, each of the amplifiers is a differential pair of transistors, the capacitor comprises first and second capacitors and the signal-controlled impedance element comprises first and second coupling transistors that each couples a respective one of the capacitors to a different side of the differential output.

Abstract: A delay device includes storage elements arranged in at least two rows 4, 5; 6, 7 in an integrated circuit, preferably in switched-capacitor technology. The delay device 2; 3 has an even number of storage elements. A first clock signal is provided from which, for producing a delay time equal to an odd multiple of the clock period of the first clock signal, a second clock signal is derived by means of a clock generation circuit 9, this second clock signal clocking the storage elements and being derived from the first clock signal in such a manner that one clock pulse of the first clock signal is suppressed in a selectable or given cycle and all the other clock pulses in the cycle are taken over in the second clock signal.

Abstract: A delay circuit is to produce a delay timing which is larger than one cycle time of a reference clock while the resolution of which is smaller than the one cycle time of the reference clock.

Abstract: In a semiconductor gate circuit, an MOS transistor having a low threshold voltage and a standard MOS transistor having threshold voltages of large absolute values are connected in series between an output node and a power supply node. The MOS transistor having the threshold voltage of the large absolute value receives on a gate thereof, a signal preceding in phase a signal applied to a gate of the MOS transistor having the small threshold voltage. In the semiconductor gate circuit, a dependency of input/output characteristics on a power supply voltage is small, and a leak current during standby is reduced. The standard MOS transistor turns on prior to turning on of the low threshold voltage MOS transistor, and turns off when the low threshold voltage MOS transistor turns off. The output node driving current is controlled by the low threshold voltage MOS transistor while a subthreshold leak current is suppressed by the standard transistor.

Abstract: A low offset amplifier has an output stage constituted by an npn transistor and a pnp transistor in a push-pull arrangement, and a driver stage. The latter includes a current-mirror circuit having, in its input branch, a pnp transistor in series with a first constant-current generator and, in its output branch, an npn transistor, and two complementary bipolar transistors with collectors connected together to the output terminal and the bases are connected together to the input terminal of the amplifier. The emitter of the pnp transistor of the driver stage is connected to the positive terminal of the supply by a second constant-current generator and to the base of the npn transistor of the output stage, and the emitter of the npn transistor of the driver stage is connected to the negative terminal of the supply by the npn transistor of the output branch of the current-mirror circuit and to the base of the pnp transistor of the output stage. The amplifier has a very low or zero offset (Vos=Vout-Vin).

Abstract: A variable frequency ring oscillator is controlled by a control signal and has an odd number of cascaded inverting gates. The inverting gates each have input terminals receiving an input signal. Except for the first of the cascaded inverting gates, each input signal on a gate is the output from the preceding inverting gate. The input terminal of the first of the inverting gates receives the output of the last of the inverting gates. At least one inverting gate is a cell having a gain variable as a function of a control signal. An output signal ext of the circuit is an inversion of an input signal inp and has a hysteresis that is a function of a control signal cont. The term "hysteresis" as used herein signifies, for example, a variable frequency signal remaining substantially in its current state for a certain length of time after which the variable frequency signal changes state with a magnitude that is a function of a control signal, upon change of state of an input signal.

Abstract: A delay circuit includes a charge/discharge circuit and a logic circuit. The charge/discharge circuit is used to moderate a slope of change of an input signal. The logic circuit receives a charge/discharge signal output from the charge/discharge circuit, and is used to change an output signal of the logic circuit when the charge/discharge signal exceeds a threshold value of the logic circuit. A time constant in the charge/discharge circuit is varied in accordance with the change in the output signal of the logic circuit. This serves to alleviate the malfunctioning and timing constraint problems that occur after the threshold value of the next-stage circuit (logic circuit) is exceeded.

Abstract: In this invention is described a CMOS buffer that reduces short circuit current in the output stage. The short circuit current is a result of current flowing between circuit bias and ground through the output transistors during switching transition. The reduction in shorting current is accomplished by driving the two CMOS output transistors of opposite type separately, and providing a turn off signal for one output transistor ahead of the turn on signal for the other transistor. Thus one transistor is turned off before the other transistor is turned on, reducing shorting between the two transistors. The on and off signal delay is controlled from unbalanced inverters connected separately to each input of the output transistors.

Abstract: This invention describes a delay circuit for integrated circuits that has the capability to delay the rising and falling transitions separately and independent of each other. A signal is fed through an RC network to a Schmitt trigger and then through an inverter to the output of the delay circuit. Two MOS transistors are connected as capacitors and in parallel but in opposing directions between the delay circuit output and the input to the Schmitt trigger to form part of the RC network. The biasing of the two transistors is such that the inversion layer capacitance is active in only one transistor for each signal transition. Thus the falling and rising transition of an input signal can be delayed separately. Changing the gate and channel size in one transistor acting as a capacitor changes the delay in one signal transition. Changing the other gate and channel size changes the delay in the other transition.

Abstract: According to the present invention, clock control logic circuitry of a clocked memory device using precharged data path techniques generates a self-timed pulse. The self-timed pulse is representative of a pulsed path active strobe or a reset strobe of the clocked memory device. The clock control logic circuitry of the present invention is characterized as having at least a first delay timing chain, a second delay timing chain, and means for selectively changing the width of a self-timed pulse generated by the clock control logic circuitry. Selectively changing the width of the self-timed pulse is accomplished by selectively adding the delay of the first delay timing chain to the delay of the second delay timing chain during a special mode of operation of the clocked memory device.

Abstract: A skew logic circuit device comprises:two or more inverters which are connected in series with one another between an input line and an output line; first control switching means for switching voltage from a first power voltage source toward an output terminal of every odd inverter; second control switching means for switching voltage from a second power voltage source toward an output terminal of every even inverter; and edge signal generating means for sequentially controlling the operation of the first and second control switching means by the edge signal of a fixed pulse width caused by logically combining the signal from the input line.

Abstract: A series delay generator for imposing a programmable delay on the timing edges of an incoming waveform is disclosed. The magnitude of the imposed delay is proportional to the value of a binary programming word. The series delay generator is implemented as a series of delay cells, each of which can be programmed into two delay states, a maximum delay and a minimum delay. The magnitude of the maximum and minimum delays can be set and calibrated using an analog tuning voltage. The series of delay cells can be segmentized in order to provide pipelined operation. The series delay generator is therefore capable of processing more than one timing edge at a time, permitting its minimum reprogramming time to span and even exceed the maximum delay span of the generator. A delay cell is also disclosed that uses a differential input and a digitally controlled current balance circuit to advance and retard the zero crossings of the incoming waveform and its inverse.

Abstract: A variable delay circuit for arbitrarily change of a signal delay helps easily attain a desired resolution with a high precision, which has been difficult due to device process dependence of a voltage control circuit applying a voltage to a CMOS circuit. A variable voltage controller is provided between a power source and a CMOS circuit propagating a signal such that a delay time of signal propagation is supervised by controlling the voltage at a connecting point in the variable voltage controller. The controller includes two MOS transistors and an npn transistor, which solves the process dependence and hence leads to a low power consumption and a high resolution.

Abstract: A pulse signal shaper supplying a pulse signal having a stable pulse width, including an input circuit that produces a first pulse signal in response to an input signal, a delay circuit that produces a second pulse signal obtained by delaying the first pulse signal by a predetermined time, and a signal mixing circuit that is connected to the input circuit and the delay circuit. The mixing circuit combines the first pulse signal and the second pulse signal to produce a third pulse signal having a pulse width equal to or greater than a delay time provided by the delay circuit, and supplies the third pulse signal as an output signal from the pulse signal shaper. In a preferred embodiment, the input circuit includes an oscillator responsive to the input signal. When the input signal has a higher frequency than a predetermined frequency, the input signal is supplied as the first pulse signal at a frequency equal to te frequency of the input signal.

Abstract: The present invention provides a circuit (10) and method for providing a delayed output signal which is less sensitive to supply variation compared to conventional circuits, has high noise immunity, can be operated at high frequency, and occupies a minimum area on the semiconductor. The delay is provided according to the present invention by separately controlling the discharge currents of a capacitor (26) before and after the trip point voltage of an output inverter (16) of the circuit (10) has been reached. The delay interval is determined primarily by the capacitor value, the voltage difference between the supply and the trip point of the output inverter, and the first discharge current, set by a resistor (24) in series with a transistor (34). The second discharge current is set by a switch (36) having a series of transistors (38, 40).

Abstract: For high-speed single-ended sensing of the small signal delivered from a (static) RAM or ROM cell, a voltage dependent timing delay circuit is disclosed which prevents early triggering of the set signal of the sense amplifier (SSA 66) when applying a high voltage screen test (i.e. 1.5 times V.sub.DD) to the cell. The timing of the SSA signal is achieved by a high precision delay chain comprising inverters, which is loaded by a voltage dependent current sink (70) coupled to the output of the chain. The inverter delay chain controls the input (SE0) for a driver for the SSA line (66). The current sink may be a pull down NFET (70) which is only activated when the supply voltage is above a determined switching threshold therefor. The gate voltage of the NFET is controlled by a bias control circuit (72) in such a manner that during operation at typical voltage levels, the NFET is deactivated, whereas at higher operating voltage levels (such as 1.5 * V.sub.

Abstract: A novel ring oscillator integrated circuit whose frequency of oscillation is independent of supply voltage, temperature and process technology is described. In addition, the ring oscillator circuit consumes low power and its frequency of oscillation is programmable. The ring oscillator comprises one or more inverter sections cascaded together in series. The output of the final inverter stage is coupled to the input of the first inverter stage. Inserted in the feedback loop is feedback control circuitry which functions to control the start/stop operation of the oscillator. Each inverter section includes a p-channel transistor coupled to a parallel combination of impedance and capacitance, which gives the inverter section asymmetric operating characteristics. This asymmetry helps to achieve a frequency of oscillation independent of supply voltage. A plurality of transistors having predetermined impedance's are coupled in series with the p-channel transistor to form the current limiting impedance.

Abstract: A pulse generator has an input and two outputs at which to respectively generate pulses in relation to different types of signal edges received at the input of the generator. The generator provides two distinct logic circuit blocks of the sequential type, the blocks being mutually independent for generation of the pulses at the two outputs. In this manner it is possible to easily control the characteristics of the pulses. In addition, if two blocks are connected with appropriate and simple logic networks, it is possible in the generation phase to impose conditions between the pulses at the two outputs in a simple manner and with a certain freedom.

Abstract: A PLL circuit includes a sampling pulse generator and a loop circuit using a sample and hold circuit as a phase detector. The sampling pulse generator generates a sampling pulse signal at each level transition of an NRZ input signal. The sample and hold circuit samples a clock signal and hold a voltage signal corresponding to a voltage of the clock signal according to the sampling pulse signal. A voltage-controlled oscillator included in the loop circuit generates the clock signal whose frequency is controlled based on tho voltage signal received from the sample and hold circuit through a loop filter. The voltage signal remains at an appropriate level even when the NRZ input signal remains at the same level for a relatively long time. The sampling pulse generator includes a delay circuit for delaying the NRZ input signal and an exclusive-OR circuit receiving the NRZ input signal and the delayed signal.

Abstract: A power short pulse generator for generating a pulse on a rising edge and falling edge of an input signal according to the present invention comprises an input node for receiving the input signal and an output node for supplying an output signal. A first pulldown circuit and a second pulldown circuit are connected in series between the output node and a first supply voltage potential, the first pulldown circuit and the second pulldown circuit each having an input. A third pulldown circuit and a fourth pulldown circuit are connected in series between the output node and the first supply voltage potential, the third pulldown circuit and the fourth pulldown circuit each having an input. A pullup circuit is connected between the output node and a second supply voltage potential, the pullup circuit having an input. A leakage current circuit is connected between the output node and the second supply voltage potential.

Abstract: A circuit for the generation of a time-stabilized output pulse Iout comprises a capacitor biased by two completely independent voltages whose bias voltages are filed by a current generator through current mirrors and are therefore very stable.

Abstract: Disclosed is a voltage-controlled oscillator which has delay units 11A which have variable resistance circuits 111 and are connected in the form of a ring, and control signal lines 5, 6 for transmitting a control signal CG which can vary control gain. The variable resistance circuits 111 can vary the variation of resistance in response to the control signal CG.

Abstract: A series delay generator for imposing a programmable delay on the timing edges of an incoming waveform is disclosed. The magnitude of the imposed delay is proportional to the value of a binary programming word. The series delay generator is implemented as a series of delay cells, each of which can be programmed into two delay states, a maximum delay and a minimum delay. The magnitude of the maximum and minimum delays can be set and calibrated using an analog tuning voltage. The series of delay cells can be segmentized in order to provide pipelined operation. The series delay generator is therefore capable of processing more than one timing edge at a time, permitting its minimum reprogramming time to span and even exceed the maximum delay span of the generator.A delay cell is also disclosed that uses a differential input and a digitally controlled current balance circuit to advance and retard the zero crossings of the incoming waveform and its inverse.

Abstract: An integrated circuit for selectively providing delay to a waveform carried on a signal line. With the present invention, a waveform is carried by a signal line to which a digitally-controlled capacitive load is coupled. A digital enable line is directly coupled to the capacitive load which either activates or deactivates the capacitive load. When the enable line is in the active state, the capacitive load is activated and the load therefore has maximum capacitance. Accordingly, the delay of the waveform carried on the signal line is also maximized. When the enable line is in the inactive state, the capacitive load has minimal capacitance and the delay of the signal being carried on the signal line is therefore minimized.

Abstract: A CMOS delay cell with feedback circuitry to ensure that the delay cell is operating in saturation mode. A voltage controlled oscillator (VCO) comprising a loop of an odd number of delay cells, where the VCO is operating in a saturation mode. Under normal operation any intermediate node in the VCO will generate an output signal from a delay cell with reduced supply noise. The output signal can be used to generate a PLL clock signal with a lower phase jitter than prior art VCO's operating at low supply potentials.

Abstract: A bit synchronizer for the interpretation of a bit data stream received in a receiver when strobed by an isochronous or plesiochronous clock signal which lies in the receiver time domain is disclosed. This is achieved by alternate activation and deactivation of a first and a second phase aligner respectively, based on monitoring a delay controlled voltage of the active phase aligner. These phase aligners each utilizes differential delay lines which are comprised of differential delay elements, which in turn are comprised of pairs of inverting devices, where both devices of each pair have a controllable delay for positive edges and a pulse form restoring function for negative edges, alternatively a controllable delay for negative edges and a pulse form restoring function for positive edges.

Abstract: Delay circuit comprising a delay cell formed by a current source (I) connected between drain and source of two field-effect transistors (PO, NO) whose gates are connected to each other in order to constitute the input of the cell, and an inverter (INV) linked to one or other of the terminals of the current source (I) according to whether the delay is to affect the leading edge or the trailing edge of the signal to be delayed, a capacitor (C) for defining a delay time (Te) proportional to the power supply voltage and inversely proportional to the current (I) delivered by the current source, being connected between the input of the inverter (INV) and earth, characterized in that it furthermore comprises a circuit (Ci, Cu, S1, S3, AMPLO, P1) for regulating the current delivered by the current source in order to make it proportional to the power supply voltage of the circuit.