Abstract: A compensation circuit 10 is disclosed herein. The circuit includes a control circuit 14 including a delay element 18 with a delay sensitive to at least one parameter which causes variations in delay and also comprises a compensated driver circuit 16. The compensated driver circuit 16 has a control input B coupled to the control circuit 14 and a signal input C coupled to an input circuit 12. The delay of an output signal OUT of the compensated driver circuit 16 is controlled in part by the control circuit 14 which modifies the delay of the output signal OUT in response to variation of the parameter. Other systems and methods and numerous variations are also disclosed.

Abstract: A delay circuit comprises cascade-connected first through third inverters. The second inverter comprises a first resistor one terminal of which is connected to an output of the first inverter; a P-channel MOS transistor a gate of which is connected to the other terminal of the first resistor, and a source of which receives a power supply voltage; an N-channel MOS transistor a gate of which is connected to the other terminal of the first resistor, a source of which receives a ground voltage, and a drain of which is connected to a drain of the P-channel MOS transistor; and a capacitor one terminal of which is connected to the other terminal of the first resistor, and the other terminal of which is connected to the other terminal of a current path of the P-channel MOS transistor.

Abstract: A VCO includes an oscillator and a controller for controlling the operation of the oscillator. The oscillator is formed by connecting odd number of stages of delay circuits in a ring form. The controller creates a second control voltage based on an input first control voltage. The second control voltage is set in a symmetrical relation to the first control voltage with respect to an intermediate potential between the power supply and the ground set as a reference. Each of the delay circuits includes an inverter, first and second current control circuits, and first and second current value setting circuits. The inverter includes a first transistor of first conductivity type and a second transistor of second conductivity type to receive and output a signal. The first current control circuit is connected between the first transistor and the ground, for controlling a current flowing in the first transistor when the first transistor is set in the conductive state according to the first control voltage.

Abstract: A method and apparatus for testing and programming signal timing are disclosed which can be incorporated into an integrated circuit device utilizing on-chip timed command signals and pulses. The method of the invention enables nonpermanent testing and retesting of a device at various operational speeds during production testing. During retesting, temporary signal delays are selectively introduced into the circuit of a device which failed a previous test due to non-repairable errors. Once a device passes the production test error-free or with repairable errors, the temporary signal delays are permanently programmed into the device. Specifically, the method utilizes one or a plurality of mode control circuits and test voltage input terminals to nonpermanently select signal delays which may be identified and permanently enabled at a later time.

Abstract: A buffer circuit with driving current adjusting function is provided which may automatically set a driving current characteristics of a buffer to the most suitable value according to a system where the driving current is to be applied.

Abstract: A synchronous SRAM (or DRAM or other logic) chip with input registers (or latches) associated with the chip memory cell array input lines, where there is logic associated with the registers, locates the logic gates upstream of the registers and connected to the D input of each register. Hence the logic gates not only provide the needed logic function, but also provide the necessary delay to meet the specified hold time delay in synchronous circuits. This reduces the logic function after the input registers and hence improves the clock-to-output access time of the chip.

Abstract: A circuit for the generation of a time-stabilized output pulse Iout comprises a capacitor biased by two completely independent voltages whose bias voltages are fixed by a current generator through current mirrors and are therefore very stable.

Abstract: A transition detection circuit is provided comprising input means receiving the signal to be monitored for generating a first pulse having a first predetermined pulsewidth when a transition occurs in the signal being monitored; and output means responsive to the first pulse from the input means for generating a second pulse having a second predetermined pulsewidth which is less than the first predetermined pulsewidth. The present invention permits a large number of signals to be monitored for transition yet provide a highly precise output pulsewidth, all with a minimum of circuitry. Preferably the input means include a plurality of input channels, each channel being assigned to a different signal being monitored and each channel providing the first predetermined pulsewidth using simple, non-precision time delay circuits. The output state employs a single, high precision time delay circuit to provide the second predetermined pulsewidth.

Abstract: A semiconductor memory device has an addressable data storage powered with an internal step-down power voltage for storing data bits, a signal buffer circuit powered with a non-step-down power voltage for producing an internal output enable signal, an output data buffer circuit powered with the non-step-down power voltage and enabled with the internal output enable signal for producing an output data signal from a read-out data bit and a delay circuit connected between the signal buffer circuit and the output data buffer circuit for introducing delay into propagation of the internal output enable signal, and the delay circuit is implemented by a plurality of complementary inverters connected in cascade, wherein the p-channel enhancement type field effect transistors of the complementary inverters have source nodes connected with an internal step-down power voltage line and channel regions biased with the non-step-down power voltage so that the delay is proportional to the external power voltage.

Abstract: A delayed-pulse generator formed by a combination of a comparator, a current-mirror circuit, a capacitor, a switching transistor and a constant-current source further has a transistor whose emitter and base are connected together and which is connected in parallel and in forward-direction with respect to the constant-current source. A charging current of a very small value can be set stably without being affected by the leakage current flowing in the switching transistor even in a high temperature operation. Thus, a pulse having a long delay time can be readily obtained. In addition, an erroneous operation caused by the leakage current flowing in the switching transistor can be effectively suppressed.