Abstract: A MOS-type power device having a drain terminal, a source terminal, and a gate terminal; and a protection circuit having a first conduction terminal connected to the gate terminal, via a diffused resistor, and a second conduction terminal connected to the source terminal. The protection circuit has a resistance variable between a first value and a second value according to the operating condition of the power device. In a first embodiment of the protection circuit, an ON-OFF switch made by means of a horizontal MOS transistor has a control terminal connected to the drain terminal of the power device. In a second embodiment of the protection circuit, the ON-OFF switch is replaced with a gradual-intervention switch made by means of a P-channel JFET transistor having a control terminal connected to the gate terminal of the power device.

Abstract: A noise limiter of a semiconductor integrated circuit device includes a diode-connected N channel MOS transistor between a bus line and a line of a potential lower than the power supply potential by a threshold voltage, and a diode-connected P channel MOS transistor between a line of a potential higher than the ground potential by a threshold voltage and the bus line. The potential of the bus line is limited between the level of the power supply potential and the ground potential, so that the noise level of the bus line is reduced.

Abstract: Apparatus for providing electrostatic discharge protection having an nMOS transistor with bias simultaneously applied to the gate and the p-well of the nMOS transistor. A bias circuit is fabricated using a plurality of the Zener diodes. The double bias allows for a relatively high gate voltage to be applied to the nMOS transistor enabling the nMOS transistor to be biased to optimum conditions for bipolar snapback.

Abstract: An ESD protection circuit layout. The ESD protection circuit layout has a first ESD protection device, a second ESD protection device, a first CDM ESD protection device, a second CDM ESD protection device, a first charge flow prevention device, a PMOS transistor, an input resistor, an NMOS transistor, a second charge flow prevention device and a substrate resistor. Charges within an integrated circuit device are discharged through a discharging loop comprising of the first CDM ESD protection device and the second CDM ESD protection device. Ultimately, the integrated circuit device is protected against CDM ESD and electrical latch-up within the integrated circuit is also minimized.

Abstract: A bus coupling includes an amplitude-controlled transmission circuit for generating a substantially rectangular active pulse for a transmission pulse including an active pulse and an equalizer pulse for a bus system which guides alternating voltage data and direct voltage in order to prepare a vehicle wiring system voltage for user terminals, in particular for the bus of the European Installation Bus Association. The transmission circuit operates with a transmission circuit operates with a transmission stage which includes as a transmission transistor, a transmission valve functioning as a transistor in the transmission circuit. Depending on the function, the selection line of this transmission circuit is reduced in terms of the control signal by a transistor of the inverse type to the transistor in the collector circuit as reducing transistor.

Abstract: A double-gated low power active clamp circuit for digital circuits includes a first double-gated MOSFET serially connected between an upper power supply voltage and an input terminal to be clamped, and a second double-gated MOSFET serially connected between a lower voltage power supply and the input terminal. The voltages at the gates of the first and second double-gated MOSFETs are held at constant reference voltages by a single or double reference circuits. The clamping action can be switched on or off. The double-gated active clamping network can be implemented with a single power supply voltage, or with multiple power supply voltages. The use of the back gates of the double-gated active clamping network enables additional clamping and ESD protection for smaller generations of transistors, such as, those having dimensions below 0.1 micron. The device is particularly suited for use with dynamic threshold double-gated silicon-on-insulator, FINFET, and bulk triple well technologies.

Abstract: The present invention relates to a bonding option circuit and a multi-level buffer that generates a plurality of selection signals from a single selective condition applied to a bonding pad to reduce the number of required bonding pads and buffers for a semiconductor device. A multi-level buffer according to the present invention can include a variable voltage divider, a comparator circuit and a logic signal generator. The variable voltage divider produces a first voltage, a second voltage, and a third voltage having voltage levels that are changed in accordance with conditions applied to a pad preferably when the variable voltage divider is activated by a power-up signal. The comparator circuit preferably generates a first comparison result and a second comparison result by being activated by the power-up signal and comparing the first to third voltages. The logic signal generator produces a first buffer output signal and a second buffer output signal.

Abstract: An integrated circuit is disclosed in which a steering diode is coupled between an input bond pad and a ground bond pad. The steering diode is reverse biased when a voltage applied to the input bond pad exceeds the voltage at the ground bond pad. A circuit coupled between the input bond pad and the ground bond pad includes a transistor having a first electrode coupled the input bond pad and a second electrode coupled to the ground bond pad. There may be other circuit elements between the emitter and the ground bond pad. At least two series coupled diodes are coupled between the input bond pad and the ground bond pad. The at least two series coupled diodes provide ESD protection to the transistor and circuit coupled between the input bond pad and the ground bond pad.

Abstract: In the high side switch type of electrical load driving circuit, wherein an N channel MOS transistor is provided on the circuit for supplying power to the electrical load, a zener diode is provided between the drain and the source of the MOS transistor to protect the MOS transistor. A load is provided between the gate and the ground to protect the MOS transistor. In this circuit, when a positive high voltage is induced on the side of the electrical load, the zener and a parasitic diode of the MOS transistor flows forward currents which absorb the high voltage noise. When a negative high voltage noise is induced from the side of the electrical load, a breakdown current flows through the zener diode, so that the voltage difference between the drain and source is clamed to a predetermined voltage. Then, the diode turns on the MOS transistor. Thus, the MOS transistor can be surely protected from high voltage noises without increasing the current capacities of elements for the protection circuit.

Abstract: The purpose of the present invention is to provide a clamping circuit which has a simple circuit design, with which the clamping voltage range can be easily adjusted, and which can operate at reduced power consumption, as well as interface circuit that makes use of the clamping circuit. NMOS transistor NT1 and diode D1 are connected in series between the feed line of power source voltage Vcc and input terminal Tin, and diode D2 and PMOS transistor PT1 are connected in series between input terminal Tin and ground voltage GND. The divider voltages VND1, and VND2 obtained from resistive elements R1, R2 and R3 connected in series are applied to the control terminals of transistors NT1 and PT1, respectively. Also, transistor NT2 is connected in parallel to resistive element R2. By means of control voltage VB input to the control terminal of NT2, the divider voltages are controlled, and the range of the clamping voltage can be controlled.

Abstract: A variable attenuator formed from a combination of PIN diodes is provided. The PIN diodes may be coupled in a “T,” “p” or other appropriate configuration. At radio frequencies (RF), a PIN diode acts as a variable resistor with a resistance value based on the bias current of the PIN diode. To control the attenuation level of the variable attenuator, the bias current of the PIN diodes are selectively adjusted. Digital values relating to selected bias currents, and thus selected attenuation levels, are stored in a memory. These digital values are provided as control signals that set the bias current levels for the PIN diodes. The bias current levels control the attenuation level of the variable attenuator.

Abstract: An insulated-gate transistor signal input device includes an insulating substrate, a first clock line formed on the insulating substrate to receive a clock signal externally supplied, a clock buffer formed on the insulating substrate to process the clock signal supplied from the first clock line, a second clock line formed on the insulating substrate to input a signal obtained from the clock buffer to a shift register serving as a load circuit formed on the insulating substrate. The insulated-gate transistor signal input device further includes a first protection diode circuit connected to the first clock line to remove electrostatic charge from the first clock line, and a second protection diode circuit connected to the second clock line to remove electrostatic charge from the second clock line.

Abstract: An indirect current sensing circuit and method for current limiting output driver circuitry is disclosed. The present invention is capable of preventing device damage and circuit disruption by maintaining output voltage signal integrity and consuming negligible power. Furthermore, the indirect current sensing circuit and method is independent of semiconductor process variations and thus is more reliable over prior art current sensing techniques. The indirect current sensing circuit and its method of current limiting, according to the present invention, can reliably drive transmission lines in networking system and communication applications.

Abstract: A voltage reference overshoot protection circuit senses unwanted ringing voltage levels in a driven device such as a backplane and controls the gate voltage to a voltage level control transistor such that a ringing output signal produced by an associated output driver is reduced in response to a control signal dependent on the ringing voltage level.

Abstract: The present invention relates to a circuit for protecting inputs and outputs on semiconductor devices. The protective circuit is particularly useful on high-speed inputs or outputs (such as in radio frequency applications where signal frequency is on the order of 100 MHz or greater and where it is necessary to minimize capacitive loading. Briefly, the present invention utilizes two FETs to shunt harmful electrostatic charges to a low impedance power bus and protect input and output circuit elements from damage or degradation. When a high voltage transient surge is detected, the drain-gate capacitance of one of the FETs couples the voltage to the gate electrode and biases one of the two transistors in the low impedance state so that the surge is absorbed without damage to the input or output circuit. Significantly, the capacitive loading of the protection circuit of the present invention is typically a fraction of a picoFarad and more particularly on the order of several hundred femtofarads.

Abstract: The present invention provides an improved high voltage protection integrated circuit (IC) input buffer. An IC includes a number of circuit elements and an input pin. Each of the circuit elements can tolerate a process dependent maximum voltage magnitude. The input pin can be provided with a voltage magnitude that is larger than the process dependent maximum voltage magnitude of individual circuit elements. The circuit elements include a subset of internal circuit elements and a subset of input buffer circuit elements. The input buffer circuit elements couple the internal circuit elements to the input pin, and are intercoupled in accordance with a predetermined topology to accept the larger voltage magnitude provided to the input pin without damaging the circuit elements.

Abstract: An ESD protection circuit comprising a substrate having a first conductivity type, a well region having a second conductivity type, a first doping region having the first conductivity type, and a second doping region having the second conductivity type. The substrate is coupled to the reference potential, the well region is formed on the substrate and electrically coupled to the node, the first doping region is electrically floated on the surface of the well region, and the second doping region is disposed on the substrate and electrically coupled to the reference potential. Moreover, the electrostatic discharge current of the node provides a voltage with sufficient magnitude to breakdown the conjunction interface between the well region and the substrate, also triggering a BJT comprising the well region, substrate and the second doping region for dissipating the electrostatic discharge current.

Abstract: Circuitry for amplifying a single-ended analog sensor output includes a field effect transistor (FET) having a gate connected to a first end of a capacitor, the second opposite end of which is connectable to the sensor output. The gate of the FET is also connected to a first end of a resistor and to a cathode of a diode. The anode of the diode, the opposite end of the resistor and the drain of the FET are connectable to a ground reference, and the source of the FET defines an amplifier output that is connectable to a constant current source. The capacitor, resistor and diode are operable to bias the FET to thereby prevent clipping of the output signal at the amplifier output. A high-pass filter is also provided at the second end of the capacitor, and a number of diodes are preferably included for providing for amplifier input protection, electrostatic discharge protection and output DC overvoltage protection.

Abstract: An off-chip driver circuit having a set of input terminals and an output terminal, a pull-up transistor having a controllable path connected between a first power supply and the output terminal of the off-chip driver circuit, a pull-down transistor having a controllable path connected between a second power supply and the output terminal of the off-chip driver circuit, a first controllable path for applying a first voltage at one of the input terminals to a control terminal of the pull-up transistor, the first controllable path functioning in response to voltages at the output terminal below a first value, a second controllable path for applying a second voltage greater than the first voltage to the control terminal of the pull-up transistor, the second controllable path functioning in response to voltages at the output terminal above the first value.

Abstract: The input circuit of the present invention includes an NMOSFET. One terminal of the NMOSFET is connected to an input terminal and the gate of the NMOSFET is connected to a power supply terminal via a clamping circuit. A signal, received at the one terminal of the NMOSFET with an amplitude equal to or larger than that of a power supply voltage, is output through the other terminal of the NMOSFET with an amplitude equal to that of the power supply voltage. The input circuit further includes: a gate controller, which is connected to the other terminal of the NMOSFET; and a PMOSFET. One terminal of the PMOSFET is directly connected to the other terminal of the NMOSFET and the gate of the PMOSFET is also connected to the other terminal of the NMOSFET via the gate controller. If the voltage at the other terminal of the NMOSFET is at a high level, the gate controller turns the PMOSFET ON. Alternatively, if the voltage at the other terminal of the NMOSFET is at a low level, the gate controller turns the PMOSFET OFF.

Abstract: A Semiconductor integrated circuit with a protection circuit against electrostatic discharge. A clamping element is connected with MIS transistor to prevent the breakdown under the charged device model. A parasitic bipolar transistor, a MOS transistor or MIS transistor whose gate is composed of an insulating film thicker than that of the transfer gate, can be used as the clamping element.

Abstract: An electrostatic protection circuit protects an internal circuit from electric charge which is applied via an electrode pad. The above electrostatic protection circuit mainly includes a protection transistor portion, a second transistor and a third transistor. In this case, the protection transistor portion includes a first transistor having a first gate electrode in order to protect the internal circuit by discharging the electric charge. The second transistor controls so as to keep the first gate electrode into a floating state before the power source is introduced. The third transistor gives a predetermined potential into the first gate electrode.

Abstract: To provide a pull-up circuit and a pull-down circuit having the same withstand voltage performance to other neighboring circuit elements without needing special layout consideration, a pull-up circuit of the invention having an nMOS pull-up transistor (N1) connected between a first node (A2) and a pull-up node (OU) comprises a pMOS transistor (P2), a drain of said pMOS transistor (P2) connected to the first node (A2), a source and a substrate of said pMOS transistor (P2) connected to a positive power supply (Vcc), and a gate of said pMOS transistor (P2) controlled with a pull-up signal; and a pull-down circuit of the invention having a pMOS transistor (P1) connected between a first node (B2) and a pull-down node (OD) comprises an nMOS transistor (N2), a drain of said nMOS transistor (N2) connected to the first node (B2), a source and a substrate of said nMOS transistor (N2) connected to a negative power supply (GND), and a gate of said nMOS transistor (N2) controlled with a pull-down signal.

Abstract: An integrated circuit is provided with electrostatic discharge (ESD) protection circuitry (120) A substrate region in the semiconductor substrate is enclosed by a ring of highly doped region (350). An NMOS ESD protection transistor (N1) with its backgate in the enclosed substrate region can be voltage pumped by pump circuitry (N2) in order to trigger bipolar conduction of the ESD protection transistor at a lower voltage. Control circuitry (304) is connected to the signal bond pad and to the gate of amplifier circuitry (P1) to provide a voltage pulse in response to an ESD zap applied to the signal bond pad. PMOS amplifier circuitry (P1) provides an amplified voltage pulse to the pump circuitry with a magnitude approximately equal to the ESD potential on the signal pad so that a strong pump current is provided to the highly doped ring.

Abstract: An error amplifier circuit is provided having a pair of current mirror transistors driven by a pair of current sources, where one of the current mirror transistors operates at a lower current density than the other, and further having a resistor in an emitter circuit of the transistor operating at the lower current density and a summing node in the emitter circuit between the emitter of the one transistor and the resistor. A feedback circuit including a second resistor and a base-emitter circuit of a third transistor is in series between a feedback node coupled to the base of the feedback transistor and the summing node, such that a current from the feedback circuit is summed with the current conducted by the emitter of the one transistor. The error amplifier is balanced when the voltage at the feedback node is equal to a predetermined voltage, which can have substantially zero temperature coefficient at a voltage as low as one bandgap voltage.

Abstract: An apparatus (100) includes a differential processing circuit (135) responsive to an input signal with first and second signal components, and a signal imbalance suppressor (130) that preprocesses the input signal, prior to input to the differential processing circuit, to remove amplitude and/or phase imbalances that exist between the first and second signal components, in order to reduce even order distortion generation within the differential processing circuit.

Abstract: A gain stage circuit includes a first transistor Q.sub.3 having a control node coupled to a bias node V.sub.B1 ; a second transistor Q.sub.2 having a control node coupled to the bias node V.sub.B1 ; a third transistor Q.sub.1 coupled in series with the second transistor Q.sub.2 and having a control node coupled to an input node V.sub.IN ; a fourth transistor Q.sub.5 matched to the second transistor Q.sub.2 and having a control node coupled to the bias node V.sub.B1 ; a current subtracting circuit 22 coupled to the second and fourth transistors Q.sub.2 and Q.sub.5 ; and a quiet current generator 20 coupled to the current subtracting circuit 22, the current subtracting circuit 22 subtracts a current in the fourth transistor Q.sub.5 from a quiet current in the quiet current generator 20.

Abstract: The present invention provides an integrated circuit having an operating voltage adaptable buffer, capable of operating in different voltage signaling environments, which includes a control circuit that provides a clamping function to the signaling path under prescribed operating conditions and which also reliably biases the p-type transistor substrate voltage of the buffer to the most positive voltage seen by the buffer under all operating conditions occurring on the signaling path, thereby protecting the p-type transistors.

Abstract: In order to reduce the amplitude of an overshoot/undershoot voltage and clamp a signal at a constant voltage level over a wide temperature range, a bias voltage having a clamping element operating at a boundary region between ON and OFF states is applied to a control electrode node of the damping element. When the difference between the voltage of a signal line and the bias voltage is higher than a P-N junction built-in voltage, the clamping element is rendered conductive to clamp the overshoot/undershoot voltage.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: two transistors coupled together in the integrated circuit so that upon the application of complementary voltage signals, electrical charge is substantially evenly distributed between output nodes. Briefly, in accordance with one more embodiment of the invention, an integrated circuit includes: a charge recycle circuit including two transistors. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: a charge recycle circuit including a first and second transistor coupled so as to respectively receive complementary voltage signals at the control voltage port of the first and second transistors. The transistors have a threshold voltage level different from the threshold voltage level of other transistors coupled to the charge recycle circuit.

Abstract: A field device electrostatic discharge protective circuit is described. The field device electrostatic discharge protective circuit comprises an N-type FET, an NMOS, an impedance device and a resistor. The gate and the drain of the N-type FET connect to the input port. The drain of the NMOS connects to the internal circuit. The source of the NMOS connects to ground. The gate of the NMOS connects to the source of the N-type FET. The impedance device is set between the source of the N-type FET and the ground. The resistor is set between the drain of the N-type FET and the drain of the NMOS.

Abstract: An output buffer including transistors which tolerate a maximum gate to source, gate to drain, or drain to source voltage ("the maximum tolerable voltage"), such as 2.7 volts, the transistors being configured to produce an output voltage significantly higher than the maximum tolerable voltage. The output buffer includes pull up transistors having source to drain paths connected in series to connect a voltage supply higher than the maximum tolerable voltage to the buffer output. The buffer further includes pull down transistors having source to drain paths connected in series to connect the buffer output to ground. The buffer further includes power supply circuitry to apply gate voltages to the pull up and pull down transistors so that the voltage potential from the source to drain of each of the pull up and pull down transistors is less than the maximum tolerable voltage.

Abstract: A SUB wiring provided outside of a common discharge line formed on outer periphery of a chip in parallel to the latter. To the common discharge line, only voltage clamping elements and diode elements as electrostatic protection elements are connected. The common discharge line is in floating condition for rising withstanding voltage. On the other hand, to the SUB wiring, additional circuits, such as BBG circuit and so forth, consisting of transistors are connected to connect the latter to the substrate. With these two wirings, the width of the common discharge line can be made narrower to limit an increase of a chip area. By this, it is possible to improve resistance to electrostatic breakdown without increasing chip area.

Abstract: An input circuit is made up of an external signal input portion which inputs an external signal, a voltage level converting circuit which has an input terminal for inputting a signal from the external signal input circuit and which has an output terminal for outputng the signal to the internal circuit after a voltage level was converted, a first power supply terminal which has a first potential for driving the voltage level converting circuit, a second power supply terminal which has a second potential for driving the voltage level converting circuit, and a noise control portion which couples to the input terminal of the voltage level converting circuit, which controls a noise from the first power supply terminal and/or the second power supply terminal, and which has a first capacitor. Accordingly, the input circuit could be applied the stable signal to the internal circuit.

Abstract: An electrostatic discharge protection circuit immune to latch-up during normal operation is disclosed. The ESD protection circuit is positioned at an IC pad for protecting an internal circuit within an integrated circuit from ESD damage. The electrostatic discharge protection circuit comprises a silicon-controlled rectifier and an ON/OFF controller. The silicon-controlled rectifier coupled between the IC pad and a grounding node to form an ESD path, wherein the ON/OFF controller is arranged in the conduction path. During normal operation the ON/OFF controller disconnects the ESD path so as to avoid latch-up even if noise interference happens.

Abstract: A square-law clamping circuit (99, 120) sinks a current from an input/output terminal proportional to a square of a difference between a voltage thereon and a reference voltage. A first MOS transistor (130) has a source for receiving the reference voltage, a gate, and a drain coupled to its gate. A current source (134) coupled to the drain of the first MOS transistor (130) sources a predetermined current therefrom. A second MOS transistor (132) has a source providing the input/output terminal (100, 121), a gate coupled to the drain of the first MOS transistor (130), and a drain. A current sink (135) coupled to the drain of the second MOS transistor (132) sinks a current therefrom.

Abstract: A switching circuit has switching elements for passing-through or cutting-off signals of a positive pulse, which is a rectangular pulse rising from a low level and falling after having kept a high level for a certain time as a high voltage input signal, and a negative pulse, which is a rectangular pulse falling from a high level and rising after having kept a low level for a certain time, the switching circuit being applied to a capacitive load driving device.

Abstract: The present invention teaches a variety of filter circuits for protecting against transient electrical pulses such as those caused by electrostatic discharge (ESD) events. One aspect of the present invention teaches an integrated circuit package having primary circuitry, an ESD protection device, a filter circuit, and a conductive lead arranged to couple a point external to the integrated circuit package to a point internal to the integrated circuit package. The ESD device, coupled in series between the conductive lead and a ground reference, can limit the voltage magnitude of a transient electrical pulse occurring upon the conductive lead. The filter circuit is operable such that the voltage magnitude of an electrical signal generated at the filter circuit output is less than the voltage magnitude of the certain transient electrical pulse itself. One preferred filter circuit has two resistors R.sub.1 and R.sub.2, two capacitors C.sub.1 and C.sub.2, and two transistors Q.sub.1 and Q.sub.2.

Abstract: A circuit structure which avoids a latchup effect. An N-well is formed in a P-type substrate. An N-type contact is formed in the N-well. A PMOS is located on the N-well. A gate of the PMOS connects to an input terminal and a source region of the PMOS connects to a voltage source. A first NMOS and a second NMOS are located on the P-type substrate. A gate of the first NMOS connects to the input terminal, a source region of the first NMOS connects to a ground terminal, and a drain region of the first NMOS connects to an output terminal and a drain region of the PMOS. A gate of the second NMOS connects to the output terminal, a source region of the second NMOS connects to a voltage source, and a drain region of the second NMOS connects to the N-type contact.

Abstract: A clamping circuit (100) is provided for controlling an external switch, using a control signal, in response to monitoring a voltage at a first node. When the voltage at the first node exceeds a certain voltage, the clamping circuit (100) closes the external switch to complete a current path to reduce the voltage at the first node. The clamping circuit (100) includes a voltage divider circuit, a first device, a second device, a current mirror circuit, and a switch. The voltage divider circuit, which may be implemented using a resistor (30) and a resistor (32), is coupled between the first node and a fourth node and generates a divider voltage at a third node that is proportional to the voltage at the first node. The first device and the second device may be implemented using a first bipolar junction transistor (38) and a second bipolar junction transistor (40), respectively.

Abstract: A circuit (100) has a pull-up transistor (110), a pull-down transistor (120), an input driver (200). The pull transistors (110, 120) pull an output line (102) to first or second reference lines (101, 103). The output line (102) can assume a potential higher than the potential at the first reference line (101). The circuit (100) further comprises protection transistors (150, 160, 170, 180). The protection transistors compare the potential at the output line (102) with the potential at the first reference line (101). The protection transistors keep a substrate line (106) of the pull-up transistor (110) at the potential of the output line (102) or at the potential of the first reference line (101), whichever is higher.

Abstract: In a circuit (10), a first N-FET (N1) and a second N-FET (N2) are coupled serially between a node (15) and ground (93). The circuit (10) accommodates a first excursion (85) of a first signal (IN) at the gates of the first N-FET (N1) which is higher than the maximum allowable drain-source voltage for N-FETs. The voltage of a second signal (OUT) between the node (15) and ground (93) is distributed across the first and the second N-FETs (N1, N2). The gate voltage of the second N-FET (N2) is not constant, but controlled by a control circuit (20) receiving signals the first signal (IN) and, optionally, the second signal (OUT). With the variation of the gate voltage for the second N-FET (N2), the size of both transistors (N1, N2) can be reduced and the fall time (T.sub.F) of the second signal (OUT) can be reduced.

Abstract: A dual-node capacitor coupling technique is used to lower the trigger voltage and to improve the uniform turn-on of a multi-finger MOSFET transistor. Preferably, each MOSFET is an NMOS device. Specifically, each NMOS device includes a capacitor that is connected between the gate of the NMOS device and the pad terminal. A first resistor is connected between the gate and the p-well, while a second resistor is connected between the p-well and the grounded source. For a positive ESD pulse to VSS, the p-well is pulled up to approximately 0.7 V during the initial ESD event, such that the source junction is forward biased and that the trigger voltage of the NMOS device is lowered. At the same time, the gate voltage is coupled within the range of approximately 1 to 2 V to promote the uniform turn on of the gate fingers of the NMOS devices during the initial ESD event.

Abstract: An integratable circuit configuration for stabilizing an operating point of a transistor by negative feedback includes first, second, third and fourth terminals. The fourth terminal is connected to a fixed ground potential, and the first and fourth terminals have a supply voltage source connected therebetween. A first transistor to be stabilized by negative feedback has a collector connected to the second terminal, an emitter connected to the fourth terminal, and a base connected to the third terminal. A second transistor has an emitter connected to the second terminal, a collector connected to the third terminal, and a base. A first resistor is connected between the first terminal and the second terminal. A second resistor is connected between the base of the second transistor and the fourth terminal. A series circuit has at least one first diode and one second diode and is connected between the first terminal and the base of the second transistor.

Abstract: A first MOS transistor (5) is provided between a power source terminal and an input terminal (3). A second MOS transistor (6) is provided between a ground terminal (2) and the input terminal (3). The gate of the first MOS transistor (5) is electrically connected to a node (8) and a resistor (9) is electrically connected between the node (8) and another ground terminal (2). The gate of the second transistor (6) is electrically connected to the ground terminal (2). When negative pulse-shaped static electricity is applied to a circuit constructed as described above, the potential applied to the gate of the first MOS transistor (5) is limited low by a voltage drop developed across the resistor (9). Therefore, the current flowing between the source and drain of the first MOS transistor (5) can be controlled low and a substrate current produced due to impact ionization can be prevented from flowing. It is thus possible to obtain a stabler operation of a semiconductor integrated circuit device.

Abstract: A low-voltage output driving circuit capable of preventing the generation of leakage current. The circuit includes a transfer gate GT installed between the output S.sub.2 of a first CMOS inverter INV.sub.C1 and the node S.sub.1 at the gate of an MOS transistor PT.sub.3 for active pull-up. At the same time, a reference voltage V.sub.REF and a voltage level V.sub.OUT, which corresponds to the voltage level of the output line of the signal S.sub.OUT, are compared by a comparator CMP. When the voltage V.sub.OUT is lower than the reference voltage V.sub.REF, the transfer gate GT is set to the ON state, and the output of the first CMOS inverter INV.sub.C1 is sent to the gate of the transistor PT.sub.3 for active pull-up. The comparator CMP is installed so that when the voltage level V.sub.OUT is higher than the reference voltage V.sub.REF, the output of the first CMOS inverter INV.sub.C1 is prevented from reaching the gate of the transistor PT.sub.3 for active pull-up.

Abstract: A mode setting circuit for generating a mode setting signal for selecting a particular operational mode in response to an input signal from a mode setting pad. The mode setting circuit includes a driver circuit for generating a mode setting signal in response to an input voltage of a mode setting pad, a first pull-down transistor for discharging a voltage at the mode setting pad, and a second pull-down transistor for discharging the voltage at the mode setting pad in response to a signal from the driver circuit. Such mode setting circuit can prevent a misoperation which may occasionally be caused by ground noises when the mode setting pad is not coupled to the supply voltage terminal. Thus, the reliability of the manufactured goods will be increased.

Abstract: This invention provides a circuit and method to replace the passive resistive or statically biased active load devices with dynamically biased active load devices. This allows the load devices to present an effective load which varies depending on the state of the circuit output. The effective load and the time rate of change of the effective load can be dynamically optimized to improve circuit performance with changing conditions. The effective load is varied according to the state of the circuit by the use of time-delayed negative feedback. The biasing of the load devices is also capable to control the logic swing of the circuit. A bias generating circuit employing a dynamically biased active load is described. This provides a method for a family of logic circuits, especially CML circuits, to operate at low voltage and low power at high switching speeds, having symmetrical rise and fall times and well defined logic signal swings.

Abstract: A high voltage generator circuit comprises a boosting circuit, limiter circuit, and a bypass circuit. When a supply voltage is inputted into the boosting circuit, a high voltage is generated and supplied to the limiter circuit. When the high voltage generated by the boosting circuit exceeds a limit voltage of the limiter circuit, the limiter circuit operates and the output voltage of the boosting circuit is thus maintained at a constant value. When the output voltage exceeds the limit voltage of the limiter circuit and an output current of the boosting circuit exceeds a reference value, a portion of the output current of the boosting circuit equivalent to a difference between the output current and a predetermined value is bypassed and discharged by the bypass circuit stated above.

Abstract: A circuit for limiting the output voltage from a power transistor connected in series with a resonant load between a voltage supply and a voltage reference, ground, is disclosed. The circuit includes a semiconductor junction element, in particular a diode of the SCR type, having an anode terminal connected to the voltage supply, a cathode terminal connected to a common circuit node between the power transistor and the resonant load, and a control terminal connected to a reference voltage of predetermined value. The reference voltage can be constructed by using a resistor connected in series with a diode across the voltage supply. The SCR diode is constructed using the parasitic PNP-NPN transistors which exist in the structure of the power transistor.