Abstract: An output driver for high speed integrated circuits includes a static driver portion and a transient driver portion. The static driver size can be adjusted to satisfy the minimal requirements for maintaining output DC voltage levels. The transient drivers include a feed-back control from the output voltage node. During a transition, the transient buffer control will sense the output level and feedback to turn off the transient driver whenever the output level rises/falls across the trip point. Accordingly the di/dt noise will drop quickly once the output has reached the trip point. The transient drivers can be larger to speed up switching speed. The buffer can use single power and ground pins or multiple power/ground pins.

Abstract: An intelligent bias voltage generating circuit capable of providing an electronic device with a reliable bias signal includes a power input terminal which is electrically connected to a power generating device for providing a power input, and a bias voltage generating circuit which is electrically connected to the power input terminal for responding to power fluctuations and generating a bias voltage signal output by a multi-section linear variation method.

Abstract: A parallel connection of an enhancement type nMOS transistor and an enhancement type pMOS transistor is connected between an input terminal receiving a clock signal and a capacitor. The pMOS transistor is turned on and off in dependece on an output of a power supply voltage detector, so that a signal transmission path between the input terminal and the capacitor, as the clock signal is at a high level, has a switched position at a side of the nMOS transistor when the power supply voltage is high, and a switched postiion at a side of the pMOS transistor when the power supply voltage is low. Due to a threshold drop effect of the nMOS transistor, a signal amplitude of a high level is limited to an output level of a limiter minus a threshold voltage of the nMOS transistor, reducing a charge-discharge current of the capacitor.

Abstract: A semiconductor unit is composed of an analog unit, a digital unit, a signal line through which a signal is transmitted from the analog unit to the digital unit, an electric source line Vdd1 through which a high voltage is applied to the analog unit, an electric source line Vdd2 through which the high voltage is applied to the digital unit, an electric source line Vss1 through which a low voltage is applied to the analog unit, an electric source line Vss2 through which the low voltage is applied to the digital unit, and a protective circuit arranged between the electric source lines Vss1 and Vss2. The protective circuit functions to electrically connect the electric source line Vss1 and the electric source line Vss2 in cases where an electric potential difference between the electric source lines Vss1 and Vss2 exceeds a prescribed value. Similar protection can be provided between the high voltage source lines Vdd1 and Vdd2 or between the signal line and the second source lines Vdd2 and Vss2.

Abstract: An apparatus for regulating a substrate voltage in a semiconductor device having a substrate voltage regulator for controlling generation of a substrate voltage so as to supply a pre-set substrate voltage to a substrate, including: a stack of a plurality of resistors being connected in series with each other and a plurality of switches being connected in parallel to corresponding resistors other than a resistor connected to a power supply voltage for decreasing an external voltage applied to one end thereof to a predetermined level; a first transistor having a first electrode connected to another end of the stack of the plurality of the resistors, a gate connected to ground and a second electrode connected to the substrate, for being controlled by a substrate voltage of the substrate; and a second transistor having a gate to which the inverse of a signal outputted from a connecting point between the other end of the stack of the plurality of the resistors and the first transistor is applied, and first and sec

Abstract: In a sense amplifier circuit, a CMOS inverter is connected to a power supply voltage and inverts and amplifies a voltage on a digit line connected to a selected memory cell of a memory cell section to generate a gate control signal. The first transistor is connected to the digit line and controls current flowing through the digit line in response to the gate control signal. A data of the selected memory cell is outputted from an output of the first transistor. A stabilizing section stabilizes an operation of the CMOS inverter such that a same operation of the CMOS inverter can be performed independent from change of the power supply voltage.

Abstract: An apparatus for switching an inductive load includes a MOSFET switch and provides for limiting a voltage across the load during switching-off of the latter. One or two clamping circuits are used without zener diodes and with different, temperature-independent clamping voltages for the purpose of rapid demagnetization of the load in a constant demagnetization time.

Abstract: A network circuit has a single port device 28 having a high impedance output node 42 when the single port device 28 is powered down; and a multi port device 50 having a bias node 60 coupled to the output node 42.

Abstract: An object is to provide a semiconductor device having an internal power supply circuit capable of supplying stable internal power supply voltage while not increasing layout area. A differential amplifying circuit in a voltage down converter controls potential level V.sub.OUT of the drain of transistor P14 such that it attains the reference potential V.sub.REF. If the potential V.sub.OUT increases, the gate potential of transistor N12 increases because of coupling function of a capacitance C2, and the transistor is rendered conductive. Thus the potential level V.sub.OUT is pulled down. By contrast, if the potential level V.sub.OUT lowers, transistor P12 is rendered conductive, and the potential level V.sub.OUT is pulled up.

Abstract: The invention relates to a system for transmitting binary signals over a signal line to a signal detecting device, in which a DC source is temporarily connectable to the signal line for generating binary signals. A discharge circuit is connected to the signal line. In order to keep the power loss very low in such a system, discharge circuit (7) contains a switchable current sink (8) connected to a signal line (3). Discharge circuit (7) also has a threshold value determination device (19) connected to signal line (3) in parallel with switchable current sink (8). Output (26) of threshold value determination device (19) is connected with a control input (17) of switchable current sink (8).

Abstract: A DC clamping circuit acting on an input signal to clamp the input signal to a voltage reference is disclosed. The DC clamping circuit comprises a comparator providing an output that decreases whenever the input signal is less than the output. A capacitor is connected to the output of the comparator for absorbing the charge output by the comparator. Finally, a differential amplifier is provided for subtracting the output of the comparator from the input signal and for adding the voltage reference.

Abstract: A protected switch has a power semiconductor device (P) having first and second main electrodes (D and S) for coupling a load (L) between first (2) and second (3) voltage supply lines, a control electrode (G) coupled to a control voltage supply line (4) and a sense electrode (S1) for providing in operation of the power semiconductor device a sense current that flows between the first (d) and sense electrodes (S1) and is indicative of the current that flows between the first (D) and second (S) main electrodes. A control arrangement (S) has a sense resistance (R4) coupled to the sense electrode (S1) and across which a sense voltage is developed by the sense current (I.sub.3). A control semiconductor device (M3) has its main electrodes coupled between the control electrode (G) and the second (S) main electrode of the power semiconductor device (P).

Abstract: A semiconductor switch including a plurality of die assembled hybrid circuit packages. Each package includes a relatively large number of parallely connected semiconductor switch devices, more particularly metal oxide semiconductor field effect transistors (MOSFETs). An active snubber circuit is connected to the MOSFETs in order to remove the requirement for current sharing during circuit interruption where the MOSFETs turn-off. Each MOSFET package furthermore includes metallic arc barriers between MOSFETs to prevent an arc from propagating from one failed MOSFET to neighboring MOSFETs. Also all of the MOSFETs are turned on momentarily to extinguish arcs whenever the semiconductor switch is in an open or non-conducting condition and a current flow is detected. Clamping of the gate electrode drive bus of the MOSFETs is additionally provided to ensure fusing of gate bonding wires coupling the gate electrodes of the respective MOSFETs to the gate drive bus.

Abstract: A protection circuit for a CMOS integrated circuit which is biased with a first voltage and a second voltage includes a voltage divider, a voltage comparator, and a switch. The full level of the first voltage is higher than that of the second voltage. The voltage divider divides the first voltage to be compared with the second voltage in the voltage comparator. The switch is controlled by the voltage comparator. The switch isolates the CMOS integrated circuit from the first voltage when the first voltage is lower than the second voltage. Therefore, no forward bias current path exists in the CMOS integrated circuit even though the voltage levels of the first and second voltages reach their full levels at different times.

Abstract: An input circuit which prevents erroneous operation caused by noise. An input stage has a NMOS transistor N11 and a PMOS transistor P11. A NMOS transistor N12 is connected in series between a ground line and the source of the NMOS transistor N11. A PMOS transistor P12 coupled to a voltage supply line V.sub.cc acts as a current control element. NMOS transistors N13 and N14 are connected in series between the ground line and the drain of PMOS transistor P12. Inverters IV11 and IV12 delay the voltage of an intermediate output node S11 and supply it to the gate of NMOS transistor N13. The gate of NMOS transistor N12 is coupled to a node S13, the gate of NMOS transistor N14 is coupled to the input line for an input signal IN, and node S13 is formed to function as a voltage sensor with respect to the ground.

Abstract: An input protection circuit for a semiconductor memory device senses when the level of an external input signal drops below a reference voltage corresponding to a predetermined logic level, thereby enabling instant correction. The input protection circuit is interposed between an external power voltage terminal and an input terminal of the input buffer, and the external power voltage is transferred to the input terminal of the input buffer when the level of the external input signal applied to the input terminal drops below the predetermined logic level. The circuit includes an internal reference voltage generator which supplies a voltage having a level corresponding to the predetermined logic level and designed to compensate for a known device offset so that the external input signal applied to the input terminal can be instantly corrected.

Abstract: A bonding option circuit comprises a logic gate circuit connected between a bonding pad and a power supply voltage, a load capacitance connected between ground and the logic gate circuit, and an output stabilizer circuit having an input connected to the bonding pad and an output connected to an output terminal. The logic circuit is so configured that when the bonding pad is in a floating condition, the logic circuit connects the bonding pad to the power supply voltage, and when the bonding pad is bonded to the ground, the logic circuit disconnects a current path between the bonding pad and the power supply voltage.

Abstract: A method and circuit for preventing forward bias of a collector-substrate diode in an integrated circuit with a bipolar transistor where a load driven by the transistor may be offset from a reference voltage, such as circuit ground, by a varying voltage offset. The difference between the bipolar transistor collector voltage and the reference voltage is sensed, and the bipolar transistor base current is varied responsive to the sensed difference so that the base current is zero when the collector voltage is equal to the reference voltage, whereby the collector current will be less than .beta. times the base current when the emitter voltage is less than the reference voltage and the diode will not become forward biased.

Abstract: An FET with a lightly doped drain is connected between an input/output pad and ground and is protected from ESD at a pad by a structure that includes a resistor formed by the process step for the lightly doped drain. The resistor adjoins and interconnects a diffusion underlying the pad and the diffusion for the drain of the FET. A parasitic bipolar transistor is formed by the pad diffusion, the source diffusion for the FET, and the intervening substrate. When an ESD voltage appears at the pad, the FET conducts in circuit with the resistor and the voltage drop across the resistor helps to protect the FET and to turn on this parasitic bipolar transistor (in preference to a parasitic bipolar transistor otherwise formed by the FET) and thereby hold down the ESD voltage at the pad and at the drain of the FET. The FET and resistor can be formed as a number of parallel connected FETs and resistors located symmetrically on opposite sides of the pad diffusion. Protection for an input inverter circuit is also provided.

Abstract: An electrostatic discharge (ESD) device includes a pair of depletion mode MOSFETs connected drain-to-drain in a series path between an input terminal and an output terminal, the gate of each MOSFET being connected to its source. A first diode having a relatively high breakdown voltage is connected between ground and the common drain terminal of the MOSFETs, and a second diode having a relatively low breakdown voltage is connected between ground and the output terminal of the device. The second diode breaks down during a relatively low, long-lived voltage spike (in an automobile, sometimes referred to as a "load dump"), while the second MOSFET saturates, limiting the size of the current through the second diode. The first diode breaks down during a large voltage spike of short duration, such as occurs from an ESD.

Abstract: An object of the present invention is to provide a power line connection circuit which obtains a desired turn-on resistance and a turn-off resistance without using a complex external circuit. The power line connection circuit provides a MOS transistor arranged in a power supply line, whose continuity is changed by applying a control signal from a control unit; a voltage conversion means for converting the voltage of the control signal; and a clamp means for clamping the converted voltage output from the voltage conversion means so as to have a predetermined voltage difference with respect to the voltage of said power supply line.

Abstract: An object of the present invention is to provide a buffer circuit little sensitive to a deviation from a threshold voltage of each of transistors. In order to achieve the above object, the present invention provides a typical buffer circuit comprising the following components.

Abstract: This invention provides circuits which provide stable internally derived voltages for mixed mode large scale integrated circuits having SRAM, DRAM, and the like. The circuits use a summation of threshold voltages of metal oxide semiconductor field effect transistors to clamp voltages and a level detection circuit to compensate for variation in the primary supply voltage. A load detection and feedback circuit using a parasitic bipolar transistor provides voltage stability over a wide range of loading conditions.

Abstract: A high voltage generator circuit comprises a boosting circuit, limiter circuit, and a bypass circuit. When a supply voltage is inputted into the boosting circuit a high voltage is generated and supplied to the limiter circuit. When the high voltage generated by the boosting circuit exceeds a limit voltage of the limiter circuit, the limiter circuit operates and the output voltage of the boosting circuit is thus maintained at a constant value. When the output voltage exceeds the limit voltage of the limiter circuit and an output current of the boosting circuit exceeds a reference value, a portion of the output current of the boosting circuit equivalent to a difference between the output current and a predetermined value is bypassed and discharged by the bypass circuit stated above.

Abstract: An input signal (IN) and a threshold signal (Vt) are coupled to an output terminal (2) via the base-emitter paths of first (Q1) and second (Q2) transistors having respective collector electrodes connected to a supply voltage source (3). The output terminal (2) is coupled to a source of reference potential (4) via a first resistor (Re) and is coupled via a second resistor (Rd) to a selected plate of a capacitor (C1) that is connected between the collector and base electrodes of the second transistor (Q2). Circuit impedances are scaled such that Re>Rd>R1 wherein Re and Rd are the values of the first and second resistors, respectively, and R1 is a component of the output impedance of the threshold signal source (5).

Abstract: This invention provides circuits which provide stable internally derived voltages for mixed mode large scale integrated circuits having SRAM, DRAM, and the like. The circuits use a summation of threshold voltages of metal oxide semiconductor field effect transistors to clamp voltages and a level detection circuit to compensate for variation in the primary supply voltage. A load detection and feedback circuit using a parasitic bipolar transistor provides voltage stability over a wide range of loading conditions.

Abstract: A circuit for limiting the output voltage from a power transistor connected in series with a resonant load between a voltage supply and a voltage reference, ground, is disclosed. The circuit includes a semiconductor junction element, in particular a diode of the SCR type, having an anode terminal connected to the voltage supply, a cathode terminal connected to a common circuit node between the power transistor and the resonant load, and a control terminal connected to a reference voltage of predetermined value. The reference voltage can be constructed by using a resistor connected in series with a diode across the voltage supply. The SCR diode is constructed using the parasitic PNP-NPN transistors which exist in the structure of the power transistor.

Abstract: An improved output driver circuit for a semiconductor integrated circuit device, wherein a stepped control voltage generation circuit is connected to the gate of a driving transistor for driving an output terminal DQ. The stepped control voltage generation circuit responds to an applied input data signal to provide a stepped control voltage changing in a stepped form including a plurality of steps to the gate of the driving transistor. The driving transistor therefore changes its state on a step by step basis from a cut off state to a conduction state. Thus, sharp change in output current flowing through the output terminal can be prevented, and noise caused by a parasitic inductance can be avoided, thus preventing an erroneous operation in the device.

Abstract: An integrated circuit output stage is intended for use with an operational amplifier. The output is capable of driving capacitive load to within a V.sub.SAT of the power supply rails. The complementary output transistors are driven by way of a combination of buffers and complementary differential amplifiers which act to bias the stage in class AB. The quiescent current is stabilized and controlled, in part, by simple resistor rationing. The output transistor saturation is sensed and a current limit is imposed so that hard saturation is avoided. Frequency compensation is achieved in a manner that responds to output transistor saturation so as to improve the high frequency transient response. Feedforward capacitors are also included to further improve high frequency response.

Abstract: An electrostatic discharge (ESD) device includes a pair of depletion mode MOSFETs connected drain-to-drain in a series path between an input terminal and an output terminal, the gate of each MOSFET being connected to its source. A first diode having a relatively high breakdown voltage is connected between ground and the common drain terminal of the MOSFETs, and a second diode having a relatively low breakdown voltage is connected between ground and the output terminal of the device. The second diode breaks down during a relatively low, long-lived voltage spike (in an automobile, sometimes referred to as a "load dump"), while the second MOSFET saturates, limiting the size of the current through the second diode. The first diode breaks down during a large voltage spike of short duration, such as occurs from an ESD.

Abstract: A storage charge reduction circuit for reducing the storage charge of a first bipolar transistor. The circuit includes a second field effect transistor connectable between the base of the first bipolar transistor and ground for conducting a compensation current from the base of the first bipolar transistor to ground. A third bipolar transistor is connected in series with a first resistor for conducting a first current from a first voltage supply through the first resistor to ground. Current mirror circuitry sets the gate-source voltage of the second field effect transistor so that the compensation current is proportional to the first current. The first current and the compensation current increase when temperature increases. In a preferred embodiment, the storage charge reduction circuit is used in a transmission line driver. The driver includes an output bipolar transistor connectable between the transmission line and ground for conducting current from the transmission line to ground.

Abstract: A high voltage circuit includes a first switching device for supplying one of a high voltage (V.sub.pp) and a low voltage (V.sub.cc) to a controlled path that includes a series connection of a control p-channel transistor and a protection p-channel transistor. A high voltage detector is utilized to determine whether V.sub.pp or V.sub.cc is applied to the controlled path. The high voltage detector also establishes a protecting condition for the protection p-channel transistor during V.sub.pp operation. On the other hand, the detector establishes a non-protecting condition during V.sub.cc operation, thereby rendering the protecting p-channel transistor transparent to circuit performance. A signal input switches the control p-channel transistor between on and off states.

Abstract: In order to prevent a malfunction caused by an electrical noise and limit an excessive main current at a high speed while cutting off the same to a value close to zero, the main current is regulated by an IGBT (1) which is connected with a load. A part of this main current is shunted to another IGBT (2). The as-shunted current flows through a resistor (3), to be converted to a voltage across the resistor (3). When the main current is excessively increased by shorting of the load or the like, this voltage exceeds a prescribed value so that a transistor (5) and a thyristor (7) enter conducting states. Consequently, a voltage across a gate (G) and an emitter (E) of the IGBT (1) is so reduced as to cut off the main current. The transistor (5) prevents the main current from excessive increase since the same has a high speed of response, while the thyristor (7) cuts off the main current to zero since the same has lower resistance in conduction.

Abstract: An output buffer circuit has a pull-up output transistor controlled by a first node and a pull-down output transistor controlled by a second node. The first node is coupled to the second node through a switching stage controlled by feedback from the output terminal. When the output buffer circuit is switched between the high and low output states, the switching stage is initially on, switches off shortly after the potential of the output terminal begins to change, then switches on again when the output terminal reaches a certain intermediate potential.

Abstract: The invention relates to a voltage limiter for a transistor circuit with semiconductors (T.sub.20 and T.sub.21) in the arrangement of a plurality of successive amplifier stages, with a reference element (Zener diode Z.sub.20) and with at least one voltage divider arrangement (voltage divider R.sub.21 /R.sub.22). In accordance with the invention, the reference element (Zener diode Z.sub.20) is disposed downstream of the triggering circuit of the first stage or even closer at the output of the voltage limiter circuit for reducing the oscillation tendency.

Abstract: Disclosed herein is a circuit for limiting the output current I.sub.O of a power MOSFET T.sub.1. A resistor R.sub.2 converts the current I.sub.O into a low voltage V.sub.0. The low voltage V.sub.O is detected by a low-voltage detecting circuit. When the low voltage V.sub.O is higher than a predetermined value V.sub.OL, the output current I.sub.O of the power MOSFET T.sub.1 is limited. The low-voltage detecting circuit comprises bipolar transistors Q.sub.1 to Q.sub.4. The base and collector of the transistor Q.sub.1 are connected to each other. The collector of the transistor Q.sub.2 is connected to the emitter of the transistor Q.sub.1. The base and emitter of the transistor Q.sub.3 are connected to the bases of the transistors Q.sub.1 and Q.sub.2, respectively. The base and collector of the transistor Q.sub.4 are connected to the emitters of the transistors Q.sub.1 and Q.sub.3, respectively. The low voltage V.sub.O is applied to the node between the emitters of the transistors Q.sub. 2 and Q.sub.4.

Abstract: An input buffer circuit is provided that has improved speed performance. The input buffer circuit has a voltage swing of V.sub.DD -V.sub.th to V.sub.SS. In so doing, the speed of the input buffer signal from input to output is significantly increased. In addition, the circuit also incorporates an additional current leaker transistor that limits the output high voltage from going above V.sub.DD -V.sub.th.