Abstract: The invention relates to a circuit arrangement for converting from a differential signal path (IFoutA-IFoutB) at the output of a mixer (18) to a signal path (Ssin gle) referenced to a reference potential (GND), wherein a controllable switch element (24a, 24b) is provided in each of the two single signal paths (IFoutA-IFoutB) of the differential signal path (IFoutA-IFoutB), wherein a first memory element (25) is connected in series with the two switch elements (24a, 24b), wherein there is provided for the two switch elements (24a, 24b), at least one control (23), which during a charging phase of the first memory element (25) connects the differential signal path (IFoutA-IFoutB) at the output of the mixer (18) with the first memory element (25) and applies the output signal on the differential output of the mixer (18) for charging the first memory element (25), and which during the discharging, respectively reverse charging, phase connects the first memory element (25) with the signal path referenced to the

Abstract: A radio frequency mixer circuit comprises a first terminal, a local oscillator terminal and a second terminal, a wave propagation medium having a first and second end, a circulator coupling together the first terminal, the first end of the wave propagation medium and the second terminal, a switching means operable according to a signal coupled to the LO terminal, the switching means being coupled to the second end of the wave propagation medium for causing a reflection with unchanged voltage wave polarity when the switching means is in an open state, or a reflection with inverted voltage wave polarity when the switching means is in a closed state, at the second end of the wave propagation medium when a wave is travelling therein.

Abstract: A frequency mixer circuit includes a mixer, a load stage, and again stage. The load stage cooperates with the mixer to generate a differential output voltage signal with a mixed frequency according to a differential local oscillator voltage signal and a differential input voltage signal. The gain stage has a transconductance, and a magnitude of the differential current signal and the transconductance have a positive relationship therebetween, so as to result in a positive relationship between the transconductance and a conversion gain which is a ratio of magnitude of the differential output voltage signal to magnitude of the differential input voltage signal.

Abstract: A receiving device includes a dividing circuit, N pieces of internal circuits, and an averaging circuit. The dividing circuit is configured to divide an input signal into N pieces of divided signals (where N is an integer of two or larger), and the N pieces of internal circuits are configured to receive and process the N pieces of divided signals. The averaging circuit is configured to receive N pieces of output signals from the N pieces of internal circuits, averaging the output signals, and output an averaged signal.

Abstract: An improved approach to direction finding using a super delta monopulse beamformer is disclosed. A super delta channel signal that includes direction finding information from two circular delta channels is formed and output by the super delta monopulse beamformer. This super delta channel signal uses only two channels, but is able to realize the accuracy of conventional three channel systems.

Abstract: The noise response in a passive mixer circuit is improved by discharging the switching transistors in the mixer circuit in an appropriate time slot prior to activation. In addition to improving the noise response, tilt in conversion gains and linearity can be reduced. A passive mixer circuit includes bypass switches arranged in proximity to the switching transistors that make up the mixer core. These bypass switches, which are activated in intervals just prior to the active intervals of their neighboring switching transistors, discharge to ground accumulated charges on the switching transistors or on reactive components around switches.

Abstract: According to an embodiment, a semiconductor circuit includes a substrate, a tunnel oxide film, a charge storage film, a blocking layer, and plural nodes. The substrate is made of a semiconductor in which two diffusion layers each serving as either a source or a drain are formed. The tunnel oxide film is formed on a region of the substrate between the diffusion layers. The charge storage film is formed on the tunnel oxide layer and stores charge. The blocking layer is formed between the charge storage film and a gate electrode and has layers of a first oxide film, a nitride film and a second oxide film to have a thickness of 5 nm or larger but 15 nm or smaller. The nodes allow external application of voltages so that the source and the drain are reversed and allow detection a gate voltage, a drain current and a substrate current.

Abstract: A frequency mixer circuit includes a gain stage and a mixer. The gain stage has a specific circuit design to convert a differential input voltage signal into a differential current signal with an input frequency. The mixer receives a differential local oscillator (LO) voltage signal with a LO frequency, and the differential current signal from the gain stage, and outputs a differential output voltage signal having a mixed frequency associated with the input frequency and the LO frequency.

Abstract: An electronic device is described, the device including a first circuit arranged to transfer a signal with a first predetermined phase shift, a second circuit, connected in series with the first circuit, arranged to transfer a signal with a second predetermined phase shift, and a resistance connected in parallel with the first and second circuits, wherein the first circuit includes a first capacitance connected between a first pair of nodes, a second capacitance connected between a second pair of nodes, and a first transformer having a first winding connected between the first pair of nodes and a second winding connected between the second pair of nodes.

Abstract: An apparatus for controlling a target device including a first input device configured to provide a first input to the target device, a second input device configured to provide a second input to the target device, and a control mixer configured to generate an output using a policy, the first input and the second input, wherein the output comprises a feedback and a target device output, wherein the feedback comprises some function of the state of the target device, the policy, and the state of each input device connected to the control mixer.

Abstract: Exemplary embodiments of the invention disclose receiver baseband filtering. In an exemplary embodiment, the filter device may comprise a continuous-time filter and a discrete-time filter operably coupled to the continuous time-filter. The discrete-time filter may include a passive infinite impulse response filter operably coupled between the continuous-time filter and an amplifier. The discrete-time filter may also include an active infinite impulse response filter operably coupled between an output of the amplifier and an input of the amplifier. The discrete-time filter may be configured to combine an output of the active infinite impulse response filter and an output of the passive infinite impulse response filter to form a composite signal. Furthermore, the amplifier may be configured to receive and amplify the composite signal.

Abstract: A frequency tunable signal source (100) with first (105) and a second (115, 315) oscillators, each of which outputs a signal at a fundamental frequency (f1, f2) and at least one signal at a harmonic frequency (f1?, f2?) and a mixer (120) with first (121) and second (122) input ports and an output port (124), and a control unit (110) which controls switches (S1, S2, S3, S4), by means of which two of said signals (f1, f2, f1?, f2?) are switchably connected to the first input port. The other two signals are switchably to the other input port, with one switch (S1, S2, S3, S4) for each signal (f1, f2, f1?, f2?). There is also comprised a third oscillator (125), with an output signal connected to a third input port (123) of the mixer (120). At least one of the oscillators (105, 115, 315, 125) is a VCO, a Voltage Controlled Oscillator.

Abstract: A switching circuit is linearized by using a capacitor to apply a drive voltage to an FET, wherein the drive voltage is independent of the signal switched by the switching circuit.

Abstract: A mixer includes a first node to which an intermediate frequency (IF) signal is input; first and second transistors that respectively have control terminals supplied with local signals having mutually opposite phases and output terminals connected to the first node; a first filter that is connected between the output terminal of the second transistor and the first node and suppresses passage of the IF signal; a second node to which the IF signal is input; third and fourth transistors that respectively have control terminals supplied with local signals having mutually opposite phases and output terminals connected to the second node; a second filter that is connected between the output terminal of the fourth transistor and the second node and suppresses passage of the IF signal; and a combiner combining a signal output from the first node and a signal output from the second node.

Abstract: A switching power amplifier for multi-path signal interleaving includes a signal splitter configured to split a multi-bit source signal from a digital source into a plurality of multi-bit signals, one or more fractional delay filters configured to delay one or more signals of the plurality of signals by a selected time, a plurality of bit-stream converters, each bit-stream converter configured to receive one of the multi-bit signals, each bit-stream converter further configured to generate a single-bit signal based on a received multi-bit signal, a plurality of switching power amplifiers, each switching power amplifier configured to receive a single-bit signal from one of the bit-stream converters, and an interleaver configured to generate an interleaved output by interleaving two or more outputs of the switching power amplifiers, wherein a sampling frequency of the interleaved output of the interleaver is greater than the selected sampling frequency of the multi-bit source signal.

Abstract: An adjustable power splitter includes: a power divider with an input and a first and second divider output; a first adjustable phase shifter and first adjustable attenuator series coupled to the first divider output and providing a first power output; a second adjustable phase shifter and second adjustable attenuator series coupled to the second divider output and providing a second power output; an interface; and a controller. The controller is configured to receive, via the interface, data indicating phase shifts to be applied by the first and second adjustable phase shifters and attenuation levels to be applied by the first and second adjustable attenuators, and to control, based on the data, the phase shifts and attenuation levels applied by the first and second adjustable phase shifters and the first and second adjustable attenuators.

Abstract: The present invention discloses a phase interpolating apparatus comprising: a first signal generation circuit, configured for generating a first signal having a first phase; an optional second signal generation circuit, configured for generating a second signal having the first phase; a third signal generation circuit, configured for generating a third signal having a second phase; a fourth/fifth signal generation circuit, configured for generating a fourth signal having a third phase when operating in a first mode and for generating a fifth signal having the second phase instead of the fourth signal when operating in a second mode; and a phase interpolator, configured for generating an interpolated signal without utilizing the fourth signal when operating in the first mode and for generating the interpolated signal according to the first signal, the third signal, and the fifth signal when operating in the second mode.

Abstract: A voltage generator includes a digital-to-analog (D/A) converting device configured to convert an input voltage to a pair of analog voltages, and a voltage mixer coupled to receive the analog voltages via electrical wirings to combine one or both of the analog voltages into an output voltage.

Abstract: In a mixer circuit that solves the problem of the extreme increase in circuit complexity that accompanies compensating for amplitude errors and phase errors, a voltage current conversion unit (11) converts an RF signal, which is a voltage signal, to a current signal and supplies the current signal. An RF path selection unit (12) connects its input terminal to any of its output terminals in accordance with the state of a four-phase clock signal and separately supplies, from its output terminals, a plurality of IF signals obtained by multiplying the RF signal by clock signals in the four-phase clock signal. An IF path selection unit (13) switches the connection relationship between its input terminals and its output terminals in accordance with a selection signal (S) and supplies the IF signal input to each of its input terminals from its output terminals that are connected to the input terminals.

Abstract: Mixers are described which allow for information sharing in redundant systems, while providing sufficient isolation between redundant system components to enable fault-tolerant operation.

Abstract: A transmitter includes a power amplifier driver to amplify a communication signal and a mixer connected with the power amplifier driver, the mixer to output the communication signal to the power amplifier driver. A capacitor and an inductor connect with the mixer and the power amplifier driver. The capacitor and the inductor create a resonant frequency to attenuate frequency components around a determined order of a local oscillator signal.

Abstract: This disclosure is directed to techniques for decoding two or more signals that vary sinusoidally with respect to a parameter value to produce a decoded signal that varies linearly with respect to the parameter value. The techniques may include receiving a first signal and a second signal, the first signal varying with respect to a parameter value according to a first sinusoidal function having a period and a first phase, the second signal varying with respect to the parameter value according to a second sinusoidal function having the period and a second phase different from the first phase. The techniques may further include performing one or more arithmetic operations using the first signal, the second signal, and an offset value to generate a third signal that varies linearly with respect to the parameter value for at least one-half of the period of the first signal and the second signal.

Abstract: A method and circuit for implementing low duty cycle distortion and low power differential to single ended level shifter, and a design structure on which the subject circuit resides are provided. The circuit includes an input differential amplifier providing positive and negative differential amplifier output signals coupled to an output amplifier providing a single ended output signal. The output amplifier amplifies and inverts the negative differential amplifier output signal. The output amplifier amplifies and superimposes the positive differential amplifier output signal with the amplified and inverted negative differential amplifier output signal, providing the single ended output signal with low duty cycle distortion.

Abstract: Embodiments provide a mixer cell, which is implemented to logically combine a data signal with an oscillator signal and a sign signal to obtain a mixer cell output signal based on the logical combination. Further embodiments provide a modulator with a plurality of mixer cells.

Abstract: A transistor-based switch is coupled to a replica circuit that includes transistor circuitry similar to that of the switch. The replica circuit biases a switched transistor to promote linear operation of the switch.

Abstract: A double balanced image reject mixer (IRM) can be configured to comprise: a common radio frequency (RF) port; four mixer devices, each comprising an intermediate frequency (IF) port, an RF port and an local oscillator (LO) port; and a four-way, in-phase splitter/combiner. The four-way, in-phase splitter/combiner can be connected between the RF common port and the RF port of each of the four mixer devices. A method of performing spurious suppression and image reject mixing in a double balanced IRM, can comprise: directly in-phase combining radio frequency (RF) output signals of four mixer devices located in the double balanced IRM; and phase pairing local oscillator (LO) signals and intermediate frequency (IF) signals such that the combination of the phases of the respective IF and LO signals can result in substantially equal phase RF signals at the RF ports of all four mixer devices.

Abstract: A sampling circuit is provided that includes a first sampling circuit that shifts a frequency, at which a gain of a frequency characteristic is maximized, to a lower frequency side, and a second sampling circuit that shifts the frequency, at which the gain of the frequency characteristic is maximized, to a higher frequency side. The sampling circuit also includes an output section provided in an output side of the first sampling circuit and an output side of the second sampling circuit, and outputs a sum or a difference between an output from the first sampling circuit and an output from the second sampling circuit.

Abstract: A sampling circuit and a receiver are provided having a high flexibility of filter design and excellent characteristics for removing an interfering wave. Provided also are a sampling circuit and a receiver having a low level of the higher harmonic spurious. The sampling circuit includes a charge sampling circuit, which executes sampling of an input signal, and a plurality of charge sharing circuits connected in parallel to the output stage of the charge sampling circuit. The charge sharing circuits include a charge sharing circuit group having transmission functions different from one another, a synthesis circuit, which is arranged at the output side of the charge sharing circuit group and synthesizes the outputs of the charge sharing circuits, and a digital control unit, which outputs a control signal for controlling the operation of the charge sharing circuit group and the synthesis circuit.

Abstract: In one embodiment, a phase interpolator with a phase range of n degrees, where 0<n?360, and having m reference signals, where m?2, and a control signal as input, and producing an output signal with a phase within the phase range using one or more of the m reference signals based on a control code provided by the control signal. The phase interpolator comprises one or more circuits configured to: divide the phase range of n degrees into k sections, wherein k>m; and for each of the k sections, select a relative gain of one or more weights assigned to the one or more reference signals, respectively, with respect to the control code provided by the control signal.

Abstract: An adjustable power splitter includes: a power divider with an input and a plurality, N, of divider outputs; a plurality, N, of adjustable phase shifters and a plurality, N, of adjustable attenuators series coupled to the divider outputs and providing a plurality, N, of power outputs; an interface; and a controller. The controller is configured to receive, via the interface, data indicating phase shifts to be applied by the adjustable phase shifters and attenuation levels to be applied by the adjustable attenuators, and to control, based on the data, the phase shifts and attenuation levels applied by the adjustable phase shifters and the adjustable attenuators.

Abstract: Signals generated by an array of photodiodes are applied to the inputs of corresponding edge detection circuits. Each edge detection circuit generates an output that changes state in response to a detected edge of the photodiode generated signal. The edge detection circuits may be formed by toggle flip-flop circuits. The outputs of the edge detection circuits are logically combined using exclusive OR logic to generate an output. The exclusive OR logic may be formed by a cascaded tree of exclusive OR circuits.

Abstract: A mixer for providing a mixed signal by mixing an input signal and an oscillation signal, comprising a follower and a switch. The follower is arranged to conduct a driving contribution from a bias terminal to an output terminal following a signal at an input terminal, wherein the input terminal and the bias terminal are respectively coupled to the input signal and the oscillation signal, and the output terminal is arranged to output the mixed signal. The switch is arranged to selectively conduct the output terminal to a reference level in response to alternating of the oscillation signal. An associated signal circuit is also disclosed.

Abstract: Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of constant envelope constituent signals. The constituent signals are amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal. Embodiments also perform frequency up-conversion.

Abstract: A mixer arrangement for generating an analog output signal by mixing an analog input signal with a discrete-time mixing signal. The mixer arrangement comprises a plurality of unit elements. Each unit element is adapted to be in an enabled mode in a first state of an enable signal supplied to the unit element, and in a disabled mode in a second state of the enable signal. Each unit element is adapted to generate the output signal of the unit element based on the analog input signal of the mixer arrangement in the enabled mode but not in the disabled mode. The unit elements are connected for generating a common output signal as the sum of the output signals from the unit elements. The mixer arrangement is adapted to generate the analog output signal of the mixer arrangement based on the common output signal. A corresponding method is also disclosed.

Abstract: A method of frequency down-converting an input signal to an output signal, a first local oscillator signal is generated as a square wave having a duty cycle of 1/3 or 2/3, and the input signal is mixed with first oscillator signal to achieve a first down-converted signal, a second local oscillator signal is generated as a modified square wave having the same period time as the first oscillator signal and a duty cycle of 2/3, of which one part has a positive amplitude and another part has a negative amplitude. The input signal is mixed with the second oscillator signal to achieve a second down-converted signal. The first oscillator signal has a delay of 1/4 of the period time to achieve a phase shift of ?/2 between the oscillator signals, and at least one down-converted signal is multiplied by a pre-calculated factor. The resulting down-converted signals are added to achieve the output signal.

Abstract: According to an embodiment, a mixer circuit includes first transistors each having a charge storage layer, a second transistor, a group of first nodes, and an output node. The first transistors as a pair receive a differential signal having a first frequency. The second transistor receives a signal having a second frequency. The group of first nodes makes the charge storage layer of at least any one of the first transistors store charge during non-operation period during which the differential signal having the first frequency and the signal having the second frequency are not mixed and reduces loss of the charge during operation period during which those signals are mixed, to adjust a threshold voltage of at least any one of the first transistors from outside. The output node outputs a signal resulting from mixing the differential signal having the first frequency and the signal having the second frequency.

Abstract: An up-conversion mixer includes a mixer cell having at least one output node configured to generate an output. The up-conversion mixer further includes a first cascaded transconductance input stage coupled to the mixer cell, the first cascaded transconductance input stage configured to receive an input signal and to reduce a third order harmonic of the output. The up-conversion mixer further includes a second cascaded transconductance input stage coupled to the mixer cell, the second cascaded transconductance input stage configured to receive the input signal and to reduce a third order harmonic of the output.

Abstract: Embodiments of the present invention disclose a frequency mixing circuit and a method for suppressing local oscillation leakage in the frequency mixing circuit, where a mixed input signal and a local oscillation signal are involved, and local oscillation leakage can be effectively reduced by using a frequency mixing circuit whose structure is simpler and is easier to be implemented. The frequency mixing circuit includes a direct current bias circuit, where the direct current bias circuit includes a direct current bias voltage source used for reducing a local oscillation current. The frequency mixing circuit is mainly applied to frequency mixing, and especially to a case where an intermediate frequency signal is mixed with a local oscillation signal to output a radio frequency signal.

Abstract: A mixer circuit (200, 300, 800, 900) for mixing a first input signal at a first frequency with a second input signal at a second frequency to an output signal at a third frequency. The mixer circuit (200, 300, 800, 900) comprises a mixing stage (205, 805) with differential input ports (206, 207; 820, 821) for the first input signal and an input port (211, 911) for the second input signal and differential output ports for the output signal, which also serve as output ports for the mixer circuit. The mixer circuit (200, 300, 800, 900) comprises a nonlinear digital to analogue converter (210, 810) which has an input port (211) which is the input port for the second input signal and an output port (212) which is connected to the input port of the mixing stage, and the digital to analogue converter has a nonlinear transfer function.

Abstract: A transmission device for two electric pulse measurement signals includes a first measurement signal input, a second measurement signal input, a differential measurement signal output and a signal converter. The first measurement signal input serves for receiving a first single-ended measurement signal, the second measurement signal input for receiving a second single-ended measurement signal, wherein the signal converter is implemented, when receiving a first one of the single-ended measurement signals, to convert either the first single-ended measurement signal or the second single-ended measurement signal into a combined differential measurement signal and provide the same at the differential measurement signal output. Here, the differential measurement signal includes a first differential portion which may be allocated to the first single-ended measurement signal and a second differential portion which may be allocated to the second single-ended measurement signal.

Abstract: A signal transmission circuit includes a first selection driver configured to generate a first drive signal in response to an input signal and a first selection signal and drive a transmission signal in response to the first drive signal, and a second selection driver configured to delay the input signal by a first delay time to generate a first delay signal. The second selection driver generates a second drive signal in response to the first delay signal and a second selection signal, generates a first code signal in response to the input signal and the second selection signal, and drives the transmission signal in response to the second drive signal and the first code signal.

Abstract: A circuit can compensate for intra pair skew or mode conversion in a channel by applying a second or corrective mode conversion effect that counters the channel's mode conversion. The circuit can process the common mode signal with a frequency dependent filter prior to injection back into the differential mode. The circuit can implement the reverse mode conversion with passive circuits using integrated resistors and metal oxide semiconductor (MOS) switches. In certain embodiments, such actions can proceed effectively without necessarily consuming active power.

Abstract: A frequency mixer having parallel mixer cores is described that is configured to heterodyne a signal. In an implementation, the frequency mixer includes a first mixer core and a second mixer core. A first balun is connected to the first mixer core and configured to furnish a LO signal occurring in a first range of frequencies to the first mixer core. The mixer includes a second balun coupled to the second mixer core, and the second balun is configured to furnish a LO signal occurring in a second range of frequencies during a second time interval. The mixer includes a first biasing voltage source that is center tapped to the first balun and a second biasing voltage source is center tapped to the second balun to further prevent operation of the at least substantially non-operational mixer core.

Abstract: In one aspect, the present invention exploits the termination conductances of a time-discrete harmonic mixer as another degree of freedom in configuring the mixer to meet given harmonic rejection performance requirements while using reduced number of unit cells. The values of these termination conductances are purposefully configured to introduce a desired non-linearity in quantization of the mixer transconductance by the unit cells. The non-uniform quantization produces a non-linear fitting of the transconductance levels to the transconductance points defining the target sinusoidal waveform. As a consequence of its termination conductance configuration, the contemplated mixer achieves levels of harmonic rejection with that would not be met if the reduced number of unit cells operated with uniform quantization. As a further advantage, the manipulated conductance values generally are lower than those used in conventional designs, e.g.

Abstract: The noise response in a passive mixer circuit is improved by discharging the switching transistors in the mixer circuit in an appropriate time slot prior to activation. In addition to improving the noise response, tilt in conversion gains and linearity can be reduced. A passive mixer circuit includes bypass switches arranged in proximity to the switching transistors that make up the mixer core. These bypass switches, which are activated in intervals just prior to the active intervals of their neighboring switching transistors, discharge to ground accumulated charges on the switching transistors or on reactive components around switches.

Abstract: Phase shift reduction in touch signals is disclosed. Touch signals with phase shifts can be demodulated with I- and Q-demodulation waveforms to generate the I and Q components of the signals. The I and Q components can then be combined so as to provide magnitude information not affected by the phase of the touch signals. The touch signals can be reconstructed with the combined I and Q components, thereby providing reconstructed touch signals with little or no phase shift.

Abstract: The CMOS programmable non-linear function synthesizer utilizes CMOS current-mode electronics to provide synthesis of arbitrary analog functions. The circuit approximates a seventh-order Taylor series expansion to synthesize an arbitrary nonlinear function. Each term of the Taylor series expansion is realized using a current-mode basic building block, and the output weighted currents of these basic building blocks are algebraically added in addition to a DC current, if needed. The CMOS current mode electronic circuit can be easily integrated, extended to include higher order terms of the Taylor series, and programmed to generate arbitrary nonlinear functions.

Abstract: A phase-combining circuit for combining cyclic timing waveforms that have been phase-controlled by control signals based on three or more input signals of different phases, has a weight signal generating circuit and a weighting circuit. The weight signal generating circuit generates weights according to the control signals, and the weighting circuit gives the weights to the respective input signals, with a positive or negative polarity for each one signal.

Abstract: A return-type current-reuse mixer having a transconductance/amplification stage, a mixing stage, and a high-pass and a low-pass filter network. The transconductance/amplification stage has a current-reuse CMOS topology wherein an input frequency signal is converted into a frequency current, low-frequency components are removed from the frequency current by the high-pass filter network, the frequency current is fed into the mixing stage, modulation occurs in the mixing stage, and then an intermediate-frequency signal is generated and output. Once high-frequency components are removed from the intermediate-frequency signal by the low-pass filter network, the intermediate-frequency signal is sent again for input into the transconductance/amplification stage, then amplified in the transconductance/amplification stage and output. The mixer transconductance/amplification stage employs a current-reuse technique.

Abstract: An adaptable mixer device is operable in a first mode and a second mode and includes a first set of mixer units operable in the first mode and a second set of mixer units operable in the second mode. The second set of mixer units includes at least one mixer unit that is common to both the first set of mixer units and the second set of mixer units. The second set of mixer units also includes a plurality of mixer units that are not in the first set of mixer units. Similarly, the first set of mixer units including a plurality of mixer units that are not in the second set of mixer units.