Abstract: An adaptive cancellation circuit and method are provided. The circuit includes a main path and an auxiliary path. The main path includes a first amplifier configured to output a first amplified signal to a first mixer. The main path is configured to output a first signal comprising a wanted signal component and a distortion component. The auxiliary path includes a second amplifier configured to output a second amplified signal to a second mixer. The second mixer is connected to a filter configured to remove the wanted signal component. The auxiliary path is configured to output a second signal including the distortion component.

Abstract: A clock signal supplying method for shift registers includes following steps: receiving a clock signal; and transmitting the clock signal to two first stage signal transmission paths simultaneously, the first stage signal transmission paths determined by a first control signal whether to be conducted, and further conducted at different time.

Abstract: A sampling circuit and a receiver, with relatively simple configurations, and clocks, exhibiting excellent frequency characteristics, are provided. In discrete time circuits, a charging switch is controlled on and off using one of four-phase control signals. A rotate capacitor shares electrical charge accumulated in an IQ generating circuit via the charging switch. A dump switch is controlled on and off using a different signal from the control signal used to control the charging switch on and off, among the four-phase control signals. A buffer capacitor shares electrical charge with the rotate capacitor via the dump switch to form an output value.

Abstract: A mixer includes a transformer and a mixing circuit. The transformer is employed for receiving an input signal to generate a differential output. The mixing circuit is coupled to the transformer, and employed for mixing the differential output with N oscillating signals having different phases to generate a plurality of mixed output signals, wherein N is greater than 2.

Abstract: An integrated circuit is described. The integrated circuit includes millimeter-wavelength transceiver circuitry. The millimeter-wavelength transceiver circuitry includes a local oscillator that generates a millimeter-wavelength oscillator signal. The millimeter-wavelength transceiver circuitry also includes mixers coupled to the local oscillator. The mixers are within an area without millimeter-wavelength structures. The mixers convert signals based on the millimeter-wavelength oscillator signal.

Abstract: Frequency conversion circuitry has an input node for receiving an input signal at a first frequency and an output node for producing an output signal at a second frequency different from the first frequency. A mixer circuit is responsive to the input signal for producing a signal at the second frequency. A step down impedance transformation circuit is coupled between the input node and an input of the mixer circuit for providing input impedance of the mixer circuit lower than impedance at the input node. An amplifier circuit is coupled between an output of the mixer circuit and the output node for amplifying the signal at the second frequency produced at the output of the mixer circuit. The mixer circuit is configured for providing input impedance of the output amplifier lower than the impedance at the input node.

Abstract: An in-phase, quadrature phase (IQ) mixer for a near field communications (NFC) device is disclosed that includes a signal provider that provides an in-phase (I) mixing signal and a quadrature phase (Q) mixing signal so that the period of the I mixing signal is equal to a period for the Q mixing signal. A controller is configured to control the signal provider so that the average of the I mixing signal over two periods is minimized and the average of the Q mixing signal over two periods is also minimized. The controller is also configured to control the signal provider so that the average propagation delay for the I mixing signal and the Q mixing signal is minimized individually and relative to each other.

Abstract: A signal converting device includes: a reference signal-mixing circuit arranged to generate a reference mixing output signal according to an input signal, a reference gain, and a reference local oscillating signal; a plurality of auxiliary signal-mixing circuits, each arranged to generate an auxiliary mixing output signal according to the input signal, an auxiliary gain, and an auxiliary local oscillating signal; and a combining circuit arranged to combine the reference mixing output signal and a plurality of the auxiliary mixing output signals to generate an output signal, and at least one of the auxiliary signal-mixing circuits is configured by the corresponding auxiliary gain to compensate phase imbalances between the reference mixing output signal and each of the auxiliary mixing output signals to reduce a power of a harmonic component in the output signal.

Abstract: The invention relates to devices comprising field effect transistors to detect the power of an electromagnetic high frequency signal VRF. According to the prior art, the high frequency signal is coupled into the gate G and via a capacitor CGD into the drain D of the field effect transistor FET, the gate G being biased with a direct voltage Vg which corresponds to the threshold value of the FET transistor. The resulting current at the source S contains a direct current portion Ids which is proportional to the square of the amplitude of the high frequency signal. The operating frequency of said power detectors is limited to a few gigahertz (GHz) by the discrete arrangement and especially by the predetermined gate length of the field effect transistor. The aim of the invention is to improve a resistive mixer in such a manner that it can be operated at high gigahertz and terahertz frequencies.

Abstract: A device, which provides a differential output signal having a first output signal component and a second output signal component based on a plurality of input signals, includes a pair of signal sources and a controller. The pair of signal sources includes a first activatable signal source for providing the first output signal component and a second activatable signal source for providing the second output signal component. The controller is operably coupled to the pair of signal sources and is configured to activate either the first signal source or the second signal source of the pair of signal sources depending on the plurality of input signals.

Abstract: A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals.

Abstract: A power combining and outphasing system and related techniques for simultaneously providing both wide-bandwidth linear amplification and high average efficiency is described. Providing linear amplification encompasses the ability to dynamically control an RF output power level over a wide range while still operating over a wide frequency bandwidth. The system and techniques described herein also operate to maintain high efficiency across a wide range of output power levels, such that a high average efficiency can be achieved for highly modulated output waveforms.

Abstract: In one embodiment of the invention, a method for convolution of signals is disclosed including generating four phased half duty cycle clocks each being out of phase by a multiple of ninety degrees from the others; coupling the four phased half duty cycle clocks into a four phase half duty cycle mixer; and switching switches in the four phase half duty cycle mixer in response to the four phased half duty cycle clocks to convolve a differential input signal with the four phased half duty cycle clocks to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port.

Abstract: An adjustable power splitter includes: a power divider with an input and a first and second divider output; a first adjustable phase shifter and first adjustable attenuator series coupled to the first divider output and providing a first power output; and a second adjustable phase shifter and second adjustable attenuator series coupled to the second divider output and providing a second power output.

Abstract: A power mixing circuit capable of maintaining a stable output voltage in a deep-power- down mode is provided. The power mixing circuit includes an input buffer, a power mixing control circuit, a power mixing driver and an output buffer. The input buffer is configured to operate using a first supply voltage, and to generate a first voltage signal in response to an input signal. The power mixing control circuit is configured to generate a power mixing control signal based on a power-up signal and a deep-power-down mode signal. The power mixing driver is configured to operate using an external supply voltage and a second supply voltage, to perform power mixing on the external supply voltage and the second supply voltage, and to generate a second voltage signal. The output buffer is configured to operate using the second supply voltage, and to generate an output signal.

Abstract: An RF transmitter capable of transmitting over a wide range of frequencies includes a mixer, a wideband high-Q balun, a first driver amplifier and a second driver amplifier. The balun has a single primary winding and two secondary windings. A differential output of the mixer is coupled to the primary winding. A first of the two secondary windings is coupled to drive the first driver amplifier. A second of the two secondary windings is coupled to drive the second driver amplifier. One driver amplifier is used when transmitting at lower frequencies whereas the other driver amplifier is used when transmitting at higher frequencies. By appropriate sizing of the inductances of the secondary windings and by switching out one of the secondary windings at certain times, the balun is tunable to operate over the wide frequency range while having a high quality factor Q, thereby facilitating reduced power consumption while simultaneously meeting performance requirements.

Abstract: Disclosed is a harmonic rejection mixer that makes it possible to suppress high-frequency response, while keeping the number of gm elements from increasing. In a harmonic rejection mixer that regulates the waveform of an output signal by mixing outputs of multiple mixers that are connected in parallel with the latter stage of multiple gm elements, some of the gm elements are shared by I phase and Q phase by using a control signal with a duty ratio of less than 50% to drive at least some of the mixers, and then using the period in which the I-phase mixers are inactive to activate the Q-phase mixers.

Abstract: A high linearity up-conversion mixer is disclosed, which includes a voltage-to-current conversion circuit and an up-conversion mixer core circuit, the voltage-to-current conversion circuit has a differential signal positive input end for receiving an I/Q-channel positive baseband voltage signal and a differential signal negative input end for receiving an I/Q-channel negative baseband voltage signal, wherein the received positive and negative baseband voltage signals are low pass filtered by the voltage-to-current conversion circuit and are respectively converted to a first and a second current signal; the first and the second current signals are inputted to the up-conversion mixer core circuit to mix with local oscillator signals so as to output high linearity frequency-mixed signals. By embedding low-pass filters into the voltage-to-current conversion circuit of the up-conversion mixer, the present invention can ensure the high linearity of the up-conversion mixer while reduce the chip area and the current.

Abstract: A system for detecting responses of a MEMS resonator device includes first and second signal sources, a signal divider and a frequency mixer. The first signal source provides a first signal and the second signal source provides a second signal that electrostatically drives the MEMS resonator device, causing mechanical vibration. The signal divider divides the first signal into a probe signal and a local oscillator (LO) signal, the probe signal being applied to the MEMS resonator device and reflected by a capacitance of the MEMS resonator device. A reflection coefficient is modulated onto the reflected probe signal at the mechanical resonance frequency by variations in the capacitance induced by the mechanical vibration of the MEMS resonator device. The frequency mixer mixes the reflected probe signal and the LO signal and outputs an intermediate frequency (IF) signal, which represents modulation of the reflection coefficient, providing an image of the mechanical vibration.

Abstract: A down-conversion module for a heterodyne receiver comprises a first mixer circuit, a second mixer circuit and an interconnection. The first mixer circuit includes first and second differential control terminals and is arranged to produce a first down-converted differential voltage signal at a first down-converted frequency as a function of a first RF differential input signal applied to the first differential control terminals and of a first RF differential reference frequency signal applied to the second differential control terminals.

Abstract: Embodiments of apparatuses, systems and methods relating to a mixer having high second- and third-order intercept points are disclosed. Other embodiments may be described and claimed.

Abstract: In various embodiments, a differential phase generating hybrid can comprise a first input port in communication with a first active splitter, a second input port in communication with a second active splitter, a first active combiner that can be configured to receive a first signal from the first active splitter and a second signal from the second active splitter. The differential phase generating hybrid can further comprise a second active combiner that can be configured to receive the first signal from the first active splitter and the second signal from the second active splitter. The differential phase generating hybrid can further comprise a first output port to provide a first composite signal from the first active combiner, and a second output port to provide a second composite signal from the second active combiner. The size of the differential phase generating hybrid can be independent of an operating frequency.

Abstract: A circuit for performing arithmetic operations includes a differential capacitive transimpedance amplifier (CTIA) and a cross-multiplexer. The cross multiplexer forwards the current to be integrated out of a plurality of current sources either to the positive input port of the differential CTIA for positive integration in direct mode or to the negative input port of the differential CTIA for negative integration in reverse mode.

Abstract: Doppler-inspired methods for signal generation and frequency up-conversion are provided that are compatible with CMOS technology. In accordance with an embodiment, a circuit is provided that includes two input signals that can propagate on artificial transmission lines in opposite directions, resembling the relative movement of source and observer in Doppler frequency shift; and an output signal combiner. By controlling the characteristics of the transmission lines and the input signal frequencies, the harmonic generation of active devices is utilized and combined to provide the desired high-frequency component at the output.

Abstract: A harmonic rejection mixer having a phase rotator fed by a local oscillator signal. The local oscillator signal has a reference frequency. The phase rotator produces a plurality of output signals, each one of the signals having a common frequency related to the reference frequency and having different relative phase shifts. A plurality of mixer sections, each one of the sections being fed an input signal and a corresponding one of the plurality of output signals mixes the local oscillator signal with the corresponding one of the plurality of output signals fed thereto. A combiner combines the mixer signal from the plurality of mixer sections into a composite output signal. A detector detects energy in a harmonic of the composite signal and for adjusting the output signal of the phase rotator to reduce the selected harmonic of the composite signal.

Abstract: An example frequency converting circuit generates a multiplied signal obtained by multiplying a local signal by an amplified signal generated by an amplifying portion. The frequency converting circuit includes a converter which converts the amplified signal into a current signal and a switching circuit which multiplies the current signal by the local signal and generates the multiplied signal. An impedance element supplies a first direct current from the amplifier and a second direct current from the switching circuit to the converter.

Abstract: This invention relates to an open wireless architecture (OWA) radio frequency (RF) transceiver architecture including RF front-end system. Specifically, the invention relates to an OWA RF front-end utilizing non-broadband RF hardware to support wide range frequency bands and broad transmission bandwidth for future wireless communications.

Abstract: A system can generate a configurable feedback. The system includes a number of circuitries that are coupled to a number of drivers and connected to each other in a chain via a single-wire connection. Control circuitry is connected to the plurality of circuitries and adapted to output configuration data to at least one circuitry of the plurality of circuitries to configure a feedback signal to be delivered by the plurality of circuitries to the control circuitry via the single-wire connection.

Abstract: Techniques for providing an efficient interface between a mixer block and a transconductance (Gm) block. In an exemplary embodiment, the output currents of at least two unit cells of the transconductance block are conductively coupled together, and coupled to the mixer block using a single conductive path. For a differential signal, the conductive path may include two conductive leads. Within the mixer block, the single conductive path may be fanned out to at least two unit cells of the mixer block. At least one Gm unit cell may be selectively enabled or disabled to control the gain setting of the mixer-transconductance block. The techniques may further be applied to transceiver architectures supporting in-phase and quadrature mixing, as well as multi-mode and/or multi-band operation.

Abstract: A sampling circuit and a receiver with which filter characteristics compatible with the reception of wideband signals can be realized with a high degree of freedom in the setting of the filter characteristics. More specifically, the sampling circuit is capable of removing adjacent interfering wave signals while keeping in-band deviation small. The sampling circuit is equipped with a discrete-time analog processing circuit group, wherein multiple discrete-time analog processing circuits are connected in parallel, a synthesizer that synthesizes the output signals from each of the circuit systems and outputs same, and a digital control unit that outputs control signals. Each of the discrete-time analog processing circuits is configured to include multiple rotate capacitor units, which each includes a main rotate capacitor and a sub-rotate capacitor, and only the main rotate capacitors share electric charge with a buffer capacitor included in the synthesizer.

Abstract: Heterodyne commutating apparatuses and methods for creating the heterodyne commutating apparatuses are disclosed. The heterodyne commutating mixer includes a plurality of switches for transferring a radio frequency input signal sequentially during a plurality of local oscillator period timeslots to a plurality of output capacitors. The heterodyne commutating mixer also includes a plurality of inductors added across differential in-phase output terminals and quadrature output terminals. Values of inductance and capacitance are set to achieve resonance at an output intermediate frequency.

Abstract: A method for generating a signal having a defined bandwidth and a desired crest factor is disclosed. The signal is composed of a number of individual sinusoidal signals, each having an amplitude and a frequency. The method includes determining an exponent to be used in a specific exponential function and corresponding to the desired crest factor, the exponent being determined based on an a priori known relationship between crest factor and exponent; calculating a phase value for each sinusoidal signal using the specific exponential function and the previously determined exponent; and superposing the sinusoidal signals to obtain the signal having the desired crest factor, whereby the phases of the individual signals are maintained.

Abstract: Disclosed is a programmable complex mixer. In accordance with the embodiments of the present invention, it is possible to control an output by programming paths and signs of internal signals in a complex mixer to reduce a processing bandwidth, power consumption, and a chip area in a transceiver, thereby improving performance of a transceiver.

Abstract: A radio frequency circuit includes a transformer, a local oscillator, a first mixer, a second mixer, a first variable gain amplifier, and a second variable gain amplifier. The first mixer includes a first inductor that is coupled between a positive in-phase input and a negative in-phase input. The second mixer includes a second inductor that is coupled between a positive quadrature input and a negative quadrature input. The first and second inductors provide inductive loads and improve conversion gains of the first and second mixers respectively.

Abstract: A phase interpolation circuit including a first multiplexer, a second multiplexer, an interpolator and a duty-cycle repeater is provided. The first multiplexer receives a plurality of even order signals. The second multiplexer receives a plurality of odd order signals. The interpolator receives a first reference signal composed of one of the even order signals through the first multiplexer, and receives a second reference signal composed of one of the odd order signals through the second multiplexer. The interpolator divides a phase difference between the first reference signal and the second reference signal into a plurality of sub-phases according to a digital control signal, and selects one of the sub-phases to generate a differential input signal. The duty-cycle repeater adjusts the duty cycle of the differential input signal and accordingly generates a differential output signal with 50% duty cycle.

Abstract: Power mixer arrays for providing watt-level power in mobile systems. In one embodiment, a fully-integrated octave-range CMOS power mixer that occupies only 2.6 mm2 using a 130 nm semiconductor process has been demonstrated. The power mixer provides an output power of +31.5 dBm into an external 50 ? load with a power added efficiency (PAE) of 44% at 1.8 GHz and a full power gain compression of only 0.4 dB.

Abstract: A harmonic rejection mixer includes a differential in-phase signal path and a differential quadrature signal path, a shared differential transconductor for generating a shared transconductor output signal from a mixer input signal, a first selective mixing circuit disposed in the differential quadrature signal path and coupled to the shared differential transconductor, and a second selective mixing circuit disposed in the differential in-phase signal path and coupled to the shared differential transconductor, the first selective mixing circuit is controlled by a first selective control signal and the second selective mixing circuit is controlled by a second selective control signal to selectively supply the shared transconductor output signal to the differential quadrature signal path and the differential in-phase signal path, respectively.

Abstract: An integrated circuit device has a modulator module that provides a modulation signal comprising one frequency keyed on and off, or alternating between two or more different frequencies or phases that are selected based upon a modulator signal. The one or more frequencies or phases may be selected from a plurality of frequency sources. Switching the one frequency on or off, or between the at least two different frequencies or phases may be synchronized with one or both of the two or more different frequencies or phases so that “glitches” or spurs are not introduced into the modulation signal. The integrated circuit device may also comprise a processor, memory, digital logic and input-output. Frequency sources may be internal to the digital device or external. The modulator signal may comprise serial data generated from the digital logic and/or processor of the digital device.

Abstract: A semiconductor integrated circuit includes a mixer circuit unit having a first single gate mixer configured to receive a first input signal having a first frequency and a second input signal having a second frequency as inputs, a second single gate mixer configured to receive the first input signal and a third input signal of a phase inverted from a phase of the second input signal as inputs, a third single gate mixer configured to receive a fourth input signal of a phase inverted from the phase of the first input signal and the second input signal as inputs, and a fourth single gate mixer configured to receive the third and the fourth input signals as inputs; and a ½-frequency divider unit configured to receive output signals from the first to the fourth single gate mixers as inputs and output a desired signal.

Abstract: A new method of combing signals of equal magnitude using the space-time (ST) 2×1 code at the receiver in a linear amplification with nonlinear components (LINC) is provided to obviate the combiner power loss and isolation requirements inherent in using traditional methods.

Abstract: A combination mixer arrangement comprising a first mixer and a second mixer coupled in parallel between first and second input ports and an output port. The mixers are arranged to be driven simultaneously by an input signal provided at the second input port. They are de-coupled, so a bias voltage applied at the first input port provides dc bias simultaneously for the mixers to enable gain expansion of the first mixer responsive to an increase in said input signal and thereby an improved linearity for the combination mixer arrangement.

Abstract: A field programmable gate array is disclosed, which comprises at least one logic element having at least one switching element. The switching element comprises a static support element and a movable connecting element for providing a non-volatile electrical connection.

Abstract: A post-mixer amplifier device which receives and processes signals for use in a software-defined radio integrated circuit is provided. The post-mixer amplifier device includes but is not limited to a voltage amplifier having first and second inputs and a first output, a positive signal output connected with the first output of the voltage amplifier, and a positive signal input connected with a first bipolar junction transistor along a first pathway. The first bipolar junction transistor includes but is not limited to a first collector connected with a the first input of the voltage amplifier and a first emitter connected with an second output of the push-pull unity gain follower and forming a first current feedback pathway. The first bipolar junction transistor is driven with a passive resistive load.

Abstract: In one form, a power converter for a power detector or the like includes first and third transistors of a first conductivity type, and second and fourth transistors of a second conductivity type. A control electrode of the first transistor receives a first bias voltage plus a positive component of a differential input signal. The second transistor is coupled in series with the first transistor and has a control electrode receiving a second bias voltage plus a negative component of the differential input signal. The third transistor is biased using the first bias voltage plus the negative component. The fourth transistor is coupled in series with the third transistor and is biased using the second bias voltage plus the positive component. A common interconnection point of the first and third transistors forms an output node.

Abstract: An amplifier, mixer, and method for input impedance matching and linearization. The transconductor includes a first differential transistor and a second differential transistor, including a first differential source and a second differential source electrically connected at a source node. The transconductor includes a pair of transmission lines including a first line of the pair of transmission lines electrically connected to the first of the two differential voltage inputs and a second line of the pair of transmission lines electrically connected to the second of the two differential voltage inputs. The pair of transmission lines is electrically connecting the two differential voltage inputs at a common node. The transconductor also includes a linearization unit including one or more linearization transistors. The one or more linearization transistors include a linearization gate electrically connected to the common node. The linearization unit is configured to supply a virtual ground at the source node.

Abstract: In one embodiment, a circuit-based apparatus that operates on an input data stream includes delay-line circuitry that characterizes the input data stream, modified over time. A plurality of integrators provide a plurality of integrated signals in response to the delay-line circuitry, and a plurality of weighting amplifiers amplify the plurality of integrated signals by a plurality of respective time-varying weighting factors to provide weighted signals. A signal-combining circuit combines the weighted signals. The circuit-based apparatus also includes a plurality of parallel signal-processing circuit paths that couple the weighted signals to the signal-combining circuit. By combining the weighted signals from the parallel signal-processing circuit paths, the signal-combining circuit provides a signal representative of the input data stream.

Abstract: A downconverter capable of being normally operated even in the case where a universal dual downconverter is made up by use of multiple downconverter circuits. The downconverter includes first and second downconverter circuits, and an amplification unit having at least a first amplifier LNA for receiving a horizontally polarized wave signal, and a second amplifier LNA for receiving a vertically polarized wave signal. If a Tone/Pola signal is a signal indicating a power-saving mode, a control circuit of the first downconverter circuit causes both a local oscillator and a frequency converter to be in a non-operating state, controlling a bias circuit such that power is supplied to the first amplifier LNA.

Abstract: One embodiment of the present disclosure relates to a circuit. The circuit includes a digital to analog converter (DAC) configured to convert a time-varying, multi-bit digital value to a corresponding time-varying output current. The circuit also includes a mixer module downstream of the DAC and comprising a plurality of mixers. A control block is configured to selectively steer output current from the DAC to different mixers of the mixer module. Other techniques are also described.

Abstract: A coplanar waveguide (CPW) based subharmonic mixer working at 670 GHz using GaAs Schottky diodes. One example of the mixer has a LO input, an RF input and an IF output. Another possible mixer has a LO input, and IF input and an RF output. Each input or output is connected to a coplanar waveguide with a matching network. A pair of antiparallel diodes provides a signal at twice the LO frequency, which is then mixed with a second signal to provide signals having sum and difference frequencies. The output signal of interest is received after passing through a bandpass filter tuned to the frequency range of interest.