With Compensation Patents (Class 327/362)
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Publication number: 20130176068Abstract: A sensor output correction circuit includes an analog-to-digital converter configured to receive an input voltage corresponding to a sensor output of a sensor and a reference voltage that are selectively input to the analog-to-digital converter; and an arithmetic unit configured to correct output data, which is output from the analog-to-digital converter when the input voltage is input to the analog-to-digital converter, based on an output value that is output from the analog-to-digital converter when the reference voltage is input to the analog-to-digital converter. The arithmetic unit includes a multiply adder and a non-restoring divider.Type: ApplicationFiled: December 19, 2012Publication date: July 11, 2013Applicant: MITSUMI ELECTRIC CO., LTD.Inventors: Konosuke YAMAMOTO, Yoichi KIMURA
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Publication number: 20130154714Abstract: A system for current mode sample and hold, comprising a first PMOS transistor configured to generate a current to be sampled. A diode-connected NMOS transistor coupled to the first PMOS transistor and configured to receive the current. A switch coupled to the diode-connected NMOS transistor and configured to sample a gate-source voltage of the diode-connected NMOS transistor. A capacitor coupled to the switch and configured to stored the gate-source voltage of the diode-connected NMOS transistor. A second NMOS transistor coupled to the capacitor and configured to generate a current equal to the sampled current value.Type: ApplicationFiled: December 19, 2012Publication date: June 20, 2013Applicant: CONEXANT SYSTEMS, INC.Inventor: Conexant Systems, Inc.
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Publication number: 20130147538Abstract: Disclosed is a digital pre-distortion device which includes a pre-compensation lookup table which outputs a first input value and a second input value adjacent to an input signal, a first distortion value corresponding to the first input value, and a second distortion value corresponding to the second input value; and a function generator which generates a pre-distortion function based on the first and second input values and the first and second distortion values and generates a pre-distortion value corresponding to the input signal from the pre-distortion function.Type: ApplicationFiled: July 27, 2012Publication date: June 13, 2013Applicant: Electronics and Telecommunications Research InstituteInventors: Jung Hoon OH, Joon Hyung KIM, JAE HO JUNG, HYUN KYU CHUNG
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Patent number: 8456226Abstract: Certain aspects of a method and system for a process sensor to compensate SoC parameters in the presence of IC process manufacturing variations are disclosed. Aspects of one method may include determining an amount of process variation associated with at least one transistor within a single integrated circuit. The determined amount of process variation may be compensated by utilizing a process dependent current, a bandgap current, and a current associated with a present temperature of the transistor. The process dependent current, the bandgap current and the current associated with the present temperature of the transistor may be combined to generate an output current. A voltage generated across a variable resistor may be determined based on the generated output current.Type: GrantFiled: July 10, 2012Date of Patent: June 4, 2013Assignee: Broadcom CorporationInventors: Stephen Chi-Wang Au, Arya Behzad, Paul Chang
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Patent number: 8405452Abstract: A filtering arrangement comprises a reference voltage input (1) and a compensation current arrangement (10) coupled to the reference voltage input (1) and configured to provide a control current at a current output (2) as a function of a voltage at the reference voltage input (1). The filtering arrangement also comprises a first and a second current source (20, 30) each having a control input (4, 5) coupled to the current output (2), a first and a second filter input (7, 8), and a first transistor (T1) and a second transistor (T2). The first transistor (T1) has a first connection (T11), a second connection (T12) and a control connection (T1c), where its first connection (T11) is coupled to the first current source (20) and its second connection (T12) is coupled to the first filter input (7) through a first resistor (R1).Type: GrantFiled: November 14, 2008Date of Patent: March 26, 2013Assignee: austriamicrosystems AGInventor: Pramod Singnurkar
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Patent number: 8319525Abstract: A flip-flop circuit includes a D flip-flop and a leakage current suppression circuit. The D flip-flop receives an input signal and a clock signal, and outputs a voltage of the input signal at a rising or falling edge of the clock signal as an output signal. The leakage current suppression circuit detects an output error caused by the leakage current flowing through at least a floating node of the D flip-flop and compensates for the leakage current to correct the output error. The leakage current suppression circuit includes a detection circuit and a compensation circuit. The detection circuit receives the output signal and clock signal and detects whether the output error has occurred to generate a detection result. The compensation circuit compensates for the leakage current according to the detection result to correct the output error.Type: GrantFiled: November 3, 2010Date of Patent: November 27, 2012Assignee: National Taiwan UniversityInventors: Yun-Ta Tsai, Shen-Iuan Liu
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Publication number: 20120268192Abstract: A high-linearity testing stimulus signal generator comprises a signal collection unit receiving an input current signal, a waveform conversion unit connecting with the signal collection unit, a first voltage-to-current conversion unit connecting with the waveform conversion unit, a delay unit connecting with the waveform conversion unit, a second voltage-to-current conversion unit connecting with the delay unit, a current comparison unit connecting respectively with the first voltage-to-current conversion unit and the second voltage-to-current conversion unit, an error calculation unit connecting with the current comparison unit, and a compensation unit connecting with the error calculation unit. The above-mentioned structure forms a feedback mechanism to perform compensation adjustment to promote the linearity of the output signals. Thus, the present invention can generate high-accuracy testing stimulus signals.Type: ApplicationFiled: April 22, 2011Publication date: October 25, 2012Inventors: Chun-Wei LIN, Yi-Cang Wu
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Patent number: 8295958Abstract: A circuit for correcting the output of an audio level meter comprises input means for generating the square or the absolute value of an input signal, a low pass filter having a predetermined attack time and release time, and output means for converting the output signal from a linear scale to a logarithmic scale. The circuit further comprises a correction means to which an information about whether the input signal to the audio level meter was subject to squaring or converting into an absolute value at the input, as well as the attack and release time of the low pass filter, are supplied as input values, and which provides, at its output, a value representing the difference between the output of the audio level meter and the true signal power of the input signal.Type: GrantFiled: August 7, 2007Date of Patent: October 23, 2012Assignee: Thomson LicensingInventors: Markus Schlosser, Ulrich Schreiber, Mario Sieck
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Publication number: 20120218022Abstract: In one embodiment, a current sensing circuit corrects for the transient and steady state temperature measurement errors due to physical separation between a resistive sense element and a temperature sensor. The sense element has a temperature coefficient of resistance. The voltage across the sense element and a temperature signal from the temperature sensor are received by processing circuitry. The processing circuitry determines a power dissipated by the sense element, which may be instantaneous or average power, and determines an increased temperature of the sense element. The resistance of the sense element is changed by the increased temperature, and this derived resistance Rs is used to calculate the current through the sense element using the equation I=V/R or other related equation. The process is iterative to continuously improve accuracy and update the current.Type: ApplicationFiled: February 25, 2011Publication date: August 30, 2012Applicant: LINEAR TECHNOLOGY CORPORATIONInventors: Kalin V. Lazarov, Matthew J. Maloney, Christopher Pollard, Edson W. Porter
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Patent number: 8237492Abstract: Certain aspects of a method and system for a process sensor to compensate SoC parameters in the presence of IC process manufacturing variations are disclosed. Aspects of one method may include determining an amount of process variation associated with at least one transistor within a single integrated circuit. The determined amount of process variation may be compensated by utilizing a process dependent current, a bandgap current, and a current associated with a present temperature of the transistor. The process dependent current, the bandgap current and the current associated with the present temperature of the transistor may be combined to generate an output current. A voltage generated across a variable resistor may be determined based on the generated output current.Type: GrantFiled: December 31, 2006Date of Patent: August 7, 2012Assignee: Broadcom CorporationInventors: Stephen Chi-Wang Au, Arya Behzad, Paul Chang
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Patent number: 8183906Abstract: The invention relates to an arrangement comprising a logarithmizing unit and a subtracting unit, wherein the subtracting unit has an output at which a voltage value linearly proportional to the temperature can be tapped off.Type: GrantFiled: March 13, 2009Date of Patent: May 22, 2012Assignee: Infineon Technologies AGInventors: Roland Thewes, Ralf Brederlow
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Patent number: 8163527Abstract: Subsystems and methods for use in patch clamp systems are provided. For example, in certain embodiments, compensation circuitry is used to compensate for non-idealities present in the patch clamp system. The accuracy of this compensation may be verified by employing, for example, circuitry that models the patch clamp system.Type: GrantFiled: May 2, 2008Date of Patent: April 24, 2012Assignee: Tecella LLCInventor: Yokichi J. Tanaka
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Patent number: 8098087Abstract: A method and apparatus is provided for standby voltage offset cancellation at inputs to a comparator within a receiver channel. Each of a first comparator input and second comparator input is isolated from an input signal such that each of the first and second comparator inputs attains a respective standby voltage level. A voltage level on one of the first and second comparator inputs is incrementally changed, while the output signal of the comparator is monitored. Upon detecting a state transition in the output signal of the comparator, the incremental changing of the voltage level on the one comparator input is stopped at a final voltage level setting. The final voltage level setting is stored in a computer memory for reference in setting of the voltage level at the one comparator input so as to compensate for the standby voltage offset at the inputs to the comparator.Type: GrantFiled: March 5, 2007Date of Patent: January 17, 2012Assignee: Altera CorporationInventors: John Dung-Ngoc Lam, Arch Zaliznyak, Wilson Wong, Tin H. Lai, Chong H. Lee, Sergey Shumarayev
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Publication number: 20120007652Abstract: A signal monitoring system includes a conversion circuit and a controller coupled to the conversion circuit. The conversion circuit converts a reference input to a reference output based on a real-time level of a trim reference and converts a monitored signal to an output signal. The controller calibrates the output signal according to the reference output and according to a predefined reference. The predefined reference is determined by the reference input and by a pre-trimmed level of the trim reference.Type: ApplicationFiled: December 22, 2010Publication date: January 12, 2012Inventor: Guoxing LI
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Patent number: 8068537Abstract: A communication circuit for providing a bi-directional data transmission over a signal line, thereby receiving a first digital data stream and transmitting a corresponding first signal into a near end of a signal line to a remote device, the remote device being connected to a far end of the signal line, receiving a second signal at the near end of the signal line from the remote device and deriving a second digital data stream therefrom, having a replica generator for providing, in response to the first digital data stream or a signal derived therefrom, a replica signal, and an extraction circuit for extracting the second digital data stream from the second signal in response to the replica signal and a comparator signal deduced from the near end of the signal line and an automatic test equipment having a plurality of communication circuits each providing a bi-directional data transmission.Type: GrantFiled: March 2, 2006Date of Patent: November 29, 2011Assignee: Verigy (Singapore) Pte. Ltd.Inventor: Bernhard Roth
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Publication number: 20110267131Abstract: An apparatus and a method for compensating periodic signal in an optical disc drive are described. The control apparatus includes an amplitude processing unit, a phase processing unit, a wave generator, a first switch module and a second switch module. The amplitude processing unit processes the amplitude of the input signal based on a reference signal for generating an amplitude signal. The phase processing unit processes the phase of the input signal based on the reference signal for generating a phase signal. The first switch module switches the amplitude signal to select one of the amplitude value and a predetermined amplitude value. The second switch module switches the phase signal to select one of the phase value and a predetermined phase value. The wave generator generates a compensated wave signal based on the selected amplitude value and the selected phase value, and outputs the compensated wave signal.Type: ApplicationFiled: July 12, 2011Publication date: November 3, 2011Applicant: MEDIATEK, Inc.Inventor: Kuo-jung Lan
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Publication number: 20110260898Abstract: In a compensator for compensating mismatches, and in methods for such compensation, the compensator compensates for mismatches in output signals of a system with mismatches during normal operation of the system with mismatches. The compensator comprises: a mismatch estimator that monitors at least two mismatched signals output by the system with mismatches during normal operation and that generates matching parameters indicating an amount of mismatch between the at least two mismatched signals, the mismatch estimator updating the matching parameters during normal operation of the system with mismatches, and a mismatch equalizer that compensates mismatches in the mismatched signals output by the system with mismatches during normal operation of the system with mismatches in response to the matching parameters.Type: ApplicationFiled: October 20, 2010Publication date: October 27, 2011Inventor: Scott R. Velazquez
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Patent number: 8044701Abstract: The disclosed device can contain a pair of switchable capacitors, one of which has the larger capacitance of the pair. Each of the switchable capacitors can include a capacitor in series with a switch. Both switchable capacitors can be connected in a parallel circuit that has a tunable capacitance. The ratio of the capacitances of the pair can approximately equal a ratio of mutually prime integers. In a particular case, the ratio of capacitances can approximately equal a ratio of two consecutive integers. The capacitance ratio can be called a weight or weight ratio. A switch controller can drive the pair of switchable capacitors with a pair of (M+1)-ary pulse width modulated signals, each of which has the same modulation period.Type: GrantFiled: October 15, 2010Date of Patent: October 25, 2011Assignee: Marvell International, Ltd.Inventor: Jody Greenberg
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Patent number: 7965133Abstract: A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.Type: GrantFiled: October 31, 2007Date of Patent: June 21, 2011Assignee: Agere Systems Inc.Inventors: Joseph Anidjar, Mohammad S. Mobin, Gregory W. Sheets, Vladimir Sindalovsky, Lane A. Smith
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Patent number: 7956667Abstract: Provided is a power voltage forming device which can correct an offset voltage of a high-frequency power amplifier without degrading distortion characteristic of a high-frequency power amplifier. The power voltage forming device (100) includes: a level adjusting unit (103) which adjusts the level of input data subjected to analog conversion, according to an output level control value for controlling the output level of the high-frequency power amplifier (200); an analog adder (104) which performs analog addition of the offset data subjected to the analog conversion, to the signal after the level adjustment; a digital adder (101) which performs digital addition of the offset data to the input data before the analog conversion; and a selection unit (106) which selects whether to perform addition by the analog adder (104) or addition by the digital adder (101) according to the output level control value.Type: GrantFiled: January 29, 2008Date of Patent: June 7, 2011Assignee: Panasonic CorporationInventors: Taichi Ikedo, Akihiko Matsuoka
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Patent number: 7925170Abstract: A predistortion circuit provides a predistorted input signal that compensates for distortion generated by a non-linear amplifier such as a laser device. The predistortion circuit may be used in an optical transmitter designed for broadband applications, such as a laser transmitter used for forward path CATV applications. The predistortion circuit may include a primary signal path and a secondary signal path that receive an input signal. A second order distortion generator on the secondary signal path generates predistortion of a magnitude corresponding to the magnitude of, but at an opposite phase to, the distortion generated by the non-linear amplifier. The second order distortion generator includes diodes with an adjustable diode bias to control phase, magnitude and/or magnitude/phase versus frequency of the predistortion.Type: GrantFiled: August 7, 2007Date of Patent: April 12, 2011Assignee: Applied Optoelectronics, Inc.Inventor: Brian Ishaug
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Patent number: 7915927Abstract: An offset cancellation circuit includes a sense amplifier configured to receive an input signal and offset voltages and to generate an output signal. A compensation voltage generation section is configured to be inputted with the output signal, and the compensation voltage generation section increases or decreases compensation voltages until the voltage level of the output signal reaches a target voltage level. The voltage level of the compensation voltages is maintained and a control signal is enabled when the voltage level of the output signal reaches the target voltage level. A control loading section is configured to provide the compensation voltages as the offset voltages or maintains the current level of the offset voltages, according to the control signal.Type: GrantFiled: December 23, 2008Date of Patent: March 29, 2011Assignee: Hynix Semiconductor Inc.Inventor: Ki Hyuk Lee
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Patent number: 7894561Abstract: A method for providing dynamic DC offset correction is provided. The method includes receiving a plurality of uncorrected samples. A determination is made regarding whether a specified number of consecutive uncorrected samples that correspond to a nominal voltage level has been received. When the specified number of consecutive uncorrected samples that correspond to the nominal voltage level has been received, an offset is generated based on an actual voltage level for each of the consecutive uncorrected samples.Type: GrantFiled: June 21, 2007Date of Patent: February 22, 2011Assignee: National Semiconductor CorporationInventor: Benjamin C. Buchanan
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Patent number: 7834676Abstract: A device for accounting for changes in characteristics of a transistor is presented. The device includes a transistor and a comparator receiving a feedback signal from the transistor and a reference signal. The comparator provides an output to a bias voltage generator. The bias voltage generator includes an input connected to the output of the comparator and an output connected to the transistor. In some embodiments of the invention the transistor is a double gate transistor and the bias voltage generator is applied to a top gate of the double gate transistor in order to control characteristics of the transistor such as turn on voltage.Type: GrantFiled: January 21, 2009Date of Patent: November 16, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Geun Lee, Jean-Ho Song, Yeong-Keun Kwon, Min-Cheol Lee, Ki-Won Kim, Young-Wook Lee
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Patent number: 7825715Abstract: The disclosed device can contain a pair of switchable capacitors, one of which has the larger capacitance of the pair. Each of the switchable capacitors can include a capacitor in series with a switch. Both switchable capacitors can be connected in a parallel circuit that has a tunable capacitance. The ratio of the capacitances of the pair can approximately equal a ratio of mutually prime integers. In a particular case, the ratio of capacitances can approximately equal a ratio of two consecutive integers. The capacitance ratio can be called a weight or weight ratio. A switch controller can drive the pair of switchable capacitors with a pair of (M+1)-ary pulse width modulated signals, each of which has the same modulation period.Type: GrantFiled: October 3, 2008Date of Patent: November 2, 2010Assignee: Marvell International Ltd.Inventor: Jody Greenberg
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Patent number: 7825713Abstract: An absolute time delay generating device includes a PVT (process-voltage-temperature) detection device and a delay-timing generator. The PVT detection device includes at least a delay module and a signal phase/frequency control module. The delay module includes a control unit and a reference unit. The control unit differs from the reference unit in sensitivity of delay property to PVT. The delay module compares phase or frequency differences generated when origin signals pass through the control unit and reference unit respectively, and produce delay parameters of the delay module. The signal phase/frequency control module receives and compares the delay parameters to determine an ambient PVT condition for the absolute time delay generating device, so as to control and correct the delay-timing generator and thereby generate accurate absolute time delay. Under various PVT influences, the absolute time delay generating device is capable of generating accurate, absolute time signals.Type: GrantFiled: October 2, 2008Date of Patent: November 2, 2010Assignee: National Chiao Tung UniversityInventors: Chen-Yi Lee, Jui-Yuan Yu, Chien-Ying Yu, Juinn-Ting Chen
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Patent number: 7812619Abstract: A capacitance measuring apparatus which comprises: a voltage source for applying voltage fluctuation to a device under test; a current source for absorbing the current flowing through the resistance component of the device under test; and an ammeter for measuring the leakage current flowing through the device under test before and after voltage fluctuation and the charging current flowing through the device under test as a result of voltage fluctuation.Type: GrantFiled: August 9, 2007Date of Patent: October 12, 2010Assignee: Agilent Technologies, Inc.Inventors: Shinichi Tanida, Hiroshi Nada, Tomoe Ikawa
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Patent number: 7791395Abstract: A signal generator generates a test signal including a positive signal and a negative signal which have the same amplitude. The signal generator corrects a DC level of the test signal based on a DC offset correcting signal supplied thereto, and supplies the corrected test signal to a frequency converter. An amplitude detector detects the amplitudes of the positive and negative signals of the test signal processed by the frequency converter. A level compressor converts in level the amplitudes of the positive and negative signals which are detected by the amplitude detector, with a gain variable depending on an input level thereto. A comparator compares the amplitudes of the positive and negative signals which are converted in level by the level compressor, with each other. An offset adjuster supplies the DC offset correcting signal depending on a compared result from the comparator to the signal generator.Type: GrantFiled: February 15, 2007Date of Patent: September 7, 2010Assignee: NEC CorporationInventors: Kiyoshi Yanagisawa, Noriaki Matsuno
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Patent number: 7777546Abstract: A DC offset calibration apparatus includes a first adjustment unit, a first offset calibration circuit, a second adjustment unit, and a second offset calibration circuit. The first adjustment unit adjusts a first input signal to generate a first output signal according to a first offset calibration signal. The first offset calibration circuit is coupled to the first output signal and the first adjustment unit for determining the first offset calibration signal according to the first output signal and predetermined threshold value. The second adjustment unit adjusts a second input signal to generate a second output signal according to a second offset calibration signal. The second offset calibration circuit is coupled to the second output signal and the second adjustment unit for determining the second offset calibration signal according to the second output signal and the predetermined threshold value. The first and the second input signals are a differential signal pair.Type: GrantFiled: January 2, 2008Date of Patent: August 17, 2010Assignee: Realtek Semiconductor Corp.Inventor: Ren-Chieh Liu
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Publication number: 20100182068Abstract: A device for accounting for changes in characteristics of a transistor is presented. The device includes a transistor and a comparator receiving a feedback signal from the transistor and a reference signal. The comparator provides an output to a bias voltage generator. The bias voltage generator includes an input connected to the output of the comparator and an output connected to the transistor. In some embodiments of the invention the transistor is a double gate transistor and the bias voltage generator is applied to a top gate of the double gate transistor in order to control characteristics of the transistor such as turn on voltage.Type: ApplicationFiled: January 21, 2009Publication date: July 22, 2010Inventors: Woo-Geun LEE, Jean-Ho Song, Yeong-Keun Kwon, Min-Cheol Lee, Ki-Won Kim, Young-Wook Lee
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Patent number: 7683695Abstract: Systems and methods for reducing the magnitude of signal dependent capacitance are provided. Capacitance canceling circuitry is operative to generate cancellation capacitance in response to the magnitude of a signal, which may be the same signal that produces the undesired signal dependent capacitance, to at least partially cancel the signal dependent capacitance.Type: GrantFiled: August 18, 2006Date of Patent: March 23, 2010Assignee: Linear Technology CorporationInventors: Joseph L. Sousa, David M. Thomas
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Publication number: 20100045359Abstract: To include a first replica buffer that has substantially the same circuit configuration as a pull-up circuit which constitutes an output buffer and a second replica buffer that has substantially the same circuit configuration as a pull-down circuit which constitutes the output buffer. When a first calibration command ZQCS is issued, either a control signal ACT1 or ACT2 is activated, and a calibration operation is performed for either the first replica buffer or the second replica buffer. When a second calibration command ZQCL is issued, both of the control signals ACT1, ACT2 are activated and the calibration operation is performed for both the first replica buffer and the second replica buffer.Type: ApplicationFiled: November 3, 2009Publication date: February 25, 2010Applicant: ELPIDA MEMORY, INC.Inventors: Hideyuki Yoko, Hiroki Fujisawa
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Patent number: 7612600Abstract: A DC offset calibration apparatus is disclosed. The DC offset calibration apparatus includes an adjustment circuit and an offset calibration circuit. The adjustment circuit is utilized for receiving an input signal and an offset calibration signal, and for adjusting the input signal to generate an output signal according to the offset calibration signal. The offset calibration circuit is coupled to the output signal and to the adjustment circuit for determining the offset calibration signal according to at least the output signal and a predetermined threshold value.Type: GrantFiled: January 2, 2008Date of Patent: November 3, 2009Assignee: Realtek Semiconductor Corp.Inventors: Ren-Chieh Liu, Han-Chang Kang
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Patent number: 7609094Abstract: An input circuit comprising a level-determining unit and an output unit is provided. In a first period controlled by a first enable signal, the level-determining unit receives an input signal at an input terminal of the input circuit and determines a voltage level of the input signal. The output unit is coupled to the input terminal. In the first period, the output unit outputs the input signal with the determined voltage level at an output terminal of the input circuit to serve as an output signal. In a second period following the first period, the output unit latches the determined voltage level of the input signal according to a second enable signal and outputs the input signal with the determined voltage level at the output terminal to serve as the output signal.Type: GrantFiled: June 21, 2007Date of Patent: October 27, 2009Assignee: Mediatek Inc.Inventor: Pi Fen Chen
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Patent number: 7592820Abstract: A circuit and method is disclosed for measuring the resistance of a resistive sensor, such as a PTC or NTC temperature sensor used for monitoring the temperature of the windings of an electric motor. The measurement circuit is based on an electronic circuit in which conductors from a sensor located in the object to be monitored are connected to an amplifier circuit in a feedback configuration that reduces the DC level supplied to the voltage divider when the sensor resistance increases. The measured signal is amplified and, using a comparator to compare it with the output voltage of a sawtooth generator, a continuous PWM (Pulse Width Modulation) signal is generated and transmitted in digital format to a SELV electronic circuit, for example through an opto-isolator. The essentially logarithmic signal amplification makes it possible to reliably distinguish between a short circuit in the sensor circuit and low values of sensor resistance.Type: GrantFiled: December 8, 2006Date of Patent: September 22, 2009Assignee: ABB OyInventors: Kari-Matti Laakso, Andreas Berts
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Patent number: 7590392Abstract: In some embodiments, a chip with a transmitter having a transmitter driver is provided. Also provided is a general compensation circuit coupled to the transmitter to generally compensate the transmitter driver and a specific compensation circuit coupled to the transmitter driver to specifically compensate the transmitter driver. Other embodiments are disclosed and claimed herein.Type: GrantFiled: October 31, 2005Date of Patent: September 15, 2009Assignee: Intel CorporationInventors: Navindra Navaratnam, Aninda K. Roy
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Patent number: 7583166Abstract: The present invention provides an apparatus for enhancing Q factor of an inductor. The apparatus includes a negative resistance generator coupled to the inductor for providing a negative resistance, and a bias circuit coupled to the negative resistance generator for biasing the negative resistance generator.Type: GrantFiled: August 7, 2006Date of Patent: September 1, 2009Assignee: Realtek Semiconductor Corp.Inventors: Ying-Yao Lin, Ying-Hsi Lin
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Patent number: 7551003Abstract: A current mirror circuit includes a pair of first and second transistors having bases connected together and emitters connected to a power line, a resistor connected between the bases of the first and second transistors and the power line, a third transistor for providing base currents of the first and second transistors and a resistor current flowing through the resistor, and a current compensation circuit that adds a compensation current to an input current to the first transistor. The amount of the compensation current is approximately equal to that of the resistor current divided by a current gain of the third transistor. Thus, the compensation current compensates the difference between a collector current of the first transistor and the input current.Type: GrantFiled: June 24, 2008Date of Patent: June 23, 2009Assignee: Denso CorporationInventor: Satoshi Sobue
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Patent number: 7521981Abstract: A mixer circuit. The mixer circuit comprises a double-balanced mixer and a carrier-leakage calibration cell. The double-balanced mixer has first and second input pairs whereby the first input pair receives the first differential input signal. The carrier-leakage calibration cell receives the second differential input signal and a differential calibration current and generates first and second output voltages to the second input pair of the double-balanced mixer.Type: GrantFiled: June 11, 2007Date of Patent: April 21, 2009Assignee: Mediatek Singapore Pte LtdInventors: Choon Yong Ng, Ee Sze Khoo
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Patent number: 7474130Abstract: A voltage-to-current converter providing an output current with compensation for process-voltage-temperature (PVT) variations of a component in the voltage-to-current converter. The voltage-to-current converter includes a first voltage-to-current converter branch, a second voltage-to-current converter branch, and a compensation current path. The first voltage-to-current converter provides a first current to the output of the voltage-to-current converter based on a variable control voltage. The second voltage-to-current converter branch provides a second current based on a fixed voltage. The compensation current path provides a compensation current from the second voltage-to-current branch to the first voltage-to-current converter branch compensating variations in the first current caused by the PVT variations of the component in the first voltage-to-current converter branch.Type: GrantFiled: February 6, 2007Date of Patent: January 6, 2009Assignee: iWatt Inc.Inventors: Ping Lo, Xuecheng Jin
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Publication number: 20090002053Abstract: Methods and systems for offset compensation using calibration are provided. Embodiments enable offset compensation using non-uniform calibration. Embodiments enable calibration schemes configurable according to the probability distribution function (PDF) of the random offset. Embodiments enable calibration schemes configurable with multiple levels of calibration resolution according to the PDF of the random offset. Embodiments enable calibration schemes configurable with multiple calibration step values according to the PDF of the random offset. Embodiments can be implemented for various types of random offset, including, without limitation, Gaussian-, Bernoulli-, uniformly-, Chi-, exponentially-, Gamma-, and Pareto-distributed offset.Type: ApplicationFiled: June 28, 2007Publication date: January 1, 2009Applicant: Broadcom CorporationInventor: Chun-Ying Chen
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Patent number: 7466601Abstract: According to one embodiment a semiconductor device is provided. The device includes a first compensator to generate a first compensated signal and a first limiter to control operation of the first compensator. Furthermore, a second compensator to generate a second compensated signal and a second limiter to control operation of the second compensator is provided. An output device is adapted to receive the first compensated signal and the second compensated signal to drive an output.Type: GrantFiled: December 1, 2006Date of Patent: December 16, 2008Assignee: Qimonda AGInventor: David Müller
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Publication number: 20080297226Abstract: A compensation circuit for compensating an output impedance of at least a first MOS device over PVT variations to which the first MOS device may be subjected includes a first current source generating a first current having a value which is substantially constant and a second current source generating a second current having a value which is programmable as a function of at least one control signal presented to the second current source. A comparator is connected to respective outputs of the first and second current sources and is operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current. A processor connected in a feedback arrangement between the comparator and the second current source receives the output signal generated by the comparator and generates the control signal for controlling the second current as a function of the output signal.Type: ApplicationFiled: May 31, 2007Publication date: December 4, 2008Inventors: Dipankar Bhattacharya, Makeshwar Kothandaraman, John C. Kriz, Antonio M. Marques, Bernard L. Morris
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Publication number: 20080284490Abstract: A method of compensating a monolithic integrated operational amplifier against process and temperature variations, such that the operational amplifier is suitable for use in an active filter, the method comprising a providing an amplifier having a first stage and an output stage, wherein the output stage drives an RC load, and wherein a compensation capacitor at an output of the first stage is selected so as to scale with the capacitance C of the RC load, and a transconductance of the first stage is a function of the resistance R of the RC load.Type: ApplicationFiled: May 18, 2007Publication date: November 20, 2008Applicant: Analog Devices, Inc.Inventor: Bernard Tenbroek
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Patent number: 7405610Abstract: A temperature compensation circuit consists of a thermo sensitive resistance, a fixed resistance, a logic buffer, and a logic inverter, without incorporating any operational amplifier. A resistance value of the thermo sensitive resistance is changed by temperature change. The fixed resistance has a small temperature changes that is smaller than that of the thermo sensitive resistance. Both the fixed resistance and the thermo sensitive resistance are connected electrically to an output terminal of the temperature compensation circuit. The logic buffer sets the other terminal of the fixed resistance to a first voltage that is one of a voltage level of a power source and a ground level. The logic inverter sets the other terminal of the thermo sensitive resistance to a second voltage that is reversed to the first voltage.Type: GrantFiled: June 20, 2006Date of Patent: July 29, 2008Assignee: DENSO CORPORATIONInventor: Hiroshi Okada
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Publication number: 20080174356Abstract: A wave detector circuit includes: a first transistor having its base and collector connected together, the first transistor receiving an AC signal and a reference voltage at its base and collector; a second transistor having its base connected to the base of the first transistor through a resistance, the second transistor outputting a detected voltage at its collector; and a diode-connected temperature compensation transistor connected between ground potential and the base and the collector of the first transistor.Type: ApplicationFiled: May 15, 2007Publication date: July 24, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kazuya YAMAMOTO, Miyo MIYASHITA, Takayuki MATSUZUKA
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Publication number: 20080136492Abstract: The leakage compensation circuit includes: a replica circuit of a circuit to be compensated, the replica circuit provides a replica leakage current equal to a leakage current of the circuit to be compensated; an amplifier having a first input coupled to the replica circuit and a second input coupled to a node to be compensated; a first resistance coupled between an output of the amplifier and the replica circuit; a second resistance coupled between the output of the amplifier and the node to be compensated; and wherein the replica leakage current is subtracted from the node to be compensated.Type: ApplicationFiled: December 6, 2006Publication date: June 12, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Yaqi Hu
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Patent number: 7368974Abstract: A signal adder circuit includes: an adding unit that includes at least a pair of amplification elements in which a constant current flows between ground terminals and a ground, input signals having different phases are input to input terminals, and output terminals to which a power supply voltage is applied are connected to each other; a gain control unit that is provided between the ground and each of the ground terminals of the amplification elements so as to adjust the amplitudes of the input signals having different phases; and a phase control unit that is provided between the ground and each of the ground terminals of the amplification elements so as to adjust the phases of the input signals having different phases.Type: GrantFiled: June 30, 2006Date of Patent: May 6, 2008Assignee: Alps Electric Co., Ltd.Inventors: Takeo Suzuki, Shigeru Osada
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Patent number: 7352231Abstract: A translinear network (34) has first (Q1, Q2, Q3, Q4) and second (Q4, Q3, Q5, Q6) translinear loops. A Trafton-Hastings clamp circuit (36) is connected to generate a piecewise-polynomial-continuous current IY, the value of which becomes undefined when current IX=0 due to a removable singularity in the transfer equation at this point. A current mirror (38) comprising a plurality of transistors (M1, M2, M3) is coupled to the Trafton-Hastings clamp circuit (36), and operates to add additional currents in transistors Q3 and Q5 to IX, when the Trafton-Hastings clamp transistor (Q7) conducts, so as to perturb the removable singularity in the transfer equation into the left half-plane.Type: GrantFiled: July 7, 2003Date of Patent: April 1, 2008Assignee: Texas Instruments IncorporatedInventor: Roy Alan Hastings
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Patent number: 7342432Abstract: A mixer circuit having improved linearity and noise figure is disclosed.Type: GrantFiled: February 11, 2004Date of Patent: March 11, 2008Assignee: Integrant Technologies Inc.Inventors: Tae-Wook Kim, Bon-Kee Kim, Kwy-Ro Lee