Abstract: A state-holding circuit having improved stability at high temperatures includes a bi-stable circuit capable of assuming one of two reversible and stable states. The bi-stable circuit comprises a plurality of logic components (e.g., transistors) arranged into two sides. Because each of the logic components has a leakage current and/or resistance that varies significantly as a function of temperature, one or more stabilization components, such as transistors or other devices, may be connected to a side of the bi-stable circuit to balance the leakage currents and/or resistances of each side. In certain embodiments, the sole function of the stabilization components is to balance the leakage currents and/or resistances of each side.

Abstract: A high gain, highly linear mixer includes an input section, mixing section, at least one tuning component, and at least one stand by current source. The input section is operably coupled to receive an input voltage signal and perform a linear transconductance thereon to produce an input current signal. The mixing section is operably coupled to mix a local oscillation with the input current to produce a mixed current signal. The tuning component is operably coupled to the mixing section and to convert the mixed current signal into a mixed voltage signal that function as the output of the mixer. The standby current source is operably coupled to the mixing section and provides a standby current to the mixing section.

Abstract: A method and apparatus are provided for operating a transmission amplifier, particularly a mobile communications terminal, with the transmission amplifier being fed with a supply voltage and with any nonlinearity of the transmission amplifier being substantially compensated for via a predistortion unit for data values in an input data stream, wherein, at least at the start of transmission operation or after a considerable change in the operating parameters, the transmission amplifier is operated with a supply voltage which is of such a magnitude that the transmission amplifier operates in the linear region, and the supply voltage for the transmission amplifier is reduced to the extent to which a quality factor for the compensation for the nonlinearity of the transmission amplifier is increased by the predistortion unit.

Abstract: A compensated switched capacitor circuit comprises a switched capacitor circuit and a compensation circuit. The compensation circuit generates a reference current that varies under closed loop control to maintain a targeted slew rate for charging a reference capacitor that is determined by the input clock frequency. The switched capacitor circuit's output amplifier is configured such that its output current varies in proportion to the reference current. Thus, by configuring the reference capacitor to track the effective capacitance of the switched capacitor circuit, the settling time of the switched capacitor circuit may be made relatively insensitive to the value of and changes in the effective capacitance over a range of clock frequencies. The compensation circuit may include a clock reconditioning circuit to ensure that the switched capacitor circuit is clocked at a desired duty cycle.

Abstract: An offset correction analogic circuit capable of compensating the offset of a digital baseband is described. The circuit comprises analog means to receive an output differential signal issued from a differential signal path. The differential signal path may be a baseband filter as used in digital communication systems. The baseband filter inputs an input differential signal having an offset to be compensated. The output differential signal is fed into an analog integrator to generate a pulsed signal either on a first output line or on a second output line according to the polarity of the output differential signal. The pulsed signal is then integrated into a switched capacitor and a differential compensation offset signal is issued. The frequency of the pulsed signal is preferably proportional to the voltage value of the output differential signal. The compensation offset signal may be summed with the input differential signal into a summing circuit.

Abstract: A mixer circuit arrangement for frequency-translating a voltage input signal by an amount dependent on the frequency of a local oscillator signal to provide an output signal. The arrangement comprises an input stage 33 and a mixer stage 32, the input stage 33 being arranged to convert the voltage input signal into differential current signals and the mixer stage 32 being arranged to mix the differential current signals with the local oscillator signal to provide the output signal. Means 34,35 is provided for injecting a compensation current into the input stage 33 so as to balance the differential current signals provided to the mixer stage 32.

Abstract: A loop filter of a compensating phase-locked loop contains capacitors formed from transistors with thin gate oxide dielectric layers. Leakage current leaks through the capacitors. To avoid jitter in the output signal of the phase-locked loop that would otherwise be caused by the leakage current, a leakage compensation circuit is provided. The leakage compensation circuit of a first embodiment replicates the leakage current using a replication capacitor and a current mirror. The voltage across the replication capacitor is proportional to the control voltage of a voltage-controlled oscillator of the compensating phase-locked loop. A second embodiment generates the compensation current by controlling the voltage on the gate of a transistor. The gate voltage depends on charge added and subtracted by a charge pump in addition to the charge pumps in the loop filter. A third embodiment applies a leakage compensation circuit to a delay locked loop.

Abstract: The present invention discloses an impedance matching circuit with automatic adjustment and a method thereof. The impedance matching circuit comprises: a resistor, for receiving a reference voltage and generating a reference current; a detection unit, for detecting resistance variation and generating a plurality of comparison voltages according to said reference current; a comparison unit, for comparing said reference voltage with said comparison voltages, and generating a control signal; and a composite resistor unit, for receiving said control signal and generating a matched impedance. Therefore, a matched impedance value can be obtained within a designed range in despite of the manufacturing process and the operation environment.

Abstract: A DC offset cancellation circuit employs multiple feedback factors for canceling DC offset by increasing convergence time. The DC offset cancellation circuit features an active low-pass analogue filter including a variable resistor, an amplifier, a capacitor pair and a comparator, the amplifier being coupled to an output of the variable resistor. Negative feedback is provided from the output of the variable resistor to the input signal source, the capacitor pair is coupled to the amplifier, one input of the comparator is coupled to an output of the amplifier, and a second input of the comparator is coupled to a reference voltage source such that a comparison signal is output by the comparator to the variable resistor after comparing the negative feedback signal with a reference voltage.

Abstract: System for a current source with enhanced output impedance. A preferred embodiment comprises a cascode current source arranged in a current mirror configuration (such as current source 600) with a pair of level shifters arranged in a source-follower configuration (such as level shifters 505 and 510). The level shifters reduce the compliance voltage of the current source, permitting use in low voltage applications.

Abstract: Electronic switch (1) with two switching states (ON, OFF) possesses at least one field effect switching transistor (Q1), input port (In) connected with source terminal (S), on which input signal (Vin) is present, output port (Out) connected with drain terminal, on which switched signal (Vout) is present, control port (Con) connected to gate terminal (G), on which is present signal (Vc) for controlling electronic switch (1) and switch apparatus (Sw), which creates the two switching states (ON, OFF) by means of a changing of control signal (Vc). Controlling signal (Vc), during at least one of the two switching states (ON, OFF) is, at least partially, formed by correction signal (Sc), which in turn is produced from input signal (Vin), so that the frequency dependent drop in voltage between the drain-source channel and the gate electrode of the field effect switching transistor (Q1) is at least partially compensated.

Abstract: A system and method to overcome or nullify a charge injection and clock feed-through error voltage caused by the turning-off charge of a switched element(s) in switched networks. A circuit for nulling a charge injection and clock feed-through error voltage includes, for example, two switched elements and a capacitor. The circuit can be used to replace any switch element in a switched network. The circuit may also include, for example, three switched elements and two capacitors.

Abstract: A bias generator adjustment system adjusts a PLL or DLL bias generator dependent on negative bias temperature instability effects in an integrated circuit. The bias generator adjustment system uses an aging independent reference circuit and a bias circuit to operatively adjust a bias generator such that transistor ‘aging’ effects that occur over the lifetime of an integrated circuit are compensated for or corrected.

Abstract: A base current compensation circuit is configured for injecting base current to the base of a transistor device to compensate for the lost current demanded by a transistor base. The base current compensation circuit is configured to inject current into the base of the transistor without the headroom requirements, as well as being less complex than other approaches. An exemplary base current compensation circuit comprises a sampling circuit and a current mirror feedback circuit configured for providing multiples of the base current demanded by the transistor device.

Abstract: A delay circuit is provided including first and second resistive elements electrically coupled in series having first and second resistance values. The first resistance value varies in proportion to temperature and the second resistance value varies in inverse proportion to temperature.

Abstract: In order to achieve an optimally stable synchronization of clock signals, a temperature-controlled delay device with which it is possible to generate a signal delay that is dependent on operating temperature is provided in a synchronization device for a semiconductor memory device. In this manner, the clock signal can be time-tuned in a particular reliable fashion.

Abstract: To provide a leak current compensating device which ensures that the voltage of the output terminal is made to ground potential while minimizing sink current flowing from the output terminal, when the output transistor goes into the OFF state.

Abstract: A method for matching output impedance of a driver to a load impedance. In representative embodiments an external impedance is attached between an external contact and a first source potential, wherein the load impedance includes the external impedance plus impedance of interconnections between an output terminal of the driver and the external impedance. An adjustable impedance, which can be field effect transistors which can be turned on separately and in combination to change the value of the adjustable impedance and which can be located on an integrated circuit, are connected between a second source potential and the output terminal of the driver. A reference potential, wherein the reference potential has a value half-way between the first source potential and the second source potential is obtained.

Abstract: A method and apparatus for compensating for gate current through a first capacitor includes: a biasing circuit; a first compensation transistor; a second compensation transistor; and a compensation capacitor. The biasing circuit ensures the bias voltage across the compensation capacitor is equal to the bias voltage across the first capacitor. In addition, the size of the second compensation transistor is chosen such that if, the ratio of the area of the compensation capacitor divided by the area of the first capacitor is area ratio “AR”, then, the ratio of the size of first compensation transistor divided by the size of second compensation transistor is also area ratio “AR”. As a result, according to the method and apparatus of the present invention, the gate current Ig through the first capacitor is equal to the current drained off through second compensation transistor.

Abstract: A current mirror for providing a large current ratio and a high output impedance even in radio frequency operation and a differential amplifier including the same are provided. The current mirror includes a current source for supplying a reference current, a reference transistor, an output transistor, and a proportional-to-absolute temperature (PTAT) voltage generator. The current source has a first terminal connected to a first reference voltage and a second terminal. The reference transistor has a control electrode, a first current carrying electrode connected to the second terminal of the current source, and a second current carrying electrode connected to a second reference voltage. The output transistor has a control electrode, a first current carrying electrode connected to an output terminal to which a mirrored current flows, and a second current carrying electrode connected to the second reference voltage.

Abstract: A leakage compensation circuit and technique is provided that compensates for losses in a referenced current of an amplifier circuit due to leakage elements. The leakage compensation circuit is configured to inject current substantially equal in magnitude to the leakage current into one or more junctions of the amplifier circuit to compensate for lost referenced current due to leakage. As a result, the amplifier circuit and various devices can realize the flow of the reference current as substantially intended without detrimental effects of leakage current, thus maintaining the integrity of the referenced current. The leakage compensation circuit comprises an array of compensation regions configured to approximate the collective loss that is created by the leakage elements and provide a compensation current substantially equal in magnitude to one or more junctions to compensate for lost referenced current.

Abstract: A direct current offset correction system is disclosed for use in an analog signal processing system. The offset correction system includes a comparator unit for comparing the polarity of signals from an analog signal channel and producing a binary output signal. The system also includes a digital accumulator unit that is coupled to the comparator output signal for providing an accumulated average signal over a predetermined period of time. The system also includes a threshold corrective signal unit for determining whether the accumulated signal is within a defined threshold window of acceptable values. The system further includes a correction unit for applying a corrective signal to the analog signal channel.

Abstract: An active feedback loop is provided in a switched-capacitor circuit to automatically cancel both junction and sub-Vth channel leakage. Low power consumption that is crucial for implantable medical devices is achieved. The circuit technique largely minimizes the effective leakage current when the switch is turned off. This circuit technique of the invention can be used in many different circuit applications.

Abstract: A method and apparatus for post-fabrication calibration and adjustment of a delay locked loop leakage current is provided. The calibration and adjustment system includes an adjustment circuit that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor. The capacitor connects to a control voltage of the delay locked loop. Such control of the leakage current in the delay locked loop allows a designer to achieve a desired delay locked loop operating characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the leakage current may be stored and subsequently read to adjust the delay locked loop.

Abstract: An on-chip test bus circuit for testing a plurality of circuits and an associated method. The test bus circuit consists of a test bus and a plurality of switching circuits which selectably provide electrical connections between the respective circuits and the test bus. The plurality of switching circuits are configured to transfer an electrical charge between a node disposed within each switching circuit not selected to provide an electrical connection and a respective charge source or sink. The charge source or sink may consist of a low-impedance, substantially noise-free DC voltage or signal source.

Abstract: Systems and methods that increase the data transmission rate through a given length of optical fiber, or increase the distortion-limited distance for an optical fiber link at a given data rate using band efficient modulation. This is achieved by modulating data for transmission onto a carrier signal. The modulated signal is predistorted and an optical carrier is amplitude modulated using the predistorted signal. The amplitude modulated optical carrier is transmitted over the optical fiber link. The original modulated microwave signal is reproduced at a receiver. The original signal is demodulated to generate the originally transmitted data. In addition, to reduce the bandwidth required by the modulated carrier, it may be single-sideband modulated. By increasing the number of bits per symbol and keeping the symbol rate constant, the data rate for a given length of optical fiber may be increased using the present invention without introducing additional distortion in the fiber.

Abstract: A method of adjusting a circuit operating characteristic. The method includes generating a first signal for application to a reference termination. The method then includes generating a first voltage based on the first signal at a first point on the reference termination and generating a second voltage based on the first signal at a second point on the reference termination. The method also includes adjusting an operating characteristic based upon the first voltage and the second voltage. In an embodiment, the operating characteristic can be an impedance.

Abstract: A self-compensation circuit for terminal resistors includes a current mirror, a reference resistor, a comparator and a plurality of terminal resistors. The current mirror provides a first current through the reference resistor to form a first voltage and a second current through an external resistor to form a second voltage. The comparator compares the first voltage and the second voltage and generates an output voltage that is able to be feedback to the control terminal of the reference resistor. The control terminal of each terminal resistor is connected to the output end of the comparator, thus the resistance of each terminal resistor is able to be proportional to the resistance of the external resistor.

Abstract: A variable offset amplifier circuit includes two differential transistor pairs and a variable current generator coupled to each differential pair to control tail current. Each differential transistor pair has a first transistor and a second transistor. The first transistors are for coupling to first and second loads. A current mirror and shunt is coupled to shunt a portion of current flowing through one of the first transistors from flowing through a correspondingly coupled load. The shunt current is mirrored from one of the second transistors to provide either positive current feedback or negative current feedback. The amplifier circuit has applications in a comparator circuit that also has a regenerative latch circuit, and as a sense amplifier in a receiver of a communications system.

Abstract: A charge pump having a phase-generator circuit generating phase signals and an oscillator circuit supplying a clock signal, a current-limitation circuit to limit the current flowing in the oscillator circuit, and a control circuit supplying on an output a control signal supplied to the current-limitation circuit. The control circuit has a first current mirror connected to a ground line, a second current mirror connected to a supply line, a cascode structure arranged between the first and the second current mirrors and connected to the output of the control circuit to compensate the effects on the control signal caused by sharp relative variations between the potential of the supply line and the potential of the ground line, and a compensation circuit to compensate the effects on the control signal caused by sharp relative variations between the potential of the supply line and the potential of the ground line and by slow variations in temperature.

Abstract: A switched capacitor circuit comprising an operational amplifier, having first and second input terminals and an output terminal, the first input terminal being connected to a first reference potential. The operational amplifier is provided with a negative feedback network including a first capacitive element which is connected between the second input terminal and the output terminal of the operational amplifier, a second capacitive element which has a first terminal alternately connected to the second input terminal of the operational amplifier and to a reference potential, and a second terminal connected to a first circuit node which is alternately connected to a signal input terminal and said first output terminal of the operational amplifier. The circuit further includes a third capacitive element connected between the circuit node and a reference potential.

Abstract: A single external impedance element is used to perform multiple circuit compensation. A reference impedance code is first generated based on matching an internal impedance generated by transistors with an impedance of the external impedance element, and then the reference impedance code can be shifted to generate new impedance codes according to impedance requirements of various different circuits that require compensation. Use of the single external impedance element for compensation of multiple circuits reduces motherboard and packaging costs. Chip area is also conserved since simpler compensation circuits can be used.

Abstract: Signal correction in a bipolar transistor circuit having a base-emitter voltage and a non-linear output signal corresponding to a detectable characteristic is improved by correcting non-linearity in the signal at third and/or higher-orders. According to an example embodiment of the present invention, the output of the transistor is corrected as a function of the base-emitter voltage, the non-linear output signal and a generated non-linearity. The generated non-linearity is adapted to cancel the non-linearity of the non-linear output signal when added thereto. Various implementations of the present invention are applicable to a variety of applications, each of which may have selected characteristics that are accounted for by the generated non-linearity, which is selectively adapted for each particular application. In this manner, third and higher-order corrections can be made, and the detection of characteristics such as data, temperature and other terms is improved.

Abstract: System for generating a reference current in a semiconductor device. The reference current is compared to an internal device current generated by an internal device circuit to verify operation of the device. The system includes a current generator that generates the reference current and is located within the semiconductor device, and a bias generator that is coupled to the internal device circuit. The bias generator generates a back bias current to offset variations to the reference current.

Abstract: A differential discrete-time signal processing channel differentially processes cardiac signals in an implantable cardiac rhythm management device. Such signal processing effectively uses downsampling to uses lower bias currents, thereby saving power and prolonging the life of the implanted device, and also reduces clock feedthrough, provides a wider dynamic range and better rejection of power supply noise. The device includes a continuous-time buffer, a decimator/averager and/or other filter and/or amplifier circuits, and an analog-to-digital converter, each configured for processing differential signals. The device also includes an operational transconductance amplifier (OTA), for the discrete-time differential signal processing. The OTA provides, among other things, an output common mode adjustment circuit and an offset compensation circuit.

Abstract: Apparatuses, systems, and methods which compensate for distortion of optical and electrical signals being transmitted by communications systems and components by changing the effective length of communications cables and waveguides.

Abstract: The device and method monitor the current delivered to a load through a power transistor including a sense transistor. The circuit includes a disturbances attenuating circuit that has a differential stage, and first, second and third stages referenced to ground, the respective input nodes of which are connected in common to an output node of the differential stage. The third stage is formed by a transistor identical to a transistor of the first stage and delivers a current signal through a current terminal thereof, proportional to the current being delivered to the load.

Abstract: An input bias current reduction circuit for multiple input stages having a common input includes a plurality of input stages each including a first input transistor with its base connected to the common input and the first current sensing transistor with its collector-emitter in series with the collector-emitter of the first input transistor and its base current replicating that of the first transistor; and a current compensation circuit for sensing the base current of the first current sensing transistor in each input stage and subtracting that from the base current of the first input transistor in each input stage for maintaining constant reduced current loading of the input.

Abstract: The distortion compensating circuit for an electrooptic converter includes a secondary distortion generating circuit 12, an amplitude vs. frequency characteristic compensating circuit 16 provided at an output coupling of the secondary distortion generating circuit, a distributing directional coupler 14 for distributing an RF signal provided at a previous stage of the secondary distortion generating circuit, a tertiary distortion generating circuit 13 provided at a coupling port of the distributing directional coupler, an amplitude vs. frequency characteristic compensating circuit 26 provided at a posterior stage of the tertiary distortion generating circuit, a phase vs.

Abstract: Signal correction in a bipolar transistor circuit having a base-emitter voltage and a non-linear output signal corresponding to a detectable characteristic is improved by correcting non-linearity in the signal at third and/or higher-orders. According to an example embodiment of the present invention, the output of the transistor is corrected as a function of the base-emitter voltage, the non-linear output signal and a generated non-linearity. The generated non-linearity is adapted to cancel the non-linearity of the non-linear output signal when added thereto. Various implementations of the present invention are applicable to a variety of applications, each of which may have selected characteristics that are accounted for by the generated non-linearity, which is selectively adapted for each particular application. In this manner, third and higher-order corrections can be made, and the detection of characteristics such as data, temperature and other terms is improved.

Abstract: A leakage current compensation system and method is disclosed that reduces frequency spurs and phase offset in a frequency synthesizer. The leakage current is determined based on the phase offset of the frequency synthesizer relative to a reference clock. A leakage current compensation circuit provides a leakage current compensation signal to the frequency synthesizer at the loop filter terminals to minimize the phase offset.

Abstract: Disclosed is a source follower with Vgs compensation, such that the output voltage precisely follows the input voltage by various arrangements of MOSFET's, switches, and capacitors. In addition, such a source follower that the output voltage precisely follows the input voltage can be implemented without adding too many components. The source follower disclosed in the present invention can be used in the driver circuit for a liquid crystal display (LCD).

Abstract: The circuit configuration compensates runtime and pulse-duty-factor differences of two input signals having approximately equal frequency and phase. For each input signal respectively present at an input of the circuit configuration, a signal path is provided that, dependent on the state of the output, is influenced in such a way that the output signal follows the input signal that changes first. A feedback branch with a time-delay element feeds back the output signal to the inputs with a delay, in such a way that these inputs are prepared for the next change of input signal. The delay time of the time-delay element is greater than the maximum chronological deviation between the two input signals.

Abstract: A distortion control circuit for selective modulation of an RF signal includes an input port for coupling with an RF signal source, such as a multifrequency CATV signal, an output port for coupling to an associated RF amplifier, and a pair of selectively biased diodes for generating new third order products from the multifrequency RF signal which are the same magnitude, but opposite in phase to the nonlinear products generated by the RF amplifier. Since both the original multifrequency RF input signal and the new generated products from the distortion control circuit are applied to the input of the RF amplifier, the nonlinear products from the distortion control circuit and the RF amplifier will be canceled and the output of the RF amplifier will comprise only the multifrequency RF signal.

Abstract: A method and a device for generating a substantially temperature independent current (I1) are described. To generate this current (I1), a conventional current generator circuit including an operational amplifier (11) controlling a transistor (12) having one (12a) of its current electrodes (12a, 12b) connected to a resistor (13) and to an input terminal (11b) of the operational amplifier (11), is used. According to the invention, a temperature stable input voltage (Vin) is applied at the other input terminal (11a) of the operational amplifier (11), and the latter is arranged so that it has an offset voltage (Vos(T)) between its input terminals (11a, 11b) having a temperature dependence, this offset voltage (Vos(T)) and the input voltage (Vin) being adjusted to compensate for the temperature dependence of the resistor (13) such that the current generated (I1) is substantially temperature independent.

Abstract: Signal correction in a bipolar transistor circuit having a base-emitter voltage and a non-linear output signal corresponding to a detectable characteristic is improved by correcting non-linearity in the signal at third and/or higher-orders. According to an example embodiment of the present invention, the output of the transistor circuit is corrected as a function of the base-emitter voltage, the non-linear output signal and a generated non-linearity. The generated non-linearity is adapted to cancel the non-linearity of the non-linear output signal. Various implementations of the present invention are applicable to a variety of applications, each of which may have selected characteristics that are accounted for by the generated non-linearity, which is selectively adapted for each particular application. In one implementation, the non-linearity is generated using two or more division circuits.

Abstract: A signal compensation circuit compensates for direct-current offset of an input signal by amplifying the input signal with an amplifier having a variable direct-current offset. A low-speed negative feedback loop charges and discharges a capacitor in an integrating circuit according to the direct-current component of the amplified signal. A high-speed negative feedback loop charges and discharges the same capacitor at a faster rate when the amplified signal goes outside an allowable amplitude range. The capacitor potential is used to control the direct-current offset of the amplifier. The allowable amplitude range is adjusted according to the amplitude of the amplified signal. High-speed compensation can thus be combined with a tolerance for runs of identical code levels in the input signal.

Abstract: The difference between the Vgs voltages of first and second MOS transistors of an integrated circuit due to variations in the production process and/or to variations of other parameters is compensated by a compensation circuit. The compensation circuit includes third and fourth MOS transistors that are the same type as the first and second transistors. These transistors are all formed in the same integrated circuit. The compensation circuit includes a bias circuit for biasing the third and fourth transistors, and a measurement circuit for measuring the difference between the Vgs voltages of the third and fourth transistors. The compensation circuit further includes a current compensation circuit for generating a compensation current that is a function of the difference measured, and a modification circuit for modifying the biasing of the first and second MOS transistor using the compensation current.

Abstract: A multi-stage, low-offset, fast-recovery, comparator system and method for: reducing the input offset voltage of the zeroing amplifier by a factor essentially equal to gain of the zeroing amplifier; reducing the input offset voltage of the combined main and zeroing amplifiers by a factor essentially equal to the product of the gains of the main and zeroing amplifiers; and amplifying the input signal to the amplification stage in accordance with the gain of the main amplifier to generate an amplified high-resolution signal.

Abstract: A system and method for providing automatic compensation of IC design parameters that vary as a result of natural process variation is disclosed. In a simplified embodiment, the difference in voltages, &Dgr;VGS, between two identical diode-connected MOSFETs, which are biased with currents that are known to be different in value, is determined. &Dgr;VGS, is inversely proportional to the transconductance of the first of the two diode-connected MOSFETs, which is also biased with a current, ID. A relationship that embodies a direct proportionality between the transconductance of the first diode-connected MOSFET and a circuit performance parameter is derived, thereby establishing a relationship between &Dgr;VGS and the circuit performance parameter. Process compensation is then implemented, comparing known reference voltages with &Dgr;VGS.