Abstract: Described is a circuit for receiving a differential input signal at two substantially symmetrically built up current paths and for providing an output signal therefrom. At least one current path comprises means for adjusting the timing information of the input signal to the timing information of the output signal. The adjustment can be accomplished by modifying a voltage level in the respective current path until the timing information of the output signals at least substantially represents the timing information of the input signal, e.g. by modifying an impedance or a current in the respective current path. The adjusting of the timing information is executed by applying a defined input signal with a known timing information, comparing the timing information of the resulting output signal with the timing information of the input signal, and modifying at least one voltage level in at least one of the current paths until the timing information of the output and input signals at least substantially match.

Abstract: A transisterized circuit may be driven with a low voltage without saturation of a direct current operating voltage point. The transisterized circuit includes a first transisterized circuit formed by a cascade connection of a first differential transisterized circuit and a first emitter follower circuit, a second transisterized circuit formed by a cascade connection of a second emitter follower circuit and a second differential transistor circuit, and an inversion circuit connected between said first transisterized circuit and said second transistor circuit.

Abstract: A compensation circuit which accounts for variations in both temperature and V.sub.CC supply voltage on an integrated circuit. The compensation circuit includes four quasi-independent compensation current sources, each of which generates a corresponding compensation current. The first compensation current source generates a first compensation current which has a positive slope with respect to temperature. The second compensation current source generates a second compensation current which has a negative slope with respect to temperature. The third compensation current source generates a third compensation current which has a negative slope with respect to the V.sub.CC supply voltage. The fourth compensation current source generates a fourth compensation current which has a positive slope with respect to the V.sub.CC supply voltage. The first, second, third and fourth compensation currents are summed to create a total compensation current.

Abstract: An analog signal transmission circuit includes a transformer, an amplifier for driving the transformer, first and second polar capacitors connected in series between the amplifier and the transformer such that those terminals of the first and second polar capacitors which have the same polarity are connected to each other, and an element, connected to the terminals of the first and second polar capacitors, for applying a DC bias in accordance with the polarity of the terminals of the first and second polar capacitors.

Abstract: A structure and a method are provided to receive a high-impedance reference voltage signal and generate a desired output signal that is capable of sourcing enough current to meet the demands of a fixed-resistance load. In such a circuit, the signal from an accurate, wide output-swing voltage source circuit having low quiescent current is combined with the output of a current source circuit so that the voltage input to the load is maintained even as the necessary current is supplied. The current source circuit preferably includes a tracking resistance that sinks a control current which a current mirror multiplies by the same ratio as that between the tracking resistance and the load resistance.

Abstract: A supply and temperature dependent linear signal generating circuit includes four transistors each having a unique current flowing therethrough and connected together to form a current multiplier. A first one of the currents is designed to be supply dependent and preferably adjustable in magnitude, a second one is designed to exhibit a specific temperature dependence, the third is designed to be both supply and temperature independent and the fourth current is defined as a ratio of the first three. The fourth current is, in one embodiment, impressed upon a network defined by a resistor divider and a voltage source to thereby define an output voltage V(T) that is both supply and temperature dependent according to the following equation:V(T)=KX*(T-TN),wherein KX is the slope of V(T) over temperature, T is the operating temperature and TN is a reference temperature at which V(T) is equal to zero. Preferably, TN is adjustable via the adjustable magnitude of the first current.

Abstract: The output (3) of a level shifter (1) is split into two paths (4,5) with a delay (.tau..sub.1, .tau..sub.2) being introduced into at least one path to enable rise delay and fall delay to be controlled independently of one another. In the context of an integrated circuit which includes a memory device, the use of an additional path allows control of the set-up and hold times in that one transition can be speeded up or slowed down independently of the other transition to achieve the best possible set-up and hold times.

Abstract: A capacitor is connected between the gate of a transistor that is an object of threshold voltage compensation and an input terminal. A switching device is connected between a current source connected to one terminal of the transistor and the gate of the transistor. A second switching device is connected between the input terminal and a terminal to which a reference voltage is applied. The switching device is turned ON so that the transistor is diode-connected. The switching device is turned ON, thus applying the reference voltage to the input terminal. A reference voltage is applied to a current inflow terminal connected to another terminal of the transistor. After charge dependent on the threshold voltage of the transistor is accumulated in the capacitor, the switching device is turned OFF. With this control, a difference of a threshold voltage from another deriving from the fine structure of transistors as well as a difference in threshold voltage between adjoining transistors can be compensated for.

Abstract: A simply structured clock pulse generator operating stably in a wide range of frequencies in response to a timing signal fed from outside a semiconductor integrated circuit. A first frequency signal fed from the external terminal of the semiconductor integrated circuit and a second frequency signal generated within the semiconductor integrated circuit are input to a phase comparator. The output signal of the phase comparator is smoothed by a low-pass filter for conversion to a voltage signal. A compensation circuit uses both a delay signal from a current-controlled delay circuit receiving the first frequency signal and the first frequency signal to generate a current signal corresponding to the frequency of the latter signal. The voltage signal generated by the low-pass filter is converted into a current signal.

Abstract: A compensation circuit adapted to receive an input signal for a circuit element to be compensated. The input signal is used as an address to a memory at which a compensated signal is stored. The stored compensated signal is output to the circuit element as the compensated signal therefor. In a specific implementation, the command input is received by a shift register. The shift register converts a serial input to a parallel output. The parallel output of the shift register is combined with the output of a temperature sensor to provide an address for the memory. The command input data includes an address to the particular circuit element to be compensated. The temperature data is used to select a particular page of memory and the remainder of the command input data is used to select data from that page for output as the compensated signal for the selected element. In the illustrative embodiment, the components compensated are automatic gain control amplifiers.

Abstract: A voltage comparator for comparing a first input voltage to a second input voltage includes a first transistor having a gate to which the first input voltage is applied and a second transistor having a gate to which the second input voltage is applied. Third and fourth transistors, coupled to the first and second transistors respectively, each conduct a first current in response to a first reference voltage being applied to a gate of each transistor. A fifth transistor is coupled to the first and second transistors and has a gate to which a second reference voltage is applied to maintain a sum of currents conducted by the first and second transistors equal to a second current. A reference generation circuit is coupled to the third, fourth and fifth transistors and is configured to generate the first and second reference voltages having magnitudes which set the second current equal to twice the first current.

Abstract: In a photodetector amplifier scheme, the invention compensates for variations in photodetector quiescent current by sampling the amplifier output and subtracting a controllable current from the input to the amplifier. When a chopper or other modulator is used on the optical signal, the samples are taken periodically during the chopping cycle. This sampled signal is processed by a combination of gain and low pass filtering. The result of this processing controls a current source which subtracts a significant fraction of the average quiescent current from the total detector current. In a typical application, the amplifier is of the resettable current integrator type. In this case, the invention makes it possible to use smaller integration capacitors resulting in larger signals than if the quiescent current were not reduced by the operation of the invention. The gain, frequency response, and range of compensated quiescent currents and can be altered by changing timing signals.

Abstract: A aperture compensation circuit which provides improvement in picture quality when a multi-media image is displayed and an RGB monitor employing the same includes a sharpness circuit provided between input terminals and a preamplifier. A lowest value detection circuit of the sharpness circuit detects a lowest value signal from among R, G and B signals supplied from the input terminals, and a differentiation circuit differentiates the lowest value signal to produce a differentiation signal. A slice circuit slices a component of the differentiation signal which corresponds to a portion at which a change from black to white occurs with an arbitrary amplitude to produce a second differentiation signal. The second differentiation signal from the slice circuit and the R, G and B signals supplied from the input terminals are added by addition circuits to effect contour correction of the R, B and G signals. A CRT is driven by the R, G and B signals for which contour correction has been performed.

Abstract: An MOS FET circuit with a summing circuit at the input of an amplifier to provide charge cancellation. The summing circuit is capacitively coupled to the input with a charge cancellation capacitor. A separate amplifier, having components substantially the same as the components of the first amplifier, is connected through the charge cancellation capacitor to the first amplifier.

Abstract: A method and system of frequency multiplying a signal having amplitude modulation using a frequency multiplier operated at a bias voltage that is less than its saturation mode voltage is described. Prior to amplification, the amplitude modulated signal is pre-distorted to compensate for distortion caused by the frequency multiplier. A first pre-distortion phase converts the amplitude modulated signal into a corresponding square root signal to compensate for a first distortion type. A second pre-distortion phase pre-distorts the square root signal to compensate for the distortion caused by biasing the frequency multiplier at a voltage less than the saturation voltage of the multiplier. As a result, a signal that is amplitude modulated can be multiplied by a frequency multiplier.

Abstract: A dynamic voltage reference circuit for generating one or more control signals for use in controlling a delay circuit or other circuit that requires compensation for process variations. The control signals are generated without drawing DC current at times other than when the active edge is propagating through the delay circuit. As a result, a reference generator with reduced power consumption is realized.

Abstract: A transistor-bias voltage stabilizing circuit comprises a current saturating resistor connected in series to the output of an FET, the gate bias voltage of which is to be stabilized and a capacitor connected in parallel to the current saturating resistor. The transistor-bias voltage stabilizing circuit may comprise a voltage detecting circuit and a negative-feedback circuit connected between the input and output of an FET, the gate bias voltage of which is to be stabilized.

Abstract: The MOSFET of the invention has a switching element connected between its gate and its source. The switching element causes a reduction of the gate-to-source voltage of the MOSFET. The switching element is driven via a diode, which is connected in the blocking direction between the drain of the MOSFET and a control terminal of the switching element.

Abstract: A low-power op-amp circuit (70) having boosted bandwidth comprises a DC circuit block (72) which is coupled to first (V.sub.DC +, V.sub.DC +, V.sub.AC +) and second (V.sub.DC -, V.sub.AC) input nodes and to an output node (V.sub.OUT) of an output stage (90). The DC circuit block (72) amplifies a differential signal received from the first (V.sub.DC +, V.sub.AC +) and second (V.sub.DC -, V.sub.AC) input nodes, and provides an amplified signal to the output node (V.sub.OUT). An AC circuit block (74) is coupled to the output (NODE 3) of the DC circuit block (72). The AC circuit block (74) is operable to monitor a transient change between the first (V.sub.DC +, V.sub.AC +) and the second (V.sub.DC -, V.sub.AC -) input nodes. The AC circuit block (74) is further operable to transfer charge to the output node (V.sub.OUT) in response to the transient change, thereby providing boosted bandwidth beyond that of the DC circuit block (72) alone.

Abstract: A circuit for compensating for the input offset voltage of a logarithmic amplifier includes a digital comparator, a logic circuit, and a digital-to-analog converter (DAC) in a feedback loop. The comparator is connected to the output of the log amplifier and digitally indicates the polarity of the input offset voltage when the amplifier input is set to zero. The logic circuit uses the digital output of the comparator to form an adjustable digital compensation signal. This digital compensation signal is applied to the DAC to generate an analog compensation signal that is injected into the input of the logarithmic amplifier to cancel the input offset voltage. The process is repeated until the proper or best compensation signal is produced.

Abstract: The odd harmonic distortion components in the output signal of a capacitively loaded follower transistor is reduced by means of an additional transistor inserted between the emitter of the follower transistor and the bias current source of the follower transistor. A second follower transistor receives the same input signal as the follower transistor and has its emitter coupled to the emitter of the additional transistor via a compensation capacitor. The current through the compensation capacitor is added to the output current and compensates for the odd harmonic distortion.

Abstract: A comparator with output that responds quickly to changes in input. The comparator is made up of three stages, an input sampling network, a first amplifier stage, and a second amplifier stage. The input sampling network interfaces the two voltage levels that are to be compared with the first amplifier stage. The first amplifier stage then generates a low level signal that is dependent on the relative levels of the two inputs and passes the low level signal to the second amplifier stage. The second amplifier stage amplifies the output of the first amplifier stage to a usable level. Superior response time is achieved through by dividing the input sampling network into two stages, an input stage and an offset stage, and decoupling the two stages during offset cancellation.

Abstract: A current sensing circuit which provides for accurate in-line current sensing with extremely low insertion loss. A low valued resistor (e.g., 0.005 ohms) is connected in series with the source and load of the current to be measured. An analog-to-digital converter (ADC) is used to measure the resulting voltage generated across the resistor. In order to minimize inaccuracies due to voltage offsets introduced by the measurement circuitry when measuring the low voltages generated across such a low resistance, the ADC is "chopped," thereby causing self cancellation of any such offset voltages. A voltage source which provides a reference voltage for the ADC has a temperature coefficient which is approximately equal in magnitude to the temperature coefficient of the resistor. Hence, for a given current through the resistor, the reported voltage as measured across the resistor remains constant over temperature.

Abstract: A description is given of a circuit arrangement comprisinga filter quadripole having two output terminals anda voltage follower circuit having two terminals, said terminals having identical electric potentials when the voltage follower circuit is in its turned-on state, each of the terminals of the voltage follower circuit being connected to one of the output terminals of the filter quadripole respectively, and the voltage follower circuit only being in its turned-on state during the turn-on time interval of the circuit arrangement. This circuit arrangement is suitable for a receiver circuit, more particularly, for a pager and has a very brief turn-on time.

Abstract: A reference potential difference canceling circuit is provided in a circuit system of a transmitter side to remove noise caused by impedance Z between circuit systems having different reference potentials from a signal, and to transmit the signal. The reference potential of the circuit system of a receiver side is supplied to an input terminal of the reference potential difference canceling circuit, and its output terminal is connected to an input terminal of an output amplifier to which a transmitting signal is input. A gain of the reference potential difference canceling circuit is set to a reciprocal number of a gain of the output amplifier.

Abstract: An input buffer circuit has a switching point accurately set according to the input logic level, even when the input buffer circuit has a low supply voltage. The switching point is set according to an internal reference voltage of equal magnitude to the desired switching point that is applied to a current source. The current source accurately sources (or sinks) a current matching the current flowing in an input inverter when the input logic level substantially equals the reference voltage. At that point, the voltage at the output of the input inverter is substantially equal one half of the supply voltage. When the input logic level is slightly below or above the reference voltage, the output of the input inverter is near the supply or ground rail, respectively. Hysteresis is added to compensate for noise that may exist on the input logic signal.

Abstract: A comparator with a built-in offset is disclosed. The comparator includes a bias current circuit, a differential input stage with the built-in offset, and a hysteresis circuit. The built-in offset is generated by using a resistor in the differential input stage of the comparator such that the resistor is driven by the bias current as well as the current generated by the hysteresis circuit. Additionally, a reset circuit which uses the comparator with the built-in offset is described. The reset circuit uses a voltage divider circuit to divide a first input voltage to the comparator. A band-gap voltage reference is used to provide a second input voltage to the comparator. Therefore, the reset circuit generates a reset signal when the divided voltage reaches the value of the band-gap voltage plus the offset. In another embodiment, a comparator having a differential input stage, an output stage, and a bias circuit with a hysteresis circuit is disclosed.

Abstract: An analog front end for signal processing circuit such as a hard-disk data read channel having a calibration circuit for canceling DC offset is described. First, the DC offset is cancelled from a positive phase input to an A/D converter (ADC). Second, a DC offset is cancelled separately from a negative phase input to the A/D converter. The combined positive and negative phases form an amplified analog signal that is used as the differential input to the A/D converter. Finally, the DC offset in a path that encompasses the system analog input through the system digital output is cancelled. Controlling the buffer amplifier bias makes trimming unnecessary. It also enables faster calibration. Further, the two differential phase lines, i.e., the positive phase line and the negative phase line, are each calibrated in turn. As such, a common calibration circuit may be used, thereby avoiding circuit duplication.

Abstract: A boost type equalizing circuit, being an equalizing circuit used in a signal reproducing circuit of memory device such as an optical disk drive and hard disk drive, and comprising boost units 4, 6, which is used for compensating distortion caused in reproduced signal of information recording medium, and compensating frequency characteristic of reproduced signal. The boost units 4, 6 are composed so that the numerator of the transfer function may have an even-number order term of fourth power or more of Laplace operator s. A boost equalizing circuit of excellent cut-off characteristic in high frequency range can be presented.

Abstract: A voltage offset compensation circuit for a high gain amplifier having a fixed input voltage offset, includes sample and hold circuitry for periodically sampling the offset voltage and gain error voltage of the amplifier, and holding the sampled voltage; storage circuitry, operable between sampling periods, to store the sampled and held voltage; and further circuitry, operable during the sampling periods, to continuously maintain the output of the high gain amplifier at a value that is gain error and voltage offset compensated. The voltage offset compensation circuit may be used in sampled-data circuits, or continuous-time amplifier circuits utilizing either single-ended, or differential, inputs and either single-ended, or differential, outputs.

Abstract: A circuit and associated method for determining the offset bias of a comparator by first shorting together the inputs of the comparator to apply the same voltage signal at each of the inputs of the comparator. The voltage signal at one of the inputs is then offset a select amount by applying varying selected resistances from a variable resistor to the comparator. The variable resistor is controlled by a programmable controller that is responsive to an input clock signal. At each selected amount of offset applied to the input, the output is monitored to determine if the output of the comparator has flipped, or changed state. When the output flips, the corresponding resistance setting is used to compensate for the corresponding offset bias of the comparator.

Abstract: Temperature and technology-independent self-calibrating monolithic logarithmic amplifier systems that use integrated cascades of current-summing or voltage-summing differential-limiter gain stages are disclosed. Each stage is trimmed and stabilized by a respective bias replicator cell and a current mirror cell. The bias replicator provides a bias current control signal in response to a change in a given difference between bias currents in a differential pair of amplifiers controlled by a predetermined differential calibration voltage. The differential pair is identical to a differential pair in the limiter amplifier. The differential calibration voltage E.sub.lin is well-within the linear portion of the amplifier's transfer curve during operation, so that the proportional relation between E.sub.k and E.sub.lin, which is the same as that between the given difference between currents and the correct bias current value I.sub.B, remains constant throughout.

Abstract: An amplifier is connected to a voltage subtractor which is connected in a predetermined current path of the amplifier to adjust the temperature-dependent voltage offset of an amplifier or of an amplifier chain. If the voltage subtractor is connected at the output of the amplifier or of an amplifier chain, then the temperature-dependent offset voltage can be subtracted using suitable means, without the amplifier itself having to be compensated. As a voltage subtractor, an operational amplifier is proposed, in the case of which the offset voltage is subtracted by means of negative feedback. The negative feedback is produced by means of a resistor having two current power sources. The voltage subtractor is preferably connected in outgoing circuit to the amplifier and constructed in accordance with the same layout rules.

Abstract: A plurality of MOS transistors connected to each other at a substrate electrode thereof to have a substrate potential are deviation-compensated by a combination of a power source having a power source potential independent from the substrate potential, a power supply line connected to a source electrode of each of the MOS transistors, a sample circuit composed of a sampled one of the MOS transistors, detection circuitry for detecting an action of the sample circuit to provide a detection signal representing a difference between the detected action of the sample circuit and a reference action therefor, and a voltage generator connected between the power source and the power supply line, the voltage generator generating a voltage depending on the detection signal.

Abstract: A bias current controlling circuit minimizes the power consumption of a high-frequency power amplifier incorporated in a battery powered portable telephone by controlling a bias current supplied to the high-frequency power amplifier in such a manner that an output signal of the high-frequency power amplifier increases the distortion as large in an allowable range as possible, because the bias current is inversely proportional to the magnitude of the distortion.

Abstract: An electronic circuit provides a linear output from a nonlinear transmission device such as a laser. Second and higher order distortion of the nonlinear device is compensated by applying a predistorted signal equal in magnitude and opposite in sign to the real and imaginary components of distortion produced by the nonlinear device. The input signal for the nonlinear device is applied to an in-line electrical path coupled to the nonlinear device. The in-line path contains at least one component for generating primarily real components of distortion. In some applications, at least one component for generating imaginary components of distortion is located on the in-line path. Filter stages are used to provide frequency dependent predistortion. In a preferred embodiment, an attenuator, a MMIC amplifier, a CATV hybrid amplifier, and a varactor in line with a semiconductor laser, provide the predistorted signal.

Abstract: An electronic gain circuit adapted to receive an input signal, an amplifier having a gain for amplifying the input signal to produce an output signal, and biasing resistors connected to the amplifier to automatically adjust the gain of the amplifier in response to fluctuations in ambient temperature such that the output signal of the amplifier responds to ambient temperature fluctuations.

Abstract: The invention exploits the phenomenon of stochastic resonance in a nonlinear dynamic system to enhance the system's response to a weak periodic signal locally corrupted by background noise. The invention is designed to enhance the signal-to-noise ratio (SNR) in the system's output power spectrum at the periodic signal's frequency. This technique utilizes an array of nonlinear dynamic elements whose individual outputs are specifically coupled to other array elements. The coupling is found to substantially enhance the output SNR over what would be expected from a signal processor based upon a single such element. This principle has the potential to substantially enhance the performance of arrays of nonlinear devices; in fact, the nonlinear array can be expected to yield an output SNR that is very close to that obtainable by an array of ideal linear devices, so that the coupling actually "linearizes" the nonlinear system.

Abstract: A current mirror circuit includes a current input terminal; a first FET and a second FET, each having a gate terminal, a drain terminal, and a source terminal, the gate terminal of the first FET being connected to the gate terminal of the second FET; a third FET having a source terminal connected to the drain terminal of the first FET, and a drain terminal and a gate terminal connected to each other and to the current input terminal; and a fourth FET having a source terminal connected to the drain terminal of the second FET, a gate terminal connected to the gate terminal of the third FET, and a drain terminal serving as a current output terminal. Therefore, even when the output voltage varies, since the current is almost constant, the circuit is not adversely affected by the variation in the output voltage. As a result, error in the output current in response to variations in the output voltage is significantly reduced.

Abstract: An integrated circuit chip for determining when the frequency of a clock pulse input signal is below a predetermined threshold level and including a capacitor charged up by a current source to produce a linearly-varying ramp signal. The charging circuit includes two MOS transistors, one arranged as a resistor to control the charging current, the other arranged as a capacitor to be charged. When the oxide layer produced by the IC process for making the chips varies in thickness from one batch of chips to a subsequently produced batch, the effect on the charging of the MOS capacitor resulting from the change in capacitance of the previously produced chip is at least partly compensated for by the corresponding change in resistance of the MOS resistor, thereby tending to maintain the charging rate constant.

Abstract: An electronic circuit having a circuit stage, such as a switched capacitor stage or a 1-bit digital-to-analog converter and switched capacitor filter, that is loaded with a load impedance employs current feedforward to substantially cancel effects of the load impedance. A circuit includes a circuit stage and a load impedance following and connected to the circuit stage. A current feedforward circuit is connected to the load impedance, substantially cancelling the load impedance to improve linearity of the digital-to-analog converter or switched capacitor filter.

Abstract: A simple, low-cost circuit and method for line zing parasitic capacitances of transistor junctions, independent of the process technology employed, are provided. In the preferred embodiment, the parasitic capacitance of a transistor in a track and hold circuit is linearized by providing a pair of diodes that act inversely to the parasitic diodes formed within the integrated circuit during normal tracking operations. Without the diodes of the present invention, the varying input signals cause the parasitic capacitance to vary, thereby causing harmonic distortion in the track and hold circuit. An alternate embodiment of the present invention is also provided in which a second complementary transistor is provided. The inclusion of the complementary transistor results in a second set of parasitic capacitances that are substantially opposite the parasitic capacitances of the track and hold transistor.

Abstract: A level detector 2 detects variation of the amplitude of an input signal a to output a level signal b representing HIGH or LOW in order to define the head portion of the input circuit a. A time constant control signal 3 generates a time constant control signal c based on the level signal b to control a time constant of an estimator 4 so as to make the time constant small for a prescribed period from a time when the level signal b varies from HIGH to LOW. The estimator 4 estimates DC offset included in the input signal a with the a time constant variation according to the time constant control signal c to output an estimate d. A compensator 1 subtracts the estimate d from the input signal a to obtain a compensation output. Therefore, in the estimator 4, the speed of estimating the DC offset is different between a period corresponding to the head portion of the input signal a and other periods.

Abstract: A plurality of MOS transistors connected to each other at a substrate electrode thereof to have a substrate potential are deviation-compensated by a combination of a power source having a power source potential independent from the substrate potential, a power supply line connected to a source electrode of each of the MOS transistors, a sample circuit composed of a sampled one of the MOS transistors, detection circuitry for detecting an action of the sample circuit to provide a detection signal representing a difference between the detected action of the sample circuit and a reference action therefor, and a voltage generator connected between the power source and the power supply line, the voltage generator generating a voltage depending on the detection signal.

Abstract: A circuit for providing an input offset voltage to balance a fully differential amplifier may include two field effect transistors (FETs) in parallel conductive paths for receiving a current, an amplifier current source, a resistor connecting the FETs at their drains, and a second amplifier with inputs for an offset correction voltage and for a reference voltage on which the fully differential amplifier is to be balanced and outputs for providing control inputs to the FETs. The input offset voltage for balancing the fully differential amplifier is the difference between currents in the parallel paths times the resistance of the resistor. The circuit may be used to balance a fully differential amplifier in a telephone CODEC. The correction voltage may correct the total offset from the CODEC, or the offset introduced by a sign bit integrator that provides a correction for excursions of the same polarity in the CODEC.

Abstract: In a summing comparator (10) in which one differential input voltage received by one differential pair (18) is dependent on temperature variations, such as across a resistor (12) with a large temperature coefficient, the dependence on temperature is offset by introducing cancelling temperature dependence in the other differential pairs (14, 16).

Abstract: An electronic circuit with an operation self-control function includes an electronic circuit body. A temperature sensor and a temperature-setting circuit detect the temperature of the electronic circuit body as an operating parameter indicative of an operating condition of the electronic circuit body, and a clock/peripheral circuit control circuit operates to restrict the operation of the electronic circuit body according to the detected temperature, to thereby restrain heat generation of the electronic circuit body.

Abstract: An analog multiplier includes at least a differential output stage formed by a pair of emitter-coupled bipolar transistors. Each transistor of the pair of emitter-coupled bipolar transistors is driven by a predistortion stage having a reciprocal of a hyperbolic tangent transfer function that is attributable to the base currents of the bipolar transistors used in the predistortion stage. The error in the output signal produced by the analog multiplier is compensated by generating replicas of the base currents of the bipolar transistors of the differential output stage and forcing those replica currents on the output node of a respective predistortion stage. Various embodiments that consume different amounts of power are described.

Abstract: A circuit for providing parameter compensation to a drive transistor of logic circuit A. A regulating transistor circuit B is connected in series with the drive transistor in order to limit the current in the drive transistor. Bias circuitry C is also provided for supplying a bias voltage Vb to a gate of the regulating transistor circuit B, wherein the voltage is responsive to a predetermined parameter. The bias circuitry C comprises an element which is sensitive to the predetermined parameter.

Abstract: An offset cancel circuit includes two terminals, an output terminal and two intermediate nodes. When the offset cancel circuit is in a first state, the offset cancel circuit supplies a potential difference responsive to a difference in potential between the two terminals between the two intermediate nodes and supplies a potential responsive to both the potential difference supplied between the two intermediate nodes and a first potential to the output terminal. On the other hand, when the offset cancel circuit is in a second state, the offset cancel circuit supplies a potential difference responsive to the difference in potential between the two terminals between the two intermediate nodes and supplies a potential responsive to both the potential difference supplied between the two intermediate nodes and a second potential to the output terminal.