Abstract: A predistortion circuit (102) includes a signal splitter (114), a diode network (118) and a signal combiner (116). The signal splitter (114) is splits an input signal into two portions. One of the signal portions is passed through the diode network (118) and combined with the other portion of the input signal in the signal combiner (116). The diode network (118) includes a plurality of diode circuits (204,206), each including two diode branches (208-214) coupled to an electrical ground (220). The resulting predistorted signal at the output (106) of the signal combiner is amplified, amplitude adjusted and injected into the nonlinear device (112). The input signal is predistorted such that distortion due to nonlinear characteristics of the nonlinear device (112) is reduced.

Abstract: A nonlinearity compensation circuit is disclosed which includes an inverse hyperbolic function generation circuit for converting differential currents corresponding to input signals in+ and in− into differential voltages which increase in proportion to an inverse hyperbolic function, an offset provision circuit for providing an offset corresponding to control signals c+ and c− to the differential voltages outputted from the inverse hyperbolic function generation circuit and a hyperbolic function generation circuit for converting the differential voltages to which the offset has been provided by the offset provision circuit into signals which increase in proportion to a hyperbolic function and outputting the resulting signals as output signals out+ and out−. Consequently, compensation for the nonlinearity such as second order distortion can be performed for the read signal from a recording medium.

Abstract: Driver circuitry (300) is disclosed, incorporating feedback circuitry (310) inter-coupled with reference circuitry (348) to equalize the voltage level of an output (328) with a reference voltage source (320) in the reference circuitry; where the driver circuitry comprises a first transistor (340) having a first terminal coupled to a voltage source (342), a second terminal coupled to an input (336), and a third terminal coupled to a resistor (344), a second transistor (338) having a first terminal coupled to ground (332), a second terminal coupled to an input (334), and a third terminal coupled to a resistor (346), a third transistor (318) having a first terminal coupled to the output, a second terminal (326) coupled jointly to the resistors, and a third terminal coupled to ground, and a resistor (330) coupling the output to a voltage source (306).

Abstract: An LVDS (Low Voltage Differential Signal) driver circuit having low sensitivity to fabrication process variation, power supply noise voltage variation, and operating temperature variation (PVT). The LVDS driver circuit includes a predriver having an input coupled to an internal circuit. The predriver is coupled to a current source. The current source includes a first resistance and is configured to produce a reference current through the first resistance. The reference current is coupled to the predriver to control an output swing of the predriver, the output swing determined by a ratio of the first resistance and a second resistance in the predriver. The ratio of the first and second resistance is such that the output swing is constant across PVT. An output driver is coupled to the predriver to receive the output swing. The output driver has an output for coupling an output signal to an external circuit.

Abstract: Apparatus, specifically a circuit (100, 200), for a highly accurate, low cost temperature sensor, particularly one using silicon thermometry and which can be implemented by an application specific integrated circuit, that also possesses a high degree of linearity and a wide dynamic range. The inventive circuit advantageously utilizes either a mixed-signal approach or a digital core and provides independent adjustment, through two point calibration, of slope and ambient output offset values, with a zero offset adjustment advantageously accomplished through use of a digital tear. Specifically, given the inherent linearity of silicon thermometry, zero offset and desired output voltage are set, independently of each other, at a first predefined ambient calibration temperature as effectively two separate offset values, while slope (span) is set at a second predefined calibration temperature (typically a full scale temperature) different from the first temperature.

Abstract: A pulse signal output circuit charges and discharges a capacitor in response to a clock signal and outputs a pulse signal having a pulse width determined by a time for charging and discharging the capacitor. A control signal generation circuit outputs a control signal in response to the pulse signal, where the control signal has a first voltage level determined by the pulse width. An output circuit has a first output transistor and a first regulating transistor connected in series between the first power supply node and the output terminal. The first output transistor is operated in response to a signal transferred from inside or outside a semiconductor device, and the first regulating transistor is operated in response to the control signal.

Abstract: A variable impedance circuit for use with a load, such as an IC-based active filter circuit, formed on a semiconductor substrate. The variable impedance circuit includes at least one non-linear element, such as a MOSFET. The variable impedance circuit also includes a means for suppressing at least a second order harmonic distortion term from the non-linear element.

Abstract: An improved integrated self-adjustable continuous time band pass filter based upon a Gm cell with Gm compensation and bipolar transistors for use in a low power processing system for processing bursted amplitude modulated signals performing impedance-related measurements across a load. The system may be used for estimating stroke volume using the output and/or estimating hemodynamic maximum sensor rate using the output. The improved Gm cell provides for stabilization of the transconductance by compensating for manufacturing process variation of the value of the linearizing resistance RG by varying the transconductance bias current using a feedback signal proportional to the resistance of a resistor which is a replicate of the linearizing resistor.

Abstract: There is provided a comparator circuit which does not output any erroneous comparison result even if the resistance value of a resistance component that exists in the input circuit for a voltage comparator is large.

Abstract: A signal isolator using magnetic coupling is disclosed. In contrast to the prior art non-isolated voltage summing circuits, the present invention utilizes current summing and magnetic coupling. In addition to providing ground and signal isolation the circuit of the present invention also provides a current-summing node which is always in a high impedance state, thereby allowing ancillary control mechanisms to be easily implemented in the circuit.

Abstract: Circuits and methods are provided that compensate for dynamic errors caused by voltage drops across a switch coupled in series with a capacitor in an electrical circuit such as a track-and-hold circuit. In such circuits, the capacitor should provide the same voltage as a signal coupled to the switch, but does not because of the switch voltage drop. The switch can be, for example, a MOSFET or more particularly a CMOS device. Dynamic errors are compensated for by measuring the voltage drop across the switch and then effectively adding the measured voltage drop to a voltage provided by the capacitor.

Abstract: A precision-controlled logarithmic amplifier having reduced interference parameters. In an embodiment, the invention comprises a logarithmic amplifier having an output signal providing a logarithmic representation of an input signal. A precision-control circuit is coupled to the logarithmic amplifier. The precision-control circuit produces a bias and a saturation current that act to reduce the effects of bias and saturation currents that are produced in the logarithmic amplifier and affect the output signal of the logarithmic amplifier.

Abstract: Method and system aspects for nulling output offset current in an amplifier are described. In an exemplary method aspect, the method includes determining at least one offset value with a power amplifier in at least one mode. The at least one offset value then utilized to identify an output offset current value in the power amplifier. An adjustment to an input signal to the power amplifier occurs until the output offset current value is substantially nulled to identify a power amplifier offset value.

Abstract: An output driver that includes a waveform detector and a driver unit. The waveform detector receives at least one data signal, detects for particular patterns of interest (e.g., a sequence of zeros or ones) within the received data signal, and provides one or more control signals indicative of the detected patterns of interest. The driver unit receives the data signal and provides at least one output signal in response thereto. The driver unit further receives the control signal(s) and adjusts one or more characteristics of the output signal based on the received control signal(s). Various characteristics of the output signal (e.g., slew rate, delay, drive strength, and others) can be adjusted to achieved the desired result (e.g., reduced amount of skew, ISI). The driver unit can be designed to include a pre-driver that receives the data signal and provides at least one pre-drive signal and a driver that receives the pre-drive signal and provides the output signal.

Abstract: A gain controller for a signal mixer in which consistent circuit gain is maintained by using transistors in the gain control and signal mixing stages with equal corresponding device dimensions and by using a differential gain control voltage with inverse and noninverse differential voltage phases which individually track variations in the dc bias currents used to power the gain control and signal mixing stages. This provides a gain factor which is independent of variations in circuit operation due to variations in circuit manufacturing processes and operating voltages and temperatures. Such a gain controller provides a self-compensating gain control signal which is based upon a variable gain control factor and tracks variations in circuit operation due to variations in circuit manufacturing processes and operating voltages and temperatures by tracking variations in the dc biasing used to power the gain control and signal mixing stages.

Abstract: A system and method that compensates for a pull-up resistor coupled to a buffer, when the pull-up resistor has an unknown resistance value. The system includes a buffer and a parameter detector. The buffer receives an input signal at a buffer input, and the buffer generates a buffered signal at a buffer output. The parameter detector measures a parameter at the buffer output when the buffer is in a high impedance output state, and the parameter detector generates a buffer control signal based upon the measured parameter. The buffer responds to the buffer control signal generated by the parameter detector.

Abstract: The level of a differential signal is determined such that a system, utilizing the level determined, can operate stably enough even if the intermediate potential of the signal changes. A comparator receives, as differential input, a differential signal to be transmitted. During a level determination interval, a sampler/level determiner samples the output of the comparator a number of times, and outputs a most frequently sampled value as the level of the differential signal.

Abstract: A programmable current source is provided for an H-switch to dampen overshoot resulting from a drop in voltage at a node during data transitions. The programmable current source is connected to both nodes of the H-switch on each side of the write head and is responsive to a voltage drop to below a threshold voltage at one node to injecting current into the one node during the period that the node voltage is below the threshold voltage. Preferably, a second programmable current source is connected to both nodes and is responsive to a voltage rise to above a second threshold voltage at the one of the nodes to sink current from the node to dampen undershoot.

Abstract: A leakage current correcting circuit for reducing a leakage current flowing into an output of a circuit in a high impedance state. The configuration includes a correcting unit having a current detecting circuit for detecting a leakage current and outputting a current equal to a detected leakage current, and a current supply circuit for receiving the output current from the current detecting circuit as an input and causing a current for offsetting the leakage current flowing into the output of the circuit in a high impedance state.

Abstract: A circuit (10) operates at relatively low values of the supply voltage, and includes a differential input circuit (16) which receives a differential input signal at first and second terminals (18, 21). A differential voltage derived by the input circuit from the differential input signal is present at third and fourth terminals (28, 31) and is amplified by a differential amplifier (12). A differential level adjuster (14) adjusts output voltages from the amplifier to suitable values for application to a matcher (15). The matcher (15) generates two currents that also flow within a differential compensator (17), and that match respective currents flowing in the amplifier. The differential compensator then provides a suitable current to each of the third and fourth terminals, such that the current flow between the first and third terminals, and between the second and fourth terminals, is substantially zero.

Abstract: A method of stabilizing the working point of a predistorter diode of a predistorter for an optical modulator as protection from temperature fluctuations, whereby the predistorter diode is supplied with a temperature-dependent voltage in order to adjust the working point, is characterized by the fact that a reference diode is thermally coupled with the predistorter diode so that the reference diode is supplied with a constant current, whereby it is not supplied with a signal distorted by the predistorter, and the predistorter diode is supplied with a voltage which is proportional to the reference diode. One advantage of the invention is that it is possible to achieve good temperature stability in an easy manner.

Abstract: A DC offset correction loop (200) utilizes a sign bit generator (204), binary search stage (206), and a digital-to-analog converter (208) in its feedback path to correct for DC offsets at the input of a gain stage (202). When a correction value is obtained, it is applied and held (524) to compensate for the DC offset. When a programming event occurs (534), such as detecting an increase in DC offset beyond a threshold, detecting a significant temperature change, or passage of time, a new DC offset correction cycle is initiated.

Abstract: To provide a buffer circuit that is able to achieve a reduction of the input current and a high input impedance by compensating the base current of a transistor, and to avoid a lowering of the input dynamic range by means of a current compensation circuit. By means of transistor P2, the base voltage of transistor Q2 is established in response to the signal of input node ND1 of the differential circuit, and the emitter voltage of transistor Q2 is set at virtually the same level as the reference voltage Vref. The collector current IC2 of transistor P2 is the same as the base current of transistor Q2, and is established with the amplification ratio of transistor Q2 as well as the current I2 of current source IS2.

Abstract: A method and system for calibrating analog integrated circuits. Initially, a single calibration circuit is formed integral with a group of analog integrated circuits. A control signal and a calibration signal are generated from the calibration circuit. Next, the control signal and the calibration signal are selectively coupled to an input of a particular analog integrated circuit among the group of analog integrated circuits. The particular analog integrated circuit is then selected for calibration via the control signal.

Abstract: A device (DC) is provided for compensating process and operating parameters variations in a CMOS integrated circuit. The device comprises means (CP, CT) for generating a first and a second compensation signals which depend on quality indexes of the fabrication process of the P and N transistors of the integrated circuit and on the operating temperature, and which are capable of compensating deviations of the controlled quantity from the desired value, due to the deviation of the quality indexes and temperature, respectively, from a typical value which would originate the desired value for the output parameter. The compensating device also can be implemented in the form of CMOS integrated circuit, preferably jointly with the device (OS) to be subjected to compensation (FIG. 1).

Abstract: A predistortion circuit includes a first splitter for splitting an input signal into primary and secondary electrical paths, a first combiner for combining a main signal on the primary electrical path and a predistorted signal on the second electrical path into a single signal for modulating a nonlinear device with predictable distortion characteristics, a distortion signal generator for receiving a branch signal from the first splitter and for producing first and second intermodulation products, a second splitter for receiving the first intermodulation products and for outputting two sets of the first intermodulation products, a third splitter for receiving the second intermodulation products and for outputting two sets of the second intermodulation products, an even-order signal processing unit for processing one set of the first intermodulation products and one set of the second intermodulation products to generate even-order intermodulation products, an odd-order signal processing unit for processing the

Abstract: A circuit arrangement for making isolated voltage and/or current measurements on a transmission line is characterized in that a shunt branch between the go conductor (+) and the return conductor (−) contains a series combination of a transformer (T), a first optically controllable, clocked switching element (OS1), and a first resistor (R1), and/or that the go conductor (+) or the return conductor (−) contains a second resistor (R2) shunted by a series combination of a transformer (T) and a second optically controllable, clocked switching element (OS2). The measured voltage and current values can thus be taken off linearly to the voltages and currents of the transmission lines using simple means and only few active components, particularly without analog-to-digital converters and power supplies tied to the potential of the transmission line.

Abstract: Log-linear variable gain amplifiers and amplifier control apparatus and methods providing temperature compensated log-linear gain characteristics with a wide range of control for a current steered variable gain amplifier. The invention provides the sum of scaled linear and exponential terms, proportional to absolute temperature and responsive to an input control voltage. The sum of these terms is applied to a current steered variable gain amplifier to provide the desired log-linear variable gain control. Various embodiments are disclosed.

Abstract: A sensor drive unit drives a sensor with an electric current. A differential current generation unit outputs a current which changes with a temperature. A compensation current output unit includes a plurality of current generation circuits. Each current generation circuit generates a current proportional to a current output from the differential current generation unit. Each current generation circuit has a transistor switch. Each transistor switch is controlled for its ON/OFF state according to input from terminals Ts0, Ts1, . . . The information input to the terminals Ts0, Ts1, . . . is stored in the memory. The compensation current output unit adds the output from the current generation circuits corresponding to the transistor switches in the ON state, and outputs the result as a sensitivity compensation current Its. The sensitivity compensation current Its is applied to the sensor.

Abstract: A simulation circuit has a simulation circuit path that simulates operation of the write current circuit path of a write current driver. A simulation transistor simulates operation of the driver transistor and a monitor circuit monitors current at the base of the simulation transistor to derive a compensation current based on variations in base current, including breakdown of the simulation transistor. The compensation current is combined with the driver current to derive the write driver current for the driver transistor of the write current driver. In another form, the simulation circuit path is a scaled-down electrical equivalency of the write current circuit path so that the simulation current is a scaled fraction of the write current and power requirements are reduced. In one form, current is added to the compensation current to accommodate unidirectional nature of current mirrors in the monitor circuit.

Abstract: A circuit for compensating for the threshold voltage nonuniformity and variations includes a transistor having a threshold voltage, a first switching element for switching between the gate and drain electrodes of the transistor, a first capacitor of which first electrode is connected to the contact between the gate electrode of the transistor and the first switching element so as to recognize and store the threshold voltage of the transistor, a second switching element for switching between the second electrode of the first capacitor and the source electrode of the transistor, and a third switching element for switching the input voltage to the second electrode of the first capacitor.

Abstract: A resistor circuit having its impedance controlled by a DC voltage is provided. The resistor circuit includes a first resistor with an expected impedance. The circuit also includes a second resistor connected in series with a DC voltage controlled transistor. The first resistor is placed in parallel with the series connection of the second resistor and the transistor. Adjustments to the impedance of the circuit occur by adding or removing the impedances of the second resistor and transistor by varying the DC voltage applied to the transistor. In doing so, the impedance of the resistor circuit will be controlled to match a desired impedance regardless of the variations caused by the manufacturing process, operating temperature or operating power supply voltage.

Abstract: A differential phase splitter circuit for producing opposite phase signals from an input AC signal is provided. A first and second transistor is provided. The source of these transistors are connected to a common first node. Further, these transistors act as a differential amplifier. The gate of the first transistor receives an input AC signal. The drain of the first transistor produces a first output AC signal. Similarly, the drain of the second transistor produces a second output AC signal that is 180 degrees out of phase with the first output AC signal. A source resistor is provided, connected in series to the common first node and ground. Lastly, an LCR feedback circuit is provided. This feedback circuit is connected between the drain of the first transistor and the gate of the second transistor. The LCR feedback circuit couples at least a fraction of the amplitude of the first output AC signal to the gate of the second transistor for amplitude balancing and phase balancing.

Abstract: In an optical recording/reproducing apparatus having a 3T-component compensating circuit, among the level-shifted radio frequency signals shifted during a reproduction of recorded data from an optical disc, the level of a 3T component is compensated for, so that error correction may be carried out by a digital signal processor. The optical recording/reproducing apparatus having a 3T-component compensating circuit for reproducing recorded data includes a peaking circuit for amplifying a 3T component from among RF signals outputted from a pickup. A compensating circuit compensates a level-shifted 3T component shifted during the amplification by the peaking circuit. A digital signal processor carries out error correction for the 3T component after the compensation by the compensating circuit.

Abstract: A filter circuit having a first variable resistive element determining the time constant of the filter circuit and a band pass filter having a second variable resistive element determining the time constant of the band pass filter. Each variable resistive element is connected to receive a time constant control signal which is obtained through a compensation circuit which receives an output voltage signal from a phase detection circuit for detecting a phase difference between the output signal of the band pass filter and a reference signal. The compensation circuit has a comparison circuit for comparing a first voltage generated by a third variable resistive element and a second voltage generated by a constant trimming resistor to generate the output voltage signal.

Abstract: A frequency-independent voltage divider includes a series arrangement of resistors connected between an input terminal and a reference terminal for receiving an input signal. An output terminal for supplying an output signal is coupled to a tap of the series arrangement. The influence of parasitic capacitances is eliminated by compensation capacitors.

Abstract: A VGA control circuit includes a differential control voltage generator having an input coupled to an external control voltage and having a pair of control voltage outputs, a transfer function compression region TFCR compensator coupled to the differential control voltage generator, and a TFCR detector coupled to the TFCR compensator and developing a compensator activation signal in response to the detection of a TFCR state in the transfer curve. A method for controlling a VGA circuit exhibiting transfer function logarithmic compression includes detecting when a VGA circuit is entering a logarithmic compression state, and applying an exponential compensation signal to the VGA circuit to cancel the compression state. A VGA system includes a VGA control system developing a plurality of differential control signals and a plurality of VGA stages coupled to the plurality of differential control signals.

Abstract: A charge sensitive amplifier with high common mode signal rejection includes an NPN bipolar junction transistor (BJT) and a P-channel metal oxide semiconductor field effect transistor (MOSFET) connected in a totem pole circuit configuration. The BJT base terminal receives a dc reference voltage, the MOSFET gate terminal receives the incoming data signal, the MOSFET drain terminal is grounded and the BJT collector terminal provides the output voltage signal and is biased by the power supply through a resistive circuit element. The MOSFET operates as a source follower amplifier with the transconductance of the BJT serving as the load at the source terminal, while the BJT operates as a common emitter amplifier with the transconductance of the MOSFET providing emitter degeneration. The signal gains of such source follower and common emitter amplifiers are substantially equal and of opposite polarities. Therefore, any common mode signal components due to common mode input signals present at the input terminals (i.

Abstract: A frequency conversion or synthesis circuit including a double balance differential active ring mixer with a current shared active radio frequency (RF) input balun, suitable for use in an RF receiver. The circuit is configured to be coupled to a bias circuit for providing a relatively constant current and a buffer circuit for receiving a signal from a local oscillator (LO) source and generating differential LO signals.

Abstract: An output buffer translates digital input signals which toggle between ground and V.sub.DDL to signals which toggle between ground and V.sub.DDH. The technology dielectric breakdown voltage limit is less than the magnitude of V.sub.DDH, such that use of a traditional output stage would subject transistors' dielectrics to voltages which exceed their dielectric breakdown limit, and would thus be damaged. Predrive circuits (40, 50) control output stage (70) transistors' (72, 78) gates, and voltage dropping circuits control output stage (70) transistors (74, 76). These control signals are generated specifically to maximize output stage transistor drive strengths, thereby minimizing output stage size. Output buffer functions when V.sub.DDL =V.sub.DDH, and its performance is V.sub.DDL independent. Temperature compensation is incorporated into the output buffer by deliberately offsetting temperature effects on output stage transistor drive strengths.

Abstract: A bias control circuit for controlling the bias current in a sense amplifier circuit. The bias control circuit maintains a substantially constant bias current when the V.sub.CC supply voltage decreases, thereby maintaining the operating speed of the sense amplifier circuit at a predetermined level. The bias control circuit also increases the bias current as the temperature of the sense amplifier circuit increases, thereby maintaining the operating speed of the sense amplifier circuit at the predetermined level. Furthermore, the bias circuit controls the logic low voltage provided by the sense amplifier circuit to be less than a predetermined threshold value, even as the V.sub.CC supply voltage increases.

Abstract: A current to voltage conversion circuit is formed of a differential amplifier circuit (1) with a negative input terminal connected to a light receiving element (3) and a register (4) which feeds back an output signal to the negative input terminal of the differential amplifier circuit (1) thereof. The variable gain amplifier circuit (5) amplifies the output voltage of the current to voltage conversion circuit to detect the bottom value of the output signal thereof. The comparator circuit (7) compares the bottom value with the reference value Vr1 so that current flowing through the resistor (4) can be adjusted according to the difference between the bottom value and the reference value Vr1. The offset of the output signal from the variable gain amplifier circuit (5) supplied through the output terminal OUT is thereby adjusted.

Abstract: A CMOS elementary cell of the first order for time-continuous analog filters with non-linearity compensation, is connected between a first supply voltage reference and a second voltage reference. The cell is of a type which comprises at least a first MOS transistor having its conduction terminals connected to the first supply voltage reference and to an output terminal, and having a control terminal connected to an input terminal of the first order CMOS elementary cell. The cell further comprises a second MOS transistor in diode configuration, and an equivalent capacitor, both connected to the output terminal of the first order CMOS elementary cell. The second, diode-connected MOS transistor and the equivalent capacitor act as a load for the first MOS transistor. The first MOS transistor operates as a drive transistor operatively tied to an input voltage signal being supplied to the input terminal of the first order CMOS elementary cell. A second order filter CMOS elementary cell is similarly connected.

Abstract: An integrated circuit comprising a power transistor and a circuit arrangement. The circuit arrangement is thermally coupled to the power transistor and operates in a temperature-dependent fashion. The integrated circuit includes a pnp or npn transistor with a temperature dependent resistor coupled between the base and emitter of the transistor. The off-state current of the transistor changes as a function of temperature and initiates a change in a base current of the power transistor.

Abstract: An electric circuit having a switchable feedback branch switchable between a first feedback state, in which the circuit arrangement has a frequency response that is stable with respect to an oscillation tendency, and a second feedback state, in which the circuit arrangement has a frequency response that is unstable with respect to an oscillation tendency. The circuit includes a switchable frequency response compensation circuit which during the first feedback state of the feedback branch can be controlled to an ineffective state and during the second feedback state of the feedback branch can be controlled to an effective state, and in the effective state causes such compensation of the frequency response of the circuit arrangement in the second feedback state that the circuit arrangement in the second feedback state remains stable with respect to an oscillation tendency.

Abstract: A level detector detects an input signal level. A rectifier (210) receives the input signal and provides a rectified signal. A prefilter (220) receives the rectified signal and attenuates high frequency components at frequencies near multiples of a decimation sample rate. The prefiltered signal is decimated (230) and low pass filtered by a lowpass filter (240) having a passband below the input frequency of the input signal. The level detector can be provided to control a variable gain stage circuit (935, 1010) which applies a gain to the input signal based on the level to form a dynamic range compressor or expander.

Abstract: A circuit and associated method for determining the offset bias of a comparator by first shorting together the inputs of the comparator to apply the same voltage signal at each of the inputs of the comparator. The voltage signal at one of the inputs is then offset a select amount by applying varying selected resistances from a variable resistor to the comparator. The variable resistor is controlled by a programmable controller that is responsive to an input clock signal. At each selected amount of offset applied to the input, the output is monitored to determine if the output of the comparator has flipped, or changed state. When the output flips, the corresponding resistance setting is used to compensate for the corresponding offset bias of the comparator.

Abstract: A multiplier and corresponding method are provided for amplifying a voltage difference between a first input voltage and a second input voltage, the multiplier being implemented with Bipolar Junction Transistor technology having high emitter resistance. The multiplier includes a first bipolar input transistor having high emitter resistance that receives the first input voltage and a second bipolar input transistor having high emitter resistance that receives the second input voltage. The multiplier also includes a first current source for generating a first current that flows through said first bipolar input transistor, a current mirror for producing a second current that is substantially equal to said first current and flows through said second bipolar input transistor.

Abstract: A hard disk drive system (10) has a read/write head (12) coupled to a read channel circuit (23) in an integrated circuit (13). The read channel circuit includes a bipolar transconductance-C filter (26) having at least one capacitor (27) with a capacitance value that may vary from an intended value. A temperature compensating voltage (VPTAT) is converted to a first current, a programming circuit (51) produces a second current (IPROG) as a function of the first current and a digital compensating input (54), and the second current is converted to a voltage (61) and used to control characteristics of the filter circuit. A trimming circuit (46) shunts away from the programming circuit a portion of the current generated by the voltage-to-current converter circuit, which portion is defined by a digital trim input (48).

Abstract: In order to correct offset differences among chips, in a multi-chip signal outputting apparatus that connects a plurality of chips each having signal sources and output terminal, output signals from the signal sources of the chips are output via a correct circuit in the output circuit stage of at least one of the chips.