Abstract: A method of driving a power transistor switch comprising: receiving a drive input signal; converting the drive input signal into a converted drive input signal; and providing the converted gate drive input signal to a control electrode of the switch to turn on the switch, the converted drive input signal having three regions with respect to time, each having a slope, a first region in time having a first slope up to a Miller Plateau of the switch; a second region in time having a second slope with a reduced slope compared with the first slope; and a third region having a third slope that is greater than the second slope, whereby the control electrode voltage rapidly reaches the Miller Plateau voltage, then more slowly reaches a threshold voltage of the switch and then, when the switch has substantially fully turned on, the control electrode voltage is rapidly increased. The switch delay time is also maintained substantially constant by adjusting the transistor control electrode precharge voltage.

Abstract: A switch includes a switching transistor, a switching resistor, connected between a control terminal of the switching transistor and a switching control terminal, and an accelerating element. The accelerating element includes a resistance smaller than a resistance of the switching resistor, the accelerating element being adapted to be connected in parallel to the switching resistor upon switching of the switching transistor until a voltage at the control terminal of the switching transistor has reached a predetermined value.

Abstract: An enhanced transistor gate drive is disclosed in which a pair of Kelvin sense leads measure the voltage potential across at the gate and source of the transistor. The difference in the voltage potential of the Kelvin sense lead from the gate and the Kelvin sense lead of the source is provided to a voltage controlled current source, which compares the output of the voltage differentiator to an oscillating voltage input. Changes to the voltage difference between the Kelvin sense connectors will result in more or less voltage being applied at the gate of the transistor, thereby parasitic inductance in the transistor from causing the device to switch on and off.

Abstract: In an electronic device according to the present invention, a source of the first signal-wire drive transistor is connected to a first power supply, a drain of the first signal-wire drive transistor is connected to a signal wire, and a control circuit controls a gate voltage so that a current flowing in the signal wire is amplified toward a voltage to which a potential of the signal wire transits during the potential transition in the signal wire and further controls the gate voltage so that a voltage value obtained after the potential transition in the signal wire is retained after the potential transition in the signal wire.

Abstract: According to an embodiment of the invention, there is provided a semiconductor device comprising: a semiconductor element having a first main electrode, a second main electrode and a control electrode, a current flowing between the first and second main electrodes being controlled by a control signal which is input between the control electrode and the second main electrode; and a capacitor formed by providing an insulating layer between the second main electrode and the control electrode of the semiconductor element.

Abstract: The first terminals of a plurality of resistor elements are connected to the intermediate connection points of a plurality of FETs connected in series, and a voltage, having a phase opposite to that of the voltage applied to the gate terminals of the plurality of FETs, is applied to the second terminals of the plurality of resistor elements. With this configuration, the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering. As a result, the power that can be handled can be increased. Furthermore, since the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering, the deterioration of the distortion characteristic and the isolation characteristic owing to the lowering of the potentials at the intermediate connection points of the plurality of field-effect transistors connected in series is prevented, and excellent high-frequency characteristics are obtained.

Abstract: A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM signals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a “symbol” at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol onto a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). The multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.

Abstract: The invention relates to a power circuit with a emitter-switched bipolar transistor (ESBT) (T2) and a MOS transistor (T3) connected downstream of the bipolar transistor. The bipolar transistor (T2) is controlled by a Mosfet transistor (T1). A zener diode (D1) which is disposed between the exit of the MOS transistor (T3) and the base of the bipolar transistor (T2) transmits the return current of the base collector diode of the bipolar transistor (T2) to the foot point of the ESBT (T2). Furthermore, a voltage source (U) is inserted between the collector of the bipolar transistor (T2) and the drain of the Mosfet transistor (T1).

Abstract: Methods and apparatus to reduce propagation delay of circuits are disclosed. A disclosed apparatus to reduce propagation delay of a circuit comprises a level shifter to selectively turn a first circuit on and off; a first switch to couple the first circuit to a second circuit when the first circuit is on, wherein the second circuit is to selectively receive a first current from the first circuit based on a signal the second circuit receives from the level shifter; and a second switch to couple the first circuit to a reference signal based on the first current, the second switch causing the first circuit to start to turn off.

Abstract: A semiconductor integrated circuit device may include a first internal circuit operating at a first voltage higher than a power supply voltage of the device, and a second internal circuit operating at a second voltage lower than the first voltage. An interface circuit may be provided to restrict a voltage transferred from the first internal circuit to the second internal circuit. The first internal circuit may include a metal oxide semiconductor (MOS) transistor having a relatively thick gate insulation layer, and the second internal circuit may have a MOS transistor having a relatively thin gate insulation layer. The interface circuit, by restricting voltage, may reduce an electric field applied to the gate insulation layer of the second MOS transistor in an effort to prevent a reduction in turn-on speed of the second MOS transistor.

Abstract: A dynamic NP-swappable body bias circuit includes a core circuit, a power switch and a body bias controller. The core circuit includes a body bias terminal. The power switch includes a body bias terminal, and connects the core circuit to an external voltage supply. The body bias controller is connected to the body bias terminals of the core circuit and the power switch so that the power switch and the core circuit are under the control of the body bias controller.

Abstract: The invention relates to a MOSFET circuit having reduced output voltage oscillations, in which a smaller CoolMOS transistor (T2) with a zener diode (Z1) connected upstream of its gate is located in parallel with a larger CoolMOS transistor (T1), so that, during a switch-off operation, after the larger transistor has been switched off, the smaller transistor (T2) carries a tail current on account of the zener voltage still present, which tail current attenuates output oscillations of the voltage.

Abstract: A gate drive apparatus including a constant-current-pulse gate drive circuit which creates a gate signal for a switching device as a constant-current output, a constant-voltage-pulse gate drive circuit which creates the gate signal as a constant-voltage output, and a decision/switch circuit which switches the operation of the constant-current-pulse gate drive circuit and the operation of the constant-voltage-pulse gate drive circuit. The variance of switching speeds attributed to the variances of threshold voltages and mirror voltages in a plurality of switching devices which are driven by the gate drive apparatus can be suppressed, and the variance of losses can be minimized.

Abstract: A control circuit for controlling an electronic circuit, which has a current path through a semiconductor switch and a line; when the semiconductor switch is switched, the inductance of the line and/or of a component in the current path producing an excess voltage between a first and a second current-carrying terminal of the semiconductor switch; the control circuit having a controllable current source for charging or discharging a charge-controlled gate of the semiconductor switch with the aid of a control current, as well as a control unit; the control unit controlling the current source in such a manner, that in the case of a switching operation, the terminal voltage across the current-carrying terminals of the semiconductor switch does not exceed a predefined setpoint terminal voltage.

Abstract: A drive circuit for an emitter switching configuration of transistors having a cascode connection of a power bipolar transistor and of a power MOS transistor control the saturation level of the configuration in applications which provide highly variable collector currents. The drive circuit includes a circuit operable to apply a varying voltage value to the control terminal of the bipolar transistor. A current/voltage converter senses a collector current flowing in the power bipolar transistor and controls conduction of a first transistor responsive thereto, the conduction of the first transistor controlling the conduction of a second transistor so as to vary the control terminal voltage in proportion to the sensed collector current of the power bipolar transistor.

Abstract: A device (1) for controlling inductive loads (111, 112), includes: several control stages (321, 322) having a bonding pad (331, 332) for an inductive load (321, 322), a receive input (301, 302) for a conduction activate signal, a switch (121, 122) including control and output electrodes; an enabling circuit (181, 182) measuring the voltage applied to the pad (331, 332) and generating an enabling signal; a conduction re-activate circuit (2) common to the control stages, limiting the voltage on the pad of the various stages to a common level and applying a conduction activate signal to the control electrode of a switch when the enabling signal is generated. The device can be used in particular to ensure an identical duration of supply to loads connected to the bonding pad.

Abstract: A method for controlling a vertical type MOSFET in a bridge circuit is provided to reduce diode power loss and improve a reverse recovery characteristic. The method includes controlling a forward voltage of a built-in diode of the vertical type MOSFET to be a first forward voltage by setting a gate voltage of the vertical MOSFET to a first gate voltage, so that the vertical type MOSFET is switched into a first off mode; and controlling the forward voltage of the built-in diode of the vertical type MOSFET to be a second forward voltage by setting the gate voltage of the vertical MOSFET to a second gate voltage, so that the vertical type MOSFET is switched into a second off mode.

Abstract: A semiconductor device is provided which has a driving circuit operable to drive a circuit that has a delay, the semiconductor device including: an auxiliary driving circuit operable to accelerate drive of the driving circuit, which receives a drive signal of the driving circuit as an input signal.

Abstract: In an electronic device according to the present invention, a source of the first signal-wire drive transistor is connected to a first power supply, a drain of the first signal-wire drive transistor is connected to a signal wire, and a control circuit controls a gate voltage so that a current flowing in the signal wire is amplified toward a voltage to which a potential of the signal wire transits during the potential transition in the signal wire and further controls the gate voltage so that a voltage value obtained after the potential transition in the signal wire is retained after the potential transition in the signal wire.

Abstract: Techniques are provided for trimming drive current in output drivers to compensate for process variations, model inaccuracies, and/or an off-target process. The actual output drive current is measured on the integrated circuit (IC) at wafer sort or during a final test. Based on the measured output drive current, the total transistor width that is required in the output driver to meet an I/O standard is calculated. A control block controls trimming transistors that are coupled in parallel with main output drive transistors. The control block adjusts the total width of the output drive transistors to bring the total width as close as possible to the desired width. Each I/O driver on a die can be adjusted individually based on its own drive current characteristics. All I/O drivers on a die can be adjusted by the same transistor width based on a single I/O measurement or on multiple I/O measurements.

Abstract: This document discusses, among other things, a circuit for selectively engaging an output section based on a received data signal. The output is driven to a high-impedance state in anticipation of a possible change in driving agent. An output section includes active transistor elements and a pre-driver.

Abstract: A drive circuit for a voltage driven type semiconductor element, includes: an electrical charge discharge unit that discharges electrical charge from a gate terminal of a voltage driven type semiconductor element when the voltage driven type semiconductor element is turned OFF; and an electrical discharge control unit that detects a time variation of a collector voltage of the voltage driven type semiconductor element, and controls electric discharge by the electrical charge discharge unit according to the time variation of the collector voltage which has been detected.

Abstract: Techniques and circuits for high speed switching of transistors are provided. These techniques and circuits switch an output device while varying the drive current to the output device in proportion to the output current through the output device. In addition, these techniques and circuits provide a switching circuit with substantially no quiescent currents. This is accomplished by sampling the output current conducted by the output device and using the sample as a signal to drive either the output device fully ON or to switch the output device fully OFF.

Abstract: The invention relates to a method and apparatus for controlling a high voltage generator during wafer burn-in. The method includes generating an enable signal for enabling a high voltage generator responsive to a mode signal, e.g., a wafer burn-in test mode. The method provides an external voltage to a semiconductor memory device through a pad responsive to the enable signal. The method varies a high voltage level being output from the high voltage generator in response to a reference voltage level.

Abstract: An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time interval to produce an output voltage. A sense amplifier samples and converts the output voltage of the integrator to a logic signal; and a latch stores the logic signal. In an alternate embodiment, a preamplifier conditions the input signal prior to being integrated. In another embodiment using multiple receivers, circuitry is added to the receiver to compensate for timing errors associated with the distribution of the timing signals. In yet another embodiment, the integrator is coupled to an equalization circuit that compensates for intersymbol interference. In another embodiment, another circuit compensates for accumulated voltage offset errors in the integrator.

Abstract: One end of each of five resistors is connected to each of the two ends and the respective intermediate points of a cascade of four depression-type FETs, while the other ends of the five resistors are provided with a predetermined voltage. This configuration fixes the source-drain potential of the four FETs. This fixing of the source-drain potential of the FETs permits stable application of a bias voltage for turning ON the FETs between the gate and the source each FET, so as to ensure the ON-OFF switching of the FETs.

Abstract: A drive circuit for driving an insulated gate transistor, the drive circuit including a driver that applies a gate voltage to the transistor, and a timing controller that controls a timing of the driver. The driver includes first and second drive circuits, the first and second drive circuits are electrically connected to the timing controller through first and second electrical connections, respectively, the first and second electrical connections control the first and second drive circuits, respectively, and the driver is capable of applying the gate voltage as a first gate voltage through the first drive circuit to the transistor, and as a second gate voltage through the second drive circuit to the transistor. The first gate voltage is lower than a threshold voltage of the transistor, the second gate voltage is a specified voltage for driving the transistor, and the timing controller controls the driver so that an application of the first gate voltage precedes an application of the second gate voltage.

Abstract: A timer circuit is arranged for reduced propagation delay and improved stability at low supply voltages. The timer circuit includes a capacitor circuit, a voltage offset circuit, an inverter circuit, and a current source circuit. The current source circuit is arranged to provide a current. Also, the capacitor circuit is arranged to provide a voltage ramp in response to the current. The voltage offset circuit is configured to provide a voltage offset. Further, the current source circuit, the capacitor circuit, and the voltage offset current are arranged to provide two voltage ramps that are offset from each other. Additionally, the inverter circuit includes a p-type transistor and an n-type transistor. The p-type transistor is configured to receive one of the two voltage ramps, and the n-type transistor is configured to receive the other of the two voltage ramps.

Abstract: A common voltage source IC device includes an operational amplifier, a push-pull circuit receiving an output signal from the operational amplifier and outputting a common voltage to a common voltage terminal; an inverting resistor connected to an inverting input of the operational amplifier; a feedback resistor connected to the common voltage terminal and the inverting input; a capacitor connected to the common voltage terminal and the inverting input; a first switching resistor connected to the inverting input and a first switching transistor, the first switching transistor connected to the common voltage terminal; a driving resistor receiving a drive voltage and connected to a non-inverting input of the operational amplifier; a variable resistor connected to the non-inverting input and a ground source; and a second switching resistor connected to the non-inverting input and a second switching transistor, the second switching transistor connected to the ground source.

Abstract: The present invention provides systems and methods that utilize inductive current steering to improve logic circuit performance by mitigating propagation delays associated with conventional transistor current steering. The system and methods employ RF transformers, wherein energizing primary windings induce current in associated secondary windings. In one aspect, a single clock bus is employed to induce the current, which is routed via respective ends of the secondary winding to emitter leads of the transistors. This current and voltage is 180 degrees out-of-phase such that one transistor is “on” while the other is “off,” which generates a differential output. In another aspect, a differential clock signal is employed to induce the current in secondary windings and associated transistor emitters.

Abstract: A semiconductor device includes a power device, and a driver which drives the power device. The driver includes a capacitor which is charged or discharged in correspondence to an external control signal, a first comparator which compares a voltage of the capacitor with a first reference voltage, and outputs a first signal based on a result of the comparison, a drive controller which outputs a drive signal in correspondence to the first signal to the power device; and a capacitor charger which detects the voltage of the capacitor, and supplies a current to the capacitor to charge the capacitor when the voltage of the capacitor is increasing within a given range.

Abstract: A method and device for switching power semi-conductors on and off, especially for IGBTs and MOS-FETs with inductive loads, and how they would be employed with torque-variable asynchronous machines, in ignition systems for spark ignition engines, in switch mode power supplies and power factor controllers. During a switching operation of the power semiconductor, a voltage across the semiconductor and the current through the semiconductor are measured, a time function of the voltage as well as a time function of the current are controlled, and the control of the voltage time function and the control of the current time function are effected essentially one after the other.

Abstract: An electronic switch applies ground potential to the backgate of a MOS pass transistor when the transistor is in the off state and the switch is open, during normal conditions. When the transistor is switched to the on state and the switch is closed, the gate voltage is applied to the backgate of the pass transistor in order to reduce the threshold voltage and the on resistance. During an undershoot condition, the gate of the pass transistor is connected to the negative voltage applied to an input port and this voltage is also connected to the backgate of the pass transistor to prevent the pass transistor from being biased on or the parasitic NPN transistor from being biased on and transmitting the input glitch to the output.

Abstract: A feedback enhanced triggering device for an electrostatic discharge protection circuit includes: a first inverter 30b having an output coupled to an input of a second inverter 30c, the second inverter 30c having an output coupled to a control node for a discharge device 31 such as a transistor; a high side feedback transistor 34 coupled to the output of the first inverter 30b, and having a control node coupled to the output of the second inverter 30c; and a low side feedback transistor 35 coupled to the output of the first inverter 30b, and having a control node coupled to the output of the second inverter 30c, wherein the feedback transistors 34 and 35 provide enhanced triggering for electrostatic discharge protection.

Abstract: A circuit arrangement for rapidly switching in particular inductive loads, comprises a load (11) being connectable to a supply voltage source (31) by means of a switching transistor(41) implemented as an N-channel MOS power transistor and connected as a high-side switch, a potential exceeding the voltage of the supply voltage source (31) being applicable to the gate electrode of the switching transistor (41) by controllable switching means, said switching means incorporating at least a first switching-means transistor (52) whose collector current can flow at least in part to the gate electrode of the switching transistor (41) during the conducting state. The first switching-means transistor (52) is connected as a current source. Furthermore, the first switching-means transistor (52) connected as a voltage source can be part of a current mirror circuit.

Abstract: The invention relates to a method and apparatus for controlling a high voltage generator during wafer burn-in. The method includes generating an enable signal for enabling a high voltage generator responsive to a mode signal, e.g., a wafer bum-in test mode. The method provides an external voltage to a semiconductor memory device through a pad responsive to the enable signal. The method varies a high voltage level being output from the high voltage generator in response to a reference voltage level.

Abstract: An invention is provided for a feed forward circuit that reduces delay through an inverting circuit. The feed forward circuit includes an inverter having an input and an output, and an inverting circuit having an input and an output. The input of the inverting circuit is coupled to the output of the inverter. A feed forward transistor having a gate coupled to the input of the inverter and a terminal coupled to the output of the inverting circuit also is included. In operation the feed forward transistor decreases the amount of time required for the output of the inverting circuit to change state. In sum, the invention reduces the delay when the inverting circuit transitions to a high state, without affecting the timing of the transition to a low state.

Abstract: A source and sink voltage regulator includes an output circuit, an amplifier circuit and a bias current control circuit. The output circuit is used to output a loading current under a stable output voltage and is further used to draw a reverse loading current while a loading voltage is greater than the output voltage. The amplifier circuit maintains the output voltage at a predetermined normal output voltage. The bias current control circuit keeps the transistors of the output circuit under a predetermined static bias current to accelerate the response speed of the voltage regulator, automatically maintaining a balance status while the output circuit is working.

Abstract: A semiconductor switching device or amplifier combined in parallel with one or more active devices defined as starter devices. A starter device is used to reduce the terminal voltage of a switching device or amplifier to a dc level below about 0.4 volts which will then allow the switching device to easily change between the on or conducting state and the off or non-conducting state. Three different starter devices are utilized. The first being a Bipolar Junction Transistor (BJT), the second a Metal Oxide Silicon Field Effect Transistor (MOSFET), and the third consisting of three normally off JFETs connected serially. Generally, a single starter device is coupled across the terminals of a semiconductor switching device or amplifier, but it is possible and sometimes advantageous to couple two or more starter devices in parallel. In a first case, a symmetrical, normally off or enhancement mode JFET is used as the switch or amplifier.

Abstract: An apparatus and method for receiving high-speed signals having a wide common-mode range with low input-to-output latency. In one embodiment, the receiver includes an integrator to accumulate charge in accordance with an input signal during an integration time interval to produce an output voltage. A sense amplifier samples and converts the output voltage of the integrator to a logic signal; and a latch stores the logic signal. In an alternate embodiment, a preamplifier conditions the input signal prior to being integrated. In another embodiment using multiple receivers, circuitry is added to the receiver to compensate for timing errors associated with the distribution of the timing signals. In yet another embodiment, the integrator is coupled to an equalization circuit that compensates for intersymbol interference. In another embodiment, another circuit compensates for accumulated voltage offset errors in the integrator.

Abstract: A high-speed current switch circuit of this invention has an n-type MOS transistor Q11 which switches and outputs a current, and a control circuit 11 which performs switching control of the MOS transistor Q11. In the control circuit 11, a source follower is formed by an N-type MOS transistor Q12 and a constant current source I2 which is a load on this transistor. A switch SW11 is connected to the MOS transistor Q12 to perform switching control of a current flowing through the MOS transistor Q12. The control circuit 11 includes a switch SW12 capable of grounding the gate of the MOS transistor 11. The source of the MOS transistor Q12 is connected to the gate of the MOS transistor Q11. Thus, even if a large current is caused to flow through the output transistor, the output transistor can be made to operate for switching at a high speed.

Abstract: An object of the present invention is to provide a simple and easily adjustable gate driving circuit for an active gate drive. As a configuration for this, a gate driving circuit includes a delay control signal creation unit configured to create a delay control signal having a certain delay time with respect to a control signal given from a superior control device, a reference signal creation unit configured to create a voltage reference signal by waveform-shaping of the delay control signal, a voltage detector configured to detect a voltage between electrodes of a voltage-driven type switching element and output a principal voltage detection signal, and a comparator configured to compare the principal voltage detection signal with the voltage reference signal and output a comparison result signal which controls a current source.

Abstract: An output buffer circuit has a main driver including a first pMOS transistor and a first nMOS transistor for driving a load, and a second pMOS transistor and a second nMOS transistor for driving the load in coaction with the first pMOS transistor and the first nMOS transistor, and a predriver including a third pMOS transistor and a third nMOS transistor for driving the first pMOS transistor, a fourth pMOS transistor and a fourth nMOS transistor for driving the first nMOS transistor, a fifth nMOS transistor for driving the first pMOS transistor in coaction with the third nMOS transistor, and a fifth pMOS transistor for driving the first nMOS transistor in coaction with the fourth pMOS transistor.

Abstract: A differential charge pump includes common mode circuitry for supplying a common mode voltage to a charging capacitor in the charge pump. The gate voltage of a reference transistor in a biasing branch of the differential charge pump is adjusted until the drain voltage of the reference transistor is equal to the common mode voltage when a specified bias current is flowing through the biasing branch. The same gate voltage and bias current are provided to a first transistor in a first common mode branch and a second transistor in a second common mode branch. The drains of the first transistor and the second transistor are connected to a first plate and a second plate, respectively, of the charging capacitor. In this manner, a desired common mode voltage is supplied to the charging capacitor.

Abstract: Techniques and circuits for high speed switching of transistors are provided. These techniques and circuits switch an output device while varying the drive current to the output device in proportion to the output current through the output device. In addition, these techniques and circuits provide a switching circuit with substantially no quiescent currents. This is accomplished by sampling the output current conducted by the output device and using the sample as a signal to drive either the output device fully ON or to switch the output device fully OFF.

Abstract: A high frequency switch module can handle transmit-receive signals of different frequency bands and realize excellent isolation. The high frequency switch module comprises a discriminating filter, a low-band high frequency switch, and a high-band frequency switch, wherein high-band 90-degree phase shifter that forms at least a high-band high frequency switch is configured by a high-pass filter, and a choke line is parallel-connected to the high-pass filter.

Abstract: A voltage supply circuit is capable of improving an operating speed of the circuit while lowering power consumption. An internal power supply voltage that is dropped and an internal ground voltage that is raised, from an external power supply, are generated and then supplied to an internal circuit. Therefore, when the circuit is driven, a swing width of a signal is reduced to reduce a dynamic power. When the internal circuit is driven at a low voltage, the back bias of a transistor is varied to lower the threshold voltage. Thus, the operating speed can be improved. Also, in a standby mode, the threshold voltage is increased to minimize the amount of current flowing at a sub-threshold voltage below the threshold voltage, thus reducing a static power.

Abstract: A high switching speed differential amplifier comprises a differential pair, a first and a second active loads, and a current source, in which the differential pair is composed of a pair of MOS transistors to receive a pair of differential signals from a first and a second inputs. The first active load is connected to an output of the first MOS transistor and includes a first and a second paths switched therebetween in response to the first input. The second active load is connected to an output of the second MOS transistor and includes a third and a fourth paths in response to the second input.

Abstract: A signal line driving circuit includes an inversion buffer, a pulse generator, a first signal buffer, and a second signal buffer. Here, the inversion buffer receives an input signal and includes an output terminal connected to the signal line to drive the signal line. The pulse generator receives the input signal to generate a pulse signal. The first signal buffer has a control terminal connected to an output terminal of the pulse generator and an input/output terminal connected to a node of the signal line. The first signal buffer reduces the rising transition time of a signal propagating on the signal line in response to a first control signal. The second signal buffer has a control terminal connected to the output terminal of the pulse generator and an input/output terminal connected to the node of the signal line. The second signal buffer reduces the falling transition time of a signal propagating on the signal line in response to a first control signal.

Abstract: A circuit arrangement for rapidly switching in particular inductive loads, comprises a load (11) being connectable to a supply voltage source (31) by means of a switching transistor(41) implemented as an N-channel MOS power transistor and connected as a high-side switch, a potential exceeding the voltage of the supply voltage source (31) being applicable to the gate electrode of the switching transistor (41) by controllable switching means, said switching means incorporating at least a first switching-means transistor (52) whose collector current can flow at least in part to the gate electrode of the switching transistor (41) during the conducting state. The first switching-means transistor (52) is connected as a current source. Furthermore, the first switching-means transistor (52) connected as a voltage source can be part of a current mirror circuit.