Abstract: In a gate circuit having a turn-off gate circuit composed of: OFF gate power source Eoff of which one terminal is connected to the emitter of semiconductor switching element 81, and switch SWoff that connects the other terminal of OFF gate power source Eoff and the gate of semiconductor switching element S1 via resistor Rg, the gate circuit is provided with second switch SWoff2 that connects the other terminal of OFF gate power source Eoff and the gate of semiconductor switching element S1. By closing second switch SWoff2 at the timing at which the turn-off operation is completed, it will connect to OFF gate power source Eoff without passing through a resistor.

Abstract: A fast high side switch for hard disk drive preamplifiers requires very fast turn on time, very low impedance when the switch is “on” and very high impedance when the switch is turned “off”. Each of the embodiments described provide a low-impedance path between the “Boost Voltage” and “Switch Out” terminals of the hard disk drive preamplifier, i.e., connecting a boost-voltage to the inductor, and as required in such a system, the proposed circuits provide a turn-on time that is much faster than the rise-time of the write current.

Abstract: A programmable current source is provided for an H-switch to dampen overshoot resulting from a drop in voltage at a node during data transitions. The programmable current source is connected to both nodes of the H-switch on each side of the write head and is responsive to a voltage drop to below a threshold voltage at one node to injecting current into the one node during the period that the node voltage is below the threshold voltage. Preferably, a second programmable current source is connected to both nodes and is responsive to a voltage rise to above a second threshold voltage at the one of the nodes to sink current from the node to dampen undershoot.

Abstract: An integrated circuit fast transmission switching device is provided which comprises a first input/output lead having a bus capacitance Cb; a second input/output lead having a bus capacitance Cb; a first bidirectional field-effect transistor having an internal resistance Ri and an internal capacitance Ci including a first input/output terminal and a second input/output terminal and a gate terminal, said first terminal being connected to said first lead and said second terminal being connected to said second lead, so as to pass bidirectional external data signals between said first and second leads when said transistor is turned on and so as to block the passage of external data signals between said first and second leads when said transistor is turned off; wherein Ri and Ci for the field-effect transistor are such that Ri(Ci+Cb) is less than 6.

Abstract: A fast high side switch for hard disk drive preamplifiers requires very fast turn on time, very low impedance when the switch is “on” and very high impedance when the switch is turned “off”. Each of the embodiments described provide a low-impedance path between the “Boost Voltage” and “Switch Out” terminals of the hard disk drive preamplifier, i.e., connecting a boost-voltage to the inductor, and as required in such a system, the proposed circuits provide a turn-on time that is much faster than the rise-time of the write current.

Abstract: An improved high speed PIN driver integrated circuit and architecture. The architecture of the PIN driver circuit does not rely on transistor clamping during normal operation in active mode, and does not require high reverse base-emitter breakdown voltage in inhibit mode or the active mode, which is in direct opposition to high speed performance at high PIN voltage excursions for CMOS, TTL, ECL level compatibility. In particular, the PIN driver circuit is always an active linear circuit and does always protects the reverse base-emitter voltage of any transistor and does not require wire-OR or clamp transistors. The architecture uses replica biasing to cancel the current of the PIN driver in the inhibit mode, which is a requirement for automatic test equipment where the leakage current produces at the PIN in the inhibit mode is not calibrated out.

Abstract: An analog switch is constructed using two bipolar junction transistors. The emitter of the first transistor is coupled to the emitter of the second transistor, and preferably the base of the first transistor is coupled to the base of the second transistor. The collectors of the transistors form the terminals of the analog switch. A current source is coupled to the bases of both transistors. The current source produces a drive current sufficient to forward bias the base-emitter junctions of both transistors. In this forward biased state, the collector of the first transistor and the collector of the second transistor are electrically coupled. A bias voltage source is coupled via a switch to the bases of both transistors. The bias voltage source produces a voltage sufficient to reverse bias the base-collector junctions of both transistors. In this reverse biased state, the electrical connection between the collector of the first transistor and the collector of the second transistor is broken.

Abstract: A driver circuit with pull down npn transistor drives an output voltage signal in response to an input voltage signal, without high-speed pnp transistors. A first npn transistor provides current to the output node when the output node is at a level equal to and less than the level of the input voltage signal less a base-to-emitter junction drop across the first npn transistor. A second npn transistor sinks current from the output node when the output node is at a level greater than the level of the input voltage signal less the base-to-emitter junction drop across the first npn transistor. The second npn transistor is controlled by a level of a control node. When the level of the output node is greater than the level of the input voltage signal less the base-to-emitter junction drop, the first npn transistor is turned off and the level of the control node is charged up by a current source.

Abstract: Between a reference voltage point and the emitter or the source of a transistor of which the collector or the drain is connected to a power source and to which an signal is input at its base or its gate, DC current passing means for causing a current to flow from the emitter or the source to the reference voltage point and a capacitor connected to the reference voltage point at one end and charged with a voltage generated in the DC current passing means are provided. A detection output for the signal is obtained from the emitter or the source of the transistor, or the other end of the capacitor.

Abstract: An electrostatic discharge (ESD) protection circuit includes two stages. A first stage is operatively coupled to a metal bonding pad. This first stage is an npn transistor having a low resistance fusible element which has a fast response time. A second stage is operatively coupled in series to the first stage. The second stage provides a high-resistance path to protect the npn transistor after the fusible element has fused to into a high resistance voltage path. In addition, a semiconductor device having internal circuitry protected by this two stage ESD protection circuit is provided. The ESD protection circuit is operatively coupled between the bonding pad which is located external to the semiconductor device and the internal circuitry.

Abstract: A buffer circuit including current sources and switches to connect and disconnect current sources to an output node. The switches are controlled by voltage detectors for comparing an input signal with a reference level. When the reference level is a predetermined value, the amplitude of an output signal swings up to V.sub.CC and swings down to V.sub.EE.

Abstract: An equivalent inductance circuit having a common input/output terminal comprises a bipolar transistor having a base grounded, an input/output terminal connected to an emitter of the bipolar transistor, and a feedback path comprising a capacitance having one end connected to a collector of the bipolar transistor and the other end connected to the emitter.

Abstract: An electrical circuit is disclosed that is capable of adjusting the peak-to-peak voltage of a binary signal symmetrically around a reference voltage, without human intervention and without introducing a transient response into the signal. One embodiment of the circuit comprises a current source, five resistors and two diodes, create an intelligent "voltage divider" that adjusts the peak-to-peak voltage of a binary signal symmetrically around a reference voltage.

Abstract: An improved current mode driver circuit uses N-type transistors in current mirrors to achieve higher speed operation at lower cost. A pair of matched low frequency P-type transistors provide a small amount of current to each side of the differential amplifier which comprise of only N-type transistors in a current mirror connection to amplify the current supplied thereto.

Abstract: A drive circuit for a voltage controlled power switching device includes a transformer, a full-wave rectifier bridge coupled to the transformer, first and second capacitors connected in series between nodes of the full-wave rectifier bridge and first and second controlled switches coupled between a control electrode of the power switching device and the first and second capacitors, respectively, wherein each controlled switch has a control electrode coupled to a secondary winding of the trans-former. Current is provided by the first capacitor to the control electrode of the power switching device through the first controlled switch at the beginning of a negative pulse appearing at the secondary winding of the transformer and charging current is provided to the first capacitor from the secondary winding of the transformer through the full-wave rectifier bridge after the beginning of the negative secondary pulse.

Abstract: A circuit arrangement for setting the operating point of at least one signal transistor (2) driven by alternating signals (1), with a current source (3) that is coupled to a supply potential (8) and to the control input of the signal transistor (2). A regulating transistor (4) has a load path coupled to a reference potential (9) and to the control input of the signal transistor (2). A resistor (5) is connected to the control input of the regulating transistor (4) and to the setting input of the signal transistor (2). A capacitor (6) is connected between the control input of the regulating transistor (4) and the reference potential (9).

Abstract: An object of the present invention is to provide a waveform shaping circuit for producing a trapezoidal pulse whose leading edge and trailing edge have the same slope and not inducing and radiating harmonic components under any conditions. A waveform shaping circuit comprises a common-emitter transistor 1, a first resistor 2 and second resistor 3 connected in series between a signal input terminal 9 and the base of the transistor 1, a third resistor and first capacitor 5 connected in parallel between a node a between the first resistor 2 and second resistor 2 and a ground, a feedback capacitor 6 connected between the collector of the transistor 1 and the node 1, and a collector load resistor 7 connected in series with the collector of the transistor 1. The waveform of a pulse to be applied to the signal input terminal 9 is reshaped to produce a trapezoidal pulse whose leading edge and trailing edge have a substantially equal slope, and then the trapezoidal pulse is led through a signal output terminal 10.

Abstract: A circuit for discharging of a photovoltaic power source has a first and a second terminal and the circuit comprises a discharge circuit which is connected between the first and second terminal of the power source which comprises a controllable current source which is controlled by a band gap reference.

Abstract: A control circuit for providing fast turn on of a PNP transistor in which a capacitor charging current is boosted and provided to the base of the PNP transistor. An embodiment of the invention provides a current amplifier in parallel with a current source for coupling to the base of the PNP transistor. The PNP transistor is connected to a positive voltage supply. A capacitor is also coupled to the positive voltage supply for delivering a charging current amplifier. In a further embodiment, an NPN transistor has its base coupled to the capacitor and its collector coupled to the base of the PNP transistor for providing the drive current boost. A diode may be coupled to the capacitor for passing a discharge current to the capacitor when the PNP transistor is off and to block the capacitor current when the PNP transistor is being switched on. A PNP drive transistor may be coupled between the collector of the NPN transistor and the base of the PNP transistor.

Abstract: A multi-stage analog bi-directional selector which has a low input impedance and cost. The multi-stage analog bi-directional selector includes a plurality of analog switches including first and second bi-polar transistors coupled together at first and second connection points, a primary channel coupled to the first connection points, a plurality of data channels coupled to the second connection points, and an address circuit which causes a single one of the analog switches to form a bi-directional analog data connection between a corresponding single one of the data channels and the primary channel.

Abstract: A base current controlling circuit for a power bipolar transistor comprising a first controlling device giving the base current only two states which are a "conduction" state and a "cut-off" state, and a second controlling device adjusting the condition of the power bipolar transistor to a predetermined preferable condition by controlling the base current value in response to a result of detection of a condition of the power bipolar transistor.

Abstract: An input signal processing circuit which prevents saturation of the input transistor. It has an input npn transistor QN1, a transistor QP1, the emitters of which are connected to the cathode terminal T.sub.CTD, and the collectors of which are connected to the collector of the input transistor. Transistors QP2,QP3 have emitters connected to the cathode terminal T.sub.CTD, and bases connected to the bases of transistor QP1. Transistor QN2 has its emitter connected to anode terminal T.sub.AND via resistor R5 and its collector connected to a common connecting point with the bases of transistors QP1,2. Transistor QN3 has its emitter connected to the anode terminal T.sub.AND, its base connected to the base of transistor QN2, and its collector connected to base and the collector of transistor QP2. A resistor R4 is connected between the collector of input transistor QN1 and the collector of third transistor QN2.

Abstract: Circuit arrangement of a driver using bipolar NMOS technology for generating fast high/low edges with a low bias current requirement.

Abstract: An impedance-generating device that provides a resistance and a reactance that are non-linear functions of a signal over a wide impedance range (VariablE Non-Linear Impedance Circuit Electronics, "VENICE"). An electronic component that has a gain characteristic with a unity gain frequency that is directly proportional to that signal can be configured to generate such an impedance. Such an electronic component configured to provide a negative effective resistance and a variable non-linear reactance can be used to implement a high frequency harmonic generator. This generator can provide high order harmonics which can be used in high frequency communications systems. The electronic component can also be configured to provide only a voltage-variable non-linear reactance which can be used to implement a reactive mixer to frequency shift a high frequency signal to an intermediate frequency signal, from mixing the high frequency signal with a local oscillator signal.

Abstract: An apparatus conducts current through a two terminal inductive load. The apparatus has a first conduction path, from a first supply voltage to one terminal of the inductive load and a second conduction path from the second terminal of the inductive load to a second supply voltage. The first conduction path includes a switching device that is controlled by a field-effect transistor having a gate terminal, second terminal, and third terminal. The gate terminal of the field-effect transistor is coupled to a reference voltage. The voltage at the second terminal of the field-effect transistor increases when the voltage at the field-effect transistor's third terminal increases.

Abstract: An electrostatic discharge (ESD) protection circuit includes two stages. A first stage is operatively coupled to a metal bonding pad. This first stage is an npn transistor having a low resistance fusible element which has a fast response time. A second stage is operatively coupled in series to the first stage. The second stage provides a high-resistance path to protect the npn transistor after the fusible element has fused to into a high resistance voltage path. In addition, a semiconductor device having internal circuitry protected by this two stage ESD protection circuit is provided. The ESD protection circuit is operatively coupled between the bonding pad which is located external to the semiconductor device and the internal circuitry.

Abstract: A integrated circuit, high impedance, current source/sink for wireless communications systems comprising one or more inverted bipolar junction transistors, and a method of ensuring high output impedance at RF frequencies. Mixers, differential amplifiers and transconductance amplifiers are disclosed as is the physical structure of bipolar transistors including heterojunction transistors.

Abstract: A write driver for writing write data to a magnetic disk. The write driver is provided with first and second pnp type input transistors whose bases are each supplied with a pair of complementary input signals, and first and second npn type output transistor in the form of an inverted Darlington arrangement. A first resistor element is provided between the emitter of a corresponding pnp type input transistor and the collector of a npn type output transistor, whereas a second resistor element is provided between the common collector of the first and second npn type output transistors and supply voltage. The collectors of the first and second pnp type transistor are supplied with clamp voltage. Third and fourth npn type output transistors each connected to the first and second npn type output transistors in series and subjected to complementary switching control are provided to form a bridge circuit and to drive an inductive head.

Abstract: A circuit to limit the maximum current passed from a power transistor (T'p) to a load (ZL) which is connected to an output terminal of the transistor. The circuit includes an error amplifier (1'), a driver circuit (P') for the transistor (T'p), and a current detector for detecting the current (IL) flowing through the load (ZL). The current detector is provided with at least first and second terminals, includes a circuit block (2) having an input terminal connected to the control terminal of (T'p) and an output terminal connected to the current generator internal to the amplifier (1'), one input (B') of the amplifier (1') being connected to the first terminal of (Rs) and the other input (A') connected to the second terminal of (Rs). The introduction of the circuit block lowers the open-loop system gain making it stable and producing a smooth reduction of any rise in the load current (IL).

Abstract: A circuit for limiting the output voltage from a power transistor connected in series with a resonant load between a voltage supply and a voltage reference, ground, is disclosed. The circuit includes a semiconductor junction element, in particular a diode of the SCR type, having an anode terminal connected to the voltage supply, a cathode terminal connected to a common circuit node between the power transistor and the resonant load, and a control terminal connected to a reference voltage of predetermined value. The reference voltage can be constructed by using a resistor connected in series with a diode across the voltage supply. The SCR diode is constructed using the parasitic PNP-NPN transistors which exist in the structure of the power transistor.

Abstract: A direct-current stabilizer includes an n-p-n transistor as a control transistor, and a control terminal to which a control voltage for driving the control transistor is applied. The value of the control voltage is determined so that a voltage applied to the base of the control transistor is not lower than the sum of the emitter voltage and the base-emitter voltage. With this structure, since the control transistor is driven by the control voltage of a value different from that of the input voltage, it is possible to limit the input voltage to a low value, allowing the difference between the input voltage and the output voltage to be minimized. Moreover, it is possible to switch the output of the direct-current stabilizer by connecting to the control terminal a transistor for switching the application of the control voltage to the control terminal between on and off. Furthermore, when the control terminal is connected to the input terminal, the control transistor is driven by the input voltage.

Abstract: A three-terminal insulated-gate power electronic device includes a first, bipolar power transistor and a second, insulated-gate transistor forming a darlington pair. The bipolar power transistor has a first electrode, a second electrode, and a control electrode respectively connected to a first electrode of the insulated-gate transistor and to a first external terminal of the three-terminal device, to a second external terminal of the three-terminal device, and to one second electrode of the insulated-gate transistor.

Abstract: A switch is described with a bipolar transistor as first switching element having a high breakdown voltage when operated in the reverse direction. This can be accomplished by a second switching element provided in the switch, a switching transistor, e.g. an MOS transistor, through which the base and the collector of the bipolar transistor are joined together, is activated in the reverse mode of the switch, i.e. when the bipolar transistor is in inverse mode, in such a way that the second switching element becomes conductive. The collector-emitter breakdown voltage of the bipolar transistor, i.e. its maximum permissible collector-emitter voltage, is thus brought closer to its higher base-emitter breakdown voltage.

Abstract: A current buffer circuit comprises an input terminal, an output terminal, a first transistor of a first conductivity type having a base connected to the input terminal and an emitter, and a second transistor of a second conductivity type having a base connected to the input terminal and an emitter. The buffer circuit further includes a third transistor of the second conductivity type having a base connected to the emitter of the first transistor, a collector connected to a first power supply terminal, and an emitter connected to the output terminal, a fourth transistor of the first conductivity type having a base connected to the emitter of the second transistor, a collector connected to a second power supply terminal, and an emitter connected to the output terminal, and a fifth transistor of the second conductivity type having a base connected to the collector of said fourth transistor, a collector connected to said output terminal, and an emitter connected to the second power supply terminal.

Abstract: A storage charge reduction circuit for reducing the storage charge of a first bipolar transistor. The circuit includes a second field effect transistor connectable between the base of the first bipolar transistor and ground for conducting a compensation current from the base of the first bipolar transistor to ground. A third bipolar transistor is connected in series with a first resistor for conducting a first current from a first voltage supply through the first resistor to ground. Current mirror circuitry sets the gate-source voltage of the second field effect transistor so that the compensation current is proportional to the first current. The first current and the compensation current increase when temperature increases. In a preferred embodiment, the storage charge reduction circuit is used in a transmission line driver. The driver includes an output bipolar transistor connectable between the transmission line and ground for conducting current from the transmission line to ground.

Abstract: A base current-control circuit comprises a detector for detecting a load current of the output transistor and for enabling the circuit to generate a detected current proportional to the load current. A base current-control voltage generator generates a voltage as a function of the detected current, and a switch generates ON/OFF signals. A base current generator utilizes the voltage to generate a base current in response to the ON/OFF signals generated by the switch to drive the output transistor.

Abstract: A biasing circuit (30) for an output vertical pnp transistor (10) formed in an integrated circuit and having an outer epitaxial region (20) includes a biasing vertical pnp transistor (33) and a comparator (38). Biasing circuit (30) is electrically connected to the integrated circuit voltage supply and the outer epitaxial region (20) of the output vertical pnp transistor (10) for electrically connecting the outer epitaxial region (20) to the voltage supply when the voltage at an output terminal (23) does not exceed the supply voltage and electrically disconnecting the outer epitaxial region (20) from the voltage supply when the voltage at the output terminal (23) exceeds the supply voltage, whereby improper operation of and damage to the integrated circuit upon the occurrence of an external fault condition is at least minimized.

Abstract: A semiconductor device, comprising a transistor, a constant voltage diode having a first end of a first conductivity type connected to an emitter of the transistor and a second end of a second conductivity type, a reverse current preventive diode having a first end of the first conductivity type connected to a collector of the transistor and a second end of the second conductivity type connected to the second end of the constant voltage diode, and a high speed diode reverse-bias connected between the transistor collector and the emitter of the transistor.

Abstract: A subcircuit for discharging a capacitor at a preselected rate incorporates a first transistor and a second transistor connected with the emitter of the first transistor providing current to the collector of the second transistor. The base of the first transistor is connected to a capacitor to be discharged at a preselected rate. The base current of the first transistor discharges the capacitor as a function of the base current provided to the second transistor. In order to provide a current of very small magnitude to the base of the second transistor, a plurality of lateral PNP transistors are connected in a plural stage arrangement in order to take advantage of the current dividing characteristic of lateral PNP transistors. A collector of one lateral PNP transistor is connected to the emitter of another so that each stage of the subcircuit reduces the output current by a very precise ratio.

Abstract: A control circuit for slowly turning off a solid-state power transistor, particularly for inductive loads, comprising means for limiting the load current flowing through the switch, and timing and control circuits to ensure, irrespective of the duration of a command pulse, slowed turn-off of the switch with a predetermined delay as to the time when the maximum load current value is reached, thereby keeping the power dissipation through the switch during the load current limiting phase within predetermined values and the turn-off overvoltage within predetermined levels.

Abstract: The invention relates to a voltage limiter for a transistor circuit with semiconductors (T.sub.20 and T.sub.21) in the arrangement of a plurality of successive amplifier stages, with a reference element (Zener diode Z.sub.20) and with at least one voltage divider arrangement (voltage divider R.sub.21 /R.sub.22). In accordance with the invention, the reference element (Zener diode Z.sub.20) is disposed downstream of the triggering circuit of the first stage or even closer at the output of the voltage limiter circuit for reducing the oscillation tendency.

Abstract: A high speed switching technology suitable for implementing field programmable gate arrays using current mode logic in the high speed data path, and CMOS steering logic outside the high speed data path to enable the high speed switching logic and to implement multiplexer, selector and crossbar switch functions. High speed emitter follower logic compatible with the high speed switching logic for level shifting, buffering, and providing more current sink or source capacity is also disclosed.

Abstract: An improved base drive circuit (10) having a level shifter (24) for providing bistable input signals to a pair of non-linear delays (30, 32). The non-linear delays (30, 32) provide gate control to a corresponding pair of field effect transistors (100, 106) through a corresponding pair of buffer components (88, 94). The non-linear delays (30, 32) provide delayed turn-on for each of the field effect transistors (100, 106) while an associated pair of transistors (72, 80) shunt the non-linear delays (30, 32) during turn-off of the associated field effect transistor (100, 106).

Abstract: A dynamic and low-loss circuit for driving a voltage-controlled semiconductor switch includes a transformer having primary and secondary windings. The primary winding is connected to a voltage for driving a voltage-controlled semiconductor switch and the secondary winding has a center tap connected to the emitter or source of the semiconductor switch and secondary winding halves with outer terminals. A bridge rectifier is connected to the secondary winding and has positive and negative direct-voltage terminals. A gate resistor is connected between the gate of the voltage-controlled semiconductor switch and the positive direct-voltage terminal. A series circuit of a first resistor and an auxiliary switch is connected between the direct-voltage terminals. A capacitor is connected between the center tap and the negative direct-voltage terminal. Two diodes have cathodes connected to the outer terminals.

Abstract: A power transistor switching circuit includes a switching transistor. A switching signal triggers a control device which, via a delay device and a control amplifier applies a first control signal to a control electrode of the switching transistor. A thyristor is coupled to the control electrode of the switching transistor. The thyristor has a first trigger gate and a second trigger gate. A measuring circuit generates a measuring signal proportional to the current in the switching transistor. A comparison device compares the measuring signal with a reference signal for applying a second trigger signal to the thyristor second trigger gate. The control device includes a further control amplifier having an input coupled to the switching signal and an output which applies a further control signal to the first trigger gate. The delay device delays the first control signal with respect to the further control signal.

Abstract: A circuit for limiting the output voltage from a power transistor connected in series with a resonant load between a voltage supply and a voltage reference, ground, is disclosed. The circuit includes a semiconductor junction element, in particular a diode of the SCR type, having an anode terminal connected to the voltage supply, a cathode terminal connected to a common circuit node between the power transistor and the resonant load, and a control terminal connected to a reference voltage of predetermined value. The reference voltage can be constructed by using a resistor connected in series with a diode across the voltage supply. The SCR diode is constructed using the parasitic PNP-NPN transistors which exist in the structure of the power transistor.