Differential Amplifier Patents (Class 327/52)
  • Publication number: 20130069693
    Abstract: A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.
    Type: Application
    Filed: November 15, 2012
    Publication date: March 21, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Semiconductor Energy Laboratory Co., Ltd.
  • Patent number: 8362807
    Abstract: A sense amplifier having compensation circuitry is described. The compensation circuitry includes at least one pair of compensation transistors. When compensation is desired, one or a combination of the bulk of the at least one pair of compensation transistors is provided with one or a combination of compensation voltages.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: January 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bharath Upputuri, Shreekanth Sampigethaya
  • Publication number: 20130021065
    Abstract: A power-up signal generation circuit includes a discharge driving unit configured to discharge a voltage of a power-up detection node in response to a voltage of an external power supply voltage, a charge driving unit configured to charge the voltage of the power-up detection node in response to a voltage of an internal power supply voltage, a power reset discharging unit configured to discharge a voltage of the power-up detection node while the semiconductor integrated circuit is reset, and an output unit configured to output a power-up signal in response to a voltage change of the power-up detection node.
    Type: Application
    Filed: November 8, 2011
    Publication date: January 24, 2013
    Inventor: Dong-Geum KANG
  • Patent number: 8354864
    Abstract: A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: January 15, 2013
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Sang Thanh Nguyen, Hung Quoc Nguyen
  • Patent number: 8339158
    Abstract: A dynamic high-speed comparative latch comprises a pre-amplifier unit for enlarging input differential signals, a regenerating latch unit for latching outputted differential signals from the pre-amplifier unit by using a positive feedback, specifically, converting the output of the pre-amplifier unit into a latched result at a first state of a clock cycle, and then retaining the latched result and simultaneously resetting relevant nodes at a second state opposite to the first state of the clock cycle, and a latch unit for outputting the effective outputted value of the regenerating latch unit when the regenerating latch unit being in a retaining state. The pre-amplifier unit is connected with the regenerating latch unit, and the regenerating latch unit is connected with the latch unit. The pre-amplifier unit comprises only one input clock signal. The present invention has a simple structure, and ensures the correctness of the output result of the latch.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: December 25, 2012
    Assignee: IPGoal Microelectronics (SiChuan) Co., Ltd.
    Inventors: Bin Li, Guosheng Wu
  • Patent number: 8330498
    Abstract: A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: December 11, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Kiyoshi Kato, Munehiro Azami
  • Publication number: 20120287740
    Abstract: Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell are disclosed. An example apparatus includes a differential amplifier configured to amplify a voltage difference between voltages applied to first and second amplifier input nodes to provide an output. The example apparatus further includes first and second capacitances coupled to the first and second amplifier input nodes. A switch block coupled to the first and second capacitances is configured to couple during a first phase a reference input node to the first and second capacitances and to the first amplifier input node. The switch block is further configured to couple during the first phase an output of the amplifier to the second amplifier input node to establish a compensation condition. During a second phase, the switch block couples its input nodes to the first and second capacitances.
    Type: Application
    Filed: May 12, 2011
    Publication date: November 15, 2012
    Applicant: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 8295296
    Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: October 23, 2012
    Assignee: Redmere Technology Ltd.
    Inventors: Aidan Gerard Keady, John Anthony Keane, Judith Ann Rea, Benjamin Griffin, John Martin Horan
  • Publication number: 20120262993
    Abstract: Methods of operating memory devices, generating reference currents in memory devices, and sensing data states of memory cells in a memory device are disclosed. One such method includes generating reference currents utilized in sense amplifier circuitry to manage leakage currents while performing a sense operation within a memory device. Another such method activates one of two serially coupled transistors along with activating and deactivating the second transistor serially coupled with the first transistor thereby regulating a current through both serially coupled transistors and establishing a particular reference current.
    Type: Application
    Filed: April 13, 2011
    Publication date: October 18, 2012
    Inventors: Violante Moschiano, Giovanni Santin, Tommaso Vali
  • Patent number: 8289054
    Abstract: A high voltage differential pair and op amp implemented in a low voltage semiconductor process. The high voltage differential pair expands the incoming common mode voltage of a differential pair to multiple times the normal operating voltage of the differential pair through the use of high voltage current sources, current sinks and stacks of transistors. The high voltage op amp includes a high voltage input stage and a high voltage common source amplifier to expand the output voltage range to multiple times the normal operating voltage of the op amp.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: October 16, 2012
    Assignee: Alfred E. Mann Foundation For Scientific Research
    Inventor: Edward K. F. Lee
  • Patent number: 8284624
    Abstract: A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: October 9, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Heung Kim, Yong-Ho Cho, Ji-Hoon Lim, Seong-Jin Jang, Tae-Yoon Lee
  • Publication number: 20120243359
    Abstract: A circuit comprises a first node, a second node, a sense amplifier, at least one first transistor, at least one second transistor, and one or a combination of a first control circuit and a second control circuit. The first control circuit is configured to generate a first control signal for at least one first gate of the at least one first transistor. The first control signal is capable of having a first voltage level lower than a first operational voltage. The second control circuit is configured to generate a second control signal for at least one second gate of the at least one second transistor. The second control signal is capable of having a second voltage level higher than a second operational voltage.
    Type: Application
    Filed: March 22, 2011
    Publication date: September 27, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Atul KATOCH
  • Patent number: 8269546
    Abstract: A modulator drive circuit provides a modulator drive signal, representative of a data waveform, to modulate an optical signal for transport across a network infrastructure. The modulator drive circuit includes a broadband Bias-T circuit insensitive to the frequency range of the data waveform. The Bias-T circuit provides for an adjustable bias level to maintain proper operation of a modulator used to modulate the optical signal. One or more modulator drive circuits may be provided on a single substrate.
    Type: Grant
    Filed: September 27, 2009
    Date of Patent: September 18, 2012
    Assignee: Infinera Corporation
    Inventor: Babak Behnia
  • Publication number: 20120224442
    Abstract: A circuit comprises a first driver, a second driver, and a remote sense amplifier. The first driver is configured to generate a first data signal on a first data line. The second driver is configured to generate a control signal on a control signal line. An RC delay of the control signal line is less than an RC delay of the first data line. The remote sense amplifier is configured to receive the first data signal, a second data signal on a second data line, and the control signal. The control signal line is configured for the control signal to enable the remote sense amplifier to amplify the voltage difference between the first data signal and the second data signal at inputs of the remote sense amplifier, if the voltage difference reaches a predetermined value.
    Type: Application
    Filed: March 4, 2011
    Publication date: September 6, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Sergiy ROMANOVSKYY
  • Patent number: 8254402
    Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves. Methods are provided for deskewing, equalizing, and boosting the differential signals in the embedded circuits that are mounted on a PCB.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: August 28, 2012
    Assignee: Remere Technology Ltd.
    Inventors: Aidan Gerard Keady, John Anthony Keane, Judith Ann Rea, Benjamin Griffin, John Martin Horan
  • Patent number: 8232828
    Abstract: There is provided an analog circuit having improved response time. An analog circuit having improved response time may include: a low level limiter converting a signal having a lower level than a predetermined reference level into a signal having a predetermined non-low level higher than the predetermined reference level; and an analog circuit section amplifying the signal from the low level limiter into a signal having a predetermined level.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: July 31, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Shinichi Iizuka, Sang Hee Kim, Jun Kyung Na, Sang Hoon Ha
  • Publication number: 20120176523
    Abstract: A sense amplifier having a negative capacitance circuit receives differential input signals via a pair of data lines, and senses and amplifies a voltage difference between differential output signals corresponding to the differential input signals as loaded by the negative capacitance circuit using a differential-to-single-ended amplifier to generate a corresponding data output signal.
    Type: Application
    Filed: January 9, 2012
    Publication date: July 12, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwi Sung Yoo, Min Ho Kwon, Wun-Ki Jung, Jin Ho Seo, Dong Hun Lee, Won Ho Choi, Jae Hong Kim
  • Publication number: 20120169378
    Abstract: A first sensing circuit has input terminals coupled to a true differential signal line and a complementary differential signal line. A second sensing circuit also has input terminals coupled to said true signal and said complementary signal. Each sensing circuit has a true signal sensing path and a complementary signal sensing path. The first sensing circuit has an imbalance that is biased towards the complementary signal sensing path, while the second sensing circuit has an imbalance that is biased towards the true signal sensing path. Outputs from the first and second sensing circuits are processed by a logic circuit producing an output signal that is indicative of whether there a sufficient differential signal for sensing has been developed between the true differential signal line and the complementary differential signal line.
    Type: Application
    Filed: May 31, 2011
    Publication date: July 5, 2012
    Applicant: STMICROELECTRONICS PVT. LTD.
    Inventors: Prashant Dubey, Navneet Gupta, Shailesh Kumar Pathak, Kaushik Saha, Gagandeep Singh Sachdev
  • Patent number: 8212589
    Abstract: A signal transfer circuit according to the present invention includes a differential signal generation unit that generates a differential signal according to a voltage difference between two input signals, a voltage difference detection unit that detects a voltage difference between the two input signals input to the differential signal generation unit, and a signal output unit that outputs a signal including a predetermined value if the voltage difference is not detected by the voltage difference detection unit, and outputs the differential signal generated by the differential signal generation unit if the voltage difference is detected by the voltage detection unit.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: July 3, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Akihiro Hiramatsu, Yutaka Saeki
  • Patent number: 8199858
    Abstract: The present invention provides an OOB detection circuit capable of making accurate signal determination even in the case where a characteristic fluctuation occurs in an analog circuit, thereby preventing deterioration in the yield of a product. To an amplitude determining circuit, a characteristic adjustment register for changing setting of an amplitude threshold adjustment mechanism for distinguishing a burst and a squelch from each other provided for the amplitude determining circuit is coupled. The characteristic adjustment register is controlled by a self determination circuit. An output of the amplitude determination circuit is supplied to a time determining circuit and also to the self determination circuit. On the basis of the output of the amplitude determining circuit, the self determination circuit controls the characteristic adjustment register.
    Type: Grant
    Filed: December 6, 2008
    Date of Patent: June 12, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuaki Kurooka, Kenichi Shimizu
  • Patent number: 8193835
    Abstract: An example of a circuit for generating high-voltage switching at an output terminal of the circuit includes a pair of n-type metal oxide semiconductor (NMOS) transistors responsive to input signals to generate a first voltage signal in a preset mode. The circuit also includes a predefined number of n-type cascode stages coupled between the output terminal and the pair of NMOS transistors to enable propagation of the first voltage signal to the output terminal. Further, the circuit includes a predefined number of p-type cascode stages coupled to the output terminal to enable propagation of the first voltage signal to an input voltage supply to the circuit. Furthermore, the circuit includes a first pair of cross-coupled p-type metal oxide semiconductor (PMOS) transistors coupled to the input voltage supply. The circuit includes a pair of PMOS transistors, coupled between the first pair of cross-coupled PMOS transistors and the p-type cascode stage.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: June 5, 2012
    Assignee: Synopsys Inc.
    Inventors: Yanyi Liu Wong, Rebecca Shiu Yun Cheng
  • Patent number: 8171353
    Abstract: Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of read data received through the read data lanes. The controller then adjusts the manner in which the read data received through the read data lanes during normal operation are divided into frames. The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: May 1, 2012
    Assignee: Micron Technology, Inc.
    Inventor: A. Kent Porterfield
  • Patent number: 8164362
    Abstract: A sense amplifier having a sampling circuit to sample the amplifier input signal; a reference node storing a reference signal corresponding to the input signal; and a timing circuit activating the sampling circuit for a predetermined interval, and admitting the reference signal to the reference node. The sense amplifier also can include a pump capacitor substantially maintaining a value of the reference signal; and a gain circuit coupled with the reference node and disposed to adaptively adjust gain of an output signal produced by the sense amplifier. The sense amplifier can be a single-ended sense amplifier.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: April 24, 2012
    Assignee: Broadcom Corporation
    Inventors: Morteza Cyrus Afghahi, Esin Terzioglu
  • Patent number: 8149018
    Abstract: A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: April 3, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Kiyoshi Kato, Munehiro Azami
  • Patent number: 8125268
    Abstract: An input buffer receiver circuit for electronic devices (e.g., memory chips) to receive and process reduced-swing and high bandwidth inputs to obtain “buffered” output signals therefrom with symmetrical rising and falling delays, and without additional current dissipation over previous receiver circuits, is disclosed. The receiver circuit may include two stages of differential amplifier pairs (i.e., a total of 4 separated differential amplifiers). The differential amplifiers in the first stage convert the single-ended input signal to a full-differential signal, which is then converted back to a single-ended output signal by the differential amplifier pair in the second stage. The output of a P-diff first stage may be connected to the input of an N-diff second stage and the output of an N-diff first stage may be connected to the input of a P-diff second stage thereby creating a “cross” coupled structure.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: February 28, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Dong Pan, Timothy B. Cowles
  • Publication number: 20120044774
    Abstract: A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.
    Type: Application
    Filed: October 31, 2011
    Publication date: February 23, 2012
    Applicant: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Sang Thanh Nguyen, Hung Quoc Nguyen
  • Patent number: 8120408
    Abstract: A delay cell circuit (200) is disclosed. The delay cell circuit may include a differential stage (202) and a cross-coupled stage (204). The cross-coupled stage can include resistors (210-0 and 210-1) the function to reduce a gain. The differential stage (202) and cross-coupled stage (204) can include variable currents sources (208 and 212), respectively. As frequency of operation increases, variable current source (208) provides a larger current to the differential stage (202) and variable current source (212) provides a smaller current to cross-coupled stage (204). Delay cell circuit (200) may be used in a voltage controlled oscillator (VCO). By including gain attenuating devices such as resistors (210-0 and 210-1), a frequency tuning range of the VCO may be increased.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: February 21, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Mohandas Palatholmana Sivadasan, Gajendar Rohilla
  • Publication number: 20120020162
    Abstract: An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIGS. 7 and 8) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch (806) coupled to receive a first program voltage (PGMDATA) and a first select signal (ROWSEL). A voltage divider (804) is coupled in series with the switch. A sense transistor (152) has a sense control terminal (156) and a current path coupled between an output terminal (108) and a reference terminal (110). A first capacitor (154) has a first terminal coupled to the switch and a second terminal coupled to the sense control terminal. An access transistor (716) has a control terminal coupled to receive a read signal (721), and a current path coupled between the output terminal and a bit line (718).
    Type: Application
    Filed: July 20, 2010
    Publication date: January 26, 2012
    Inventors: Harvey J. Stiegler, Allan T. Mitchell, Robert N. Rountree
  • Publication number: 20120020176
    Abstract: Some embodiments regard a circuit comprising: a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left drain, a third left gate, and a third left source; a first right transistor having a first right drain, a first right gate, and a first right source; a second right transistor having a second right drain, a second right gate, and a second right source; a third right transistor having a third right drain, a third right gate, and a third right source; a left node electrically coupling the first left drain, the second left drain, the second left gate, the third right gate, and the third left drain; and a right node electrically coupling the first right drain, the second right drain, the second right gate, the third left gate, and the third right drain.
    Type: Application
    Filed: July 20, 2010
    Publication date: January 26, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Ji Lu, Hung-Jen Liao, Cheng Hung Lee, Derek C. Tao, Annie-Li-Keow Lum, Hong-Chen Cheng
  • Patent number: 8102156
    Abstract: A differential amplifier circuit comprises a first input transistor including a control electrode serving as a non-inversion input terminal and a second input transistor including a control electrode serving as an inversion input terminal. These first and second input transistors constitute a difference pair. A bias current generation circuit section is provided to generate a bias current flowing to the first and second input transistors. An offset adjustment circuit section is provided to adjust an input offset voltage appearing at these input terminals. The offset adjustment circuit section has an adjustment resistance formed from a first variable resistance inserted into a first current route connecting to the first input transistor and a second variable resistance inserted into a second current route connecting to the second input transistor. The bias current generation circuit section changes the bias current in accordance with a change in a value of the adjustment resistance.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: January 24, 2012
    Assignee: Ricoh Company, Ltd.
    Inventor: Ippei Nodo
  • Patent number: 8085067
    Abstract: A differential-to-single ended converter circuit can include a latching circuit having first and second latch field effect transistors (FETs) with drains and gates cross-coupled between a first latch node and a second latch node. The source-drain paths of the first and second latch FETs are coupled to a first reference potential node via separate current paths. A sense circuit can include a first sense FET having a source-drain path coupled between the first sense node and the first reference potential node, and a gate coupled to a first input node. A second sense FET has a source-drain path coupled between the second sense node and the first reference potential node, and a gate coupled to a second input node.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: December 27, 2011
    Assignee: Cypress Semiconductor Corporation
    Inventor: Jonathon Stiff
  • Publication number: 20110310687
    Abstract: A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.
    Type: Application
    Filed: June 21, 2010
    Publication date: December 22, 2011
    Applicant: Micron Technology, Inc.
    Inventors: ONEGYUN NA, Jongtae Kwak, Seong-Hoon Lee, Hoon Choi
  • Patent number: 8081015
    Abstract: A differential amplifier includes an amplification unit and a feedback unit. The amplification unit amplifies a voltage difference between a first input signal and a second input signal and outputs a first output signal and a second output signal. The feedback unit amplifies a voltage difference between a first feedback signal based on the first output signal and a second feedback signal based on the second output signal.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: December 20, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung-Joo Ha
  • Patent number: 8081705
    Abstract: Digital video data is transmitted from a video source (61) to a video sink (62) as a group of three multilevel symbols (611, 612, and 613) per pixel color with each associated symbol being sent at a rate of three times the pixel clock (601). When eleven levels are used per symbol (611) and undesirable symbol groups having excess DC residual or minimal energy are eliminated, and a built-in-test symbol group is added for pixel alignment; there results a one-to-one correspondence between the remaining symbol groups available and the two-hundred and sixty possible states that are used in the TMDS physical layer that is in widespread commercial use.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: December 20, 2011
    Assignee: Crestron Electronics Inc.
    Inventor: Philip L. Kirkpatrick
  • Patent number: 8081016
    Abstract: An input buffer includes a driving signal generation unit, a comparison signal generation unit, and a driving unit. The driving signal generation unit is configured to generate first and second driving signals which are selectively enabled in response to a control signal generated depending on a level of an input signal. The comparison signal generation unit is configured to compare the level of the input signal with the level of a reference voltage and generate a comparison signal. The driving unit is configured to buffer the comparison signal and drive an output signal with a drivability determined by the first and second driving signals.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: December 20, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Eun Ryeong Lee
  • Publication number: 20110304358
    Abstract: Sense amplifiers and methods for precharging are disclosed, including a sense amplifier having a pair of cross-coupled complementary transistor inverters, and a pair of transistors, each one of the pair of transistors coupled to a respective one of the complementary transistor inverters and a voltage. The sense amplifier further includes a capacitance coupled between the pair of transistors. One method for precharging includes coupling input nodes of the sense amplifier to a precharge voltage, coupling the input nodes of the sense amplifier together, and coupling a resistance to each transistor of a cross-coupled pair to set a voltage threshold (VT) mismatch compensation voltage for each transistor. The voltage difference between the VT mismatch compensation voltage of each transistor is stored.
    Type: Application
    Filed: June 14, 2010
    Publication date: December 15, 2011
    Applicant: Micron Technology, Inc.
    Inventors: J. Wayne Thompson, Howard C. Kirsch, Charles L. Ingalls
  • Publication number: 20110298496
    Abstract: A sense amplifier for use in a memory array having a plurality of memory cells is provided. The sense amplifier provides low power dissipation, rapid sensing and high yield sensing operation. The inputs to the sense amplifier are the differential bitlines of an SRAM column, which are coupled to the sense amplifier via the sources of two PMOS transistors. A CMOS latching element comprised of two NMOS transistors and the aforementioned PMOS transistors act to amplify any difference between the differential bitline voltages and resolve the output nodes of the sense amplifier to a full swing value. The latching element is gated with two additional PMOS transistors which act to block the latching operation until the sense amplifier is enabled. One or more equalization transistors ensure the latch remains in the metastable state until it is enabled. Once the latch has resolved it consumes no DC power, aside from leakage.
    Type: Application
    Filed: June 2, 2011
    Publication date: December 8, 2011
    Inventors: David Rennie, Manoj Sachdev
  • Patent number: 8064508
    Abstract: An adjustable equalizer that includes a first branch including a low pass filter (LPF) and having a variable gain (?), and a second branch including a high pass filter (HPF) and having another variable gain (?). Outputs of the branches in response to an input signal are summed to produce an equalized output. The equalizer can be implemented using CMOS technology so that the gain parameters ? and ? are independently adjustable and the equalizer is capable of equalizing an input indicative of data having a maximum data rate of at least 1 Gb/s. Typically, the inventive equalizer is embodied in a receiver for use in equalizing a signal, indicative of video or other data, that has propagated over a serial link to the receiver.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: November 22, 2011
    Assignee: Silicon Image, Inc.
    Inventor: Dongyun Lee
  • Patent number: 8063696
    Abstract: An output circuit (12) converts a pair of current signals supplied to a pair of common nodes (NCa and NCb) into a pair of voltage signals (VOa and VOb). In each of input buffer circuits (11, 11, . . . ), a constant current generation section (101) generates, in an output mode, a pair of constant currents in a pair of current paths going from a pair of intermediate nodes (NMa and NMb) to a reference node (VDD1), and stops the generation of the pair of constant currents in a cutoff mode. A voltage-to-current conversion section (102) generates, in the output mode, a pair of input currents corresponding to a pair of input signals (Sa and Sb) in a pair of current paths going from the pair of intermediate nodes (NMa and NMb) to a reference node (GND) to thereby generate a pair of current signals (Ia and Ib) in a pair of current paths going from the pair of intermediate nodes (NMa and NMb) to the pair of common nodes (NCa and NCb), and stops the generation of the pair of input currents in the cutoff mode.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: November 22, 2011
    Assignee: Panasonic Corporation
    Inventor: Akinori Shinmyo
  • Patent number: 8058908
    Abstract: A level detector, a voltage generator, and a semiconductor device are provided. The voltage generator includes a level detector that senses the level of an output voltage to output a sensing signal and a voltage generating unit that generates the output voltage in response to the sensing signal. The level detector may include a first reference voltage generator configured to divide a first voltage and to output a first reference voltage, a second reference voltage generator configured to divide a second voltage in response to the output voltage and to output a second reference voltage that varies as a function of temperature, and a differential amplifier configured to receive the first and second reference voltages and to output a sensing signal in response to a sensing voltage generated by amplifying a difference between the first and second reference voltages.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: November 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Whi-Young Bae, Byung-Chul Kim
  • Patent number: 8049535
    Abstract: A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: November 1, 2011
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Sang Thanh Nguyen, Hung Quoc Nguyen
  • Patent number: 8049534
    Abstract: In bipolar CMOS or BiCMOS process technologies, drivers (such as mixed mode or hybrid mode drivers) using both bipolar and CMOS transistors (i.e., field effect transistors or FETs) may have undesirable properties, such as reduced speed, ringing, latch-up, or lower electrostatic discharge (ESD) performance. Here, a mixed or hybrid mode driver is provided that employs a current steering circuit (instead of voltages driven differential pair(s) as is done with conventional drivers) to generate pull-down currents that precisely match the voltages in the pull-up portions of driver. It increases the speed and produces smaller output common-mode voltage fluctuation over conventional drivers. Thus, the driver provided here can be produced in BiCMOS process technologies without the undesirable effects of conventional drivers.
    Type: Grant
    Filed: February 15, 2010
    Date of Patent: November 1, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Yaqi Hu, Yanli Fan, Mark W. Morgan
  • Patent number: 8031547
    Abstract: A differential sense amplifier can perform data sensing using a very low supply voltage.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: October 4, 2011
    Assignee: Atmel Corporation
    Inventors: Jimmy Fort, Renaud Dura, Thierry Soude
  • Publication number: 20110235450
    Abstract: Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop gain of the current mode sense amplifier, the load circuit including at least passive resistance.
    Type: Application
    Filed: March 26, 2010
    Publication date: September 29, 2011
    Applicant: Micron Technology, Inc.
    Inventors: Seong-Hoon Lee, Onegyun Na, Jongtae Kwak
  • Patent number: 8018253
    Abstract: A sense amplifier circuit is provided with a first transistor arrangement comprising a first n-type field effect transistor (NFET) having a respective body node, and a second transistor arrangement comprising a second NFET having a respective body node. The second transistor arrangement is electrically coupled to the first transistor arrangement, and the body node of the first NFET is electrically coupled to the body node of the second NFET. The sense amplifier circuit also includes or cooperates with a voltage condition selector that is electrically coupled to the body node of the first NFET and to the body node of the second NFET. The voltage condition selector is configured to assert one of a plurality of voltage conditions at the body node of the first NFET and at the body node of the second NFET.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: September 13, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Russell Schreiber, Keith Kasprak
  • Publication number: 20110205822
    Abstract: A bitline sense amplifier includes a pre-sensing unit and an amplification unit. The pre-sensing unit is connected to a first bitline and a second bitline, and is configured to perform a pre-sensing operation by controlling a voltage level of the second bitline based on at least one pre-sensing voltage and variation of a voltage level of the first bitline. The amplification unit is configured to perform a main amplification operation by amplifying a pre-sensed voltage difference based on a first voltage signal and a second voltage signal. The pre-sensed voltage difference indicates a difference between the voltage level of the first bitline and the voltage level of the second bitline after the pre-sensing operation.
    Type: Application
    Filed: January 14, 2011
    Publication date: August 25, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joung-Yeal Kim, Seong-Jin Jang, Jin-Seok Kwak
  • Publication number: 20110204923
    Abstract: Methods, systems, and devices are described for providing voltage comparison adapted to operate at high-speeds and over a relatively large range of supply voltages.
    Type: Application
    Filed: January 24, 2011
    Publication date: August 25, 2011
    Applicant: ASIC ADVANTAGE INC.
    Inventor: Sam Seiichiro Ochi
  • Patent number: 8004119
    Abstract: A new multi-function shunt active filter has been successfully implemented. The proposed decoupler and cascade controller provide a simple solution to power factor correction, reduction of harmonics loads and load balancing. The mathematical burden of resolving the load current to fundamental and harmonics is not required. The decoupler and controller can easily be implemented using low-cost analogue devices.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: August 23, 2011
    Assignee: The Hong Kong Polytechnic University
    Inventors: Kai Ming Tsang, Wai Lok Chan
  • Patent number: 8000672
    Abstract: In one embodiment, the present invention includes a receiver having two complementary input sense amplifiers to receive, amplify and latch a differential signal and to output complementary stage differential output signals to a latch coupled to receive and combine the n? them into a latched differential output signal. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: August 16, 2011
    Assignee: Intel Corporation
    Inventor: Taner Sumesaglam
  • Publication number: 20110178768
    Abstract: Systems and methods of resistance-based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance-based memory circuit includes determining a range of sizes for a clamp transistor and selecting a set of clamp transistors having sizes within the determined range of sizes. For each clamp transistor in the set of clamp transistors, a simulation may be executed to generate a first contour graph representing current values over a range of statistical values. The first contour graph may be used to identify a read disturbance area and a design range of the gate voltage of the clamp transistor and a load of the clamp transistor. The method may execute a simulation to generate a second contour graph representing sense margin over a range of statistical values of the gate voltage of the clamp transistor and the load of the clamp transistor.
    Type: Application
    Filed: January 21, 2010
    Publication date: July 21, 2011
    Applicants: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Seong-Ook Jung, Jisu Kim, Jee-Hwan Song, Seung H. Kang