Abstract: This invention provides a circuit and a method for limiting the power consumed by memory array sense amplifiers while enhancing the speed of memory systems. It provides a circuit and a method which automatically limits the precharge time and voltage, which limits the power consumed and speeds the voltage transitions. The invention automatically disables the data line precharge right after achieving the trip point of the first inverter of the sense output circuit. This is the essence of the automatic saving of power consumption. In addition, the circuit and method of this invention provide for faster access speed, since the data line precharge and voltage swing are limited. Also, the circuit and method of this invention allow for smaller integrated circuit layout area due to no required reference circuit and no required circuit for generating the precharge period.

Abstract: The present invention relates to a sense amplifier select circuit for use in a memory device consisting of cell arrays and sense amplifier arrays arranged in a shared sense amplifier mode. The sense amplifier select circuit includes a first controller for outputting a sense amplifier select signal in response to a block select signal and an operation control signal of a sense amplifier, and a second controller connected to the first controller to control the sense amplifier select signal, wherein the second controller applies an enable/disable signal when selection of a cell array is changed and keeps the enable/disable state when a sense amplifier to be sensed within a selected cell array is changed. As such, a corresponding cell array is continuously connected/disconnected to/from a bit line sense amplifier. As a result, it is possible to significantly reduce consumption of current occurring due to toggle of a sense amplifier select signal.

Abstract: The present invention comprises a pair of circuits (171, 172) within the first stage (100) of an AC signal pre-amplifier. The present invention reduces the current mismatch at the base of the first stage transistors (141, 142, 143, 144) resulting in faster switching times by reducing input stage offset and, hence improving input dynamic range.

Abstract: A sense amplifying circuit and a bit comparator having the sense amplifying circuit. The sense amplifying circuit may include a selecting unit, a sensing unit, a latching unit, an output unit, and a switching unit. The selecting unit may select one pair from a first pair of a first signal and a first inverted signal and a second pair of a second signal and a second inverted signal, in response to a selection signal and an inverted selection signal. The sensing unit may sense voltage levels of one pair of signals selected from the first pair and the second pair. The latching unit may precharge first and second nodes in response to a clock signal and controls voltage levels of the first and second nodes in response to a sensing result of the sensing unit. The output unit may invert the voltage levels of the first and second nodes to generate first and second output signals. The switching unit is capable of controlling the operation of the selecting unit in response to the clock signal.

Abstract: A first sense amplifier has complementary inputs and outputs coupled between a pair of complementary sense lines. Each sense line is connected to a respective complementary digit line through a coupling transistor. The coupling transistors are activated during an initial sensing period to couple a differential voltage from the digit lines to the sense lines. The sense lines are then isolated from the digit lines to allow the first sense amplifier to respond to the differential voltage without being loaded by the capacitance of the digit lines. The sense lines are also coupled to complementary inputs of a second sense amplifier that has complementary outputs coupled to the digit lines. By coupling the inputs of the second sense amplifier to the sense lines rather than the digit lines, the differential voltage applied to the second sense amplifier increases faster than the increase of the differential voltage between the digit lines.

Abstract: The invention provides a method and apparatus for performing a voltage to current conversion. In particular, the invention provides a voltage to current converter configured to vary its transconductance (Gm). Such a converter is configured to receive a voltage input signal combined with a reference voltage signal to be converted to a current output. Optionally, the reference voltage signal may be provided by a parabolic impedance network that includes a bank of resistors and a plurality of corresponding current sources. Each current source corresponds to each node between two resistors, and may be varied in order to program changes in the comparator's Gm. Each resistor and corresponding current source is configured to create an individual reference voltage reference having a value that occurs in a parabolic manner in relation to other voltage references occurring across the impedance network. The converter further includes a plurality of comparators corresponding to the plurality of voltage reference signals.

Abstract: A method and circuits of a high isolation and high-speed buffer amplifier capable to handle frequencies in the GHz range have been achieved. The output to input isolation is primary dependent on the gate-source capacitance of the active buffer transistor. Having two or more in series and by reducing the impedance between them a high isolation can be achieved. The input signals are split in several signal paths and are amplified in the push-pull mode using source follower amplifiers. Then the amplified signals are being combined again. The amplified output current is mirrored applying a multiplication factor. Said method and technology can be used for buffer amplifiers having differential input and differential output or having single input and single output or having differential input and single output. A high reversed biased (output to input) isolation and a reduced quiescent current have been achieved.

Abstract: A system and method of adjusting a sense amplifier to compensate for the process-type of the sense amplifier includes determining a process-type of the sense amplifier. An amplification control parameter is provided to the sense amplifier. The amplification control parameter is adjusted to adjust the sense amplifier according to the process-type of the sense amplifier.

Abstract: A sense amplifier having a synchronous reset capability or an asynchronous reset capability, which is readily implemented and has high speed, is provided. The sense amplifier includes a first sense-amplifying unit which sense-amplifies an input signal in response to a clock signal and generates an output signal, and a second sense-amplifying unit which sense-amplifies a complementary signal of the input signal in response to the clock signal and generates a complementary signal of the output signal. The sense amplifier further includes a first controller which is connected to the first sense-amplifying unit and sets the output signal in response to a reset signal and an inverted signal of the reset signal, and a second controller which is connected to the second sense-amplifying unit and resets the complementary signal of the output signal in response to the reset signal and the inverted signal of the reset signal.

Abstract: A differential output circuit includes first and second inputs, first and second outputs, a resistor element connected between the outputs, first and second N-channel MISFETs, and first and second P-channel MISFETs. The inputs respectively receive first and second complementary input signals. The first N-channel MISFET has a source connected to the first input, a gate receiving a power supply potential, and a drain connected to the first output. The second N-channel MISFET has a source connected to the second input, a gate receiving the power supply potential, and a drain connected to the second output. The first P-channel MISFET has a source receiving the power supply potential, a gate connected to the second input, and a drain connected to the first output. The second P-channel MISFET has a source receiving the power supply potential, a gate connected to the first input, and a drain connected to the second output.

Abstract: A sense amplifier for use in a memory device and in a memory-resident system. The sense amplifier operates on a lower voltage consistent with the voltage range of the differential input data and the sense amplifier further operates on a higher voltage to level-shift the output signal concurrently with the sensing operation. The sense amplifier includes a pair of differential cross-coupled inverters whose inputs are coupled to receive the data from the memory. Once the input nodes of the cross-coupled inverters are charged, the cross-coupled inverters are further coupled to pull-up and pull-down circuits that span the higher voltage range for performing the level-shifting functionality. In order to recondition the sense amplifier for a subsequent sensing process, a clamp circuit shorts the level-shifted outputs together to prevent a higher voltage level from being inadvertently passed to the memory device when isolating pass gates are reactivated.

Abstract: A sensor for a switching circuit detects the logical state of the switching circuit by monitoring the current flow through the switching circuit. The current flow is conditioned by one or more current limiters and a voltage regulator, coupled in series with the switching circuit. The sensor also includes a current limit control circuit coupled to each of the current limiters. The sensor is effectively shielded from the effect of parasitic capacitance in the switching device because the current flow through the switching circuit reacts immediately and without regard to the level of parasitic capacitance whenever the switching circuit makes a state change.

Abstract: In one embodiment, a power switch device (33) includes a first MOSFET device 41 and a second MOSFET device (42). A split gate structure (84) including a first gate electrode (48,87) controls the first MOSFET device (41). A second gate electrode (49,92) controls the second MOSFET device (42). A current limit device (38) is coupled to the first gate electrode (48,97) to turn on the first MOSFET device during a current limit mode. A comparator device (36) is coupled to the second gate electrode (49,92) to turn on the second MOSFET device (42) when the power switch device (33) is no longer in current limit mode.

Abstract: A sense amplifier circuit includes a latch circuit to enhance the speed of a sensing operation and to obviate the need for a latch circuit to capture the output value of the sense amplifier circuit. In one embodiment, first and second differential amplifiers provide a differential signal to the latch circuit. The high gain in the latch circuit resolves the differential signal to a logic signal, which is then provided to an output amplifier. In one embodiment, the differential signal is provided to the latch circuit after the differential signal across the input terminals of the first and second differential amplifiers exceeds a predetermined value.

Abstract: The present invention provides systems and methods related to a variable gain amplifier. The variable gain amplifier includes a first differential amplifier, a second differential amplifier, a combining circuit, and a current control circuit. The first differential amplifier circuit and the second differential amplifier circuit share a common input signal and have different amplification degrees. Each of the first and second differential amplifier circuits includes a first transistor and a second transistor that form a differential pair. The first transistor and the second transistor of each differential amplifier circuit have bases that are supplied with the input signal, and collectors that output signals to the combining circuit. The current control circuit changes a ratio between a bias current of the first differential amplifier circuit and a bias current of said second differential amplifier circuit based on a gain control signal.

Abstract: In transmitting a first pair of differential clock signals UCLK, UXCLK having an extremely small amplitude voltage based on a power-source potential and a second pair of differential clock signals LCLK, LXCLK having an extremely small amplitude voltage based on the power-source potential, an inverting circuit as a signal receiving circuit is composed of a CMOS inverting circuit. A PMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the first pair of differential clock signals. An NMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the second pair of differential clock signals. When the potentials of the differential clock signals change, potentials at the respective gate and source electrodes of the two transistors shift in opposite directions, which surely cuts off the transistors.

Abstract: A method for amplifying a digital signal representative of data to be transmitted by a line driver with pre-emphasis over an output line is provided. The gain of the line driver is varied between an upper value to coincide with switching of the digital signal and a lower value in absence of the digital signal switching. In particular, the varying includes amplifying the digital signal with a first gain for generating an amplified digital signal, delaying the digital signal with a predetermined delay for generating a delayed digital signal, and amplifying the delayed digital signal with a second gain for generating a delayed and amplified digital signal. An ouput signal corresponding to a difference between the amplified digital signal and the delayed and amplified digital signal is output over the output line.

Abstract: An apparatus for transforming single ended signals into differential mode signals. A preferred embodiment comprises an inverter (for example, inverter 505) and a pair of latches (for example, latches 510 and 520). One latch has as its input an input signal to be converted and the other latch has as its input an inverse of the input signal. The latches maybe clocked by a differential mode clock and remove a timing mismatch between the input signal and its inverse that is incurred via the inverter. The latch outputs are then provided to a differential mode buffer to perform signal voltage and current compatibility transformations.

Abstract: An electronic circuit comprising an amplifier (AMP) for amplifying a binary input signal (Ui) including an input stage coupled to receive the binary input signal (Ui) comprising means for supplying a DC current to the input stage. The means supplies a current having a first (I1) current value to the input stage during a period of time that is approximately equal to the period of time corresponding to a transition phase from a first binary signal value to a second binary signal value. During the remaining time, the means supplies a current having a second (I2) current value which is smaller than the first (I1) current value. By virtue thereof, the electronic circuit only consumes a significant amount of power during a transition phase from the first binary signal value to the second binary signal value. The amplifier (AMP) can be implemented in all kinds of digital circuits, of which the digital voltage range (the difference between the second and the first binary values) must be increased.

Abstract: A data interface for CMOS imagers is disclosed that can be either a single-ended interface or a differential interface. The single-ended interface provides compatibility with many existing external devices. Further providing a differential interface allows a lower noise and a lower power interface for external devices that can support a differential signal. The combined single-ended and differential signal interface does not increase the number of pins required for a single-ended only interface. The data transfer width is set to the word width, which allows a fixed timing relationship between the clock edge and data transfer in both single-ended and differential modes. In single-ended mode, the data is transferred once per clock, but in the differential mode, the data is transferred twice per clock, once on each clock edge. This fixed timing relationship eliminates the need for and cost of explicit bit synchronization.

Abstract: A gain boost circuit is provided in a differential amplifier including differentially connected first and second input transistors the drains of which are coupled to sources of first and second cascode transistors. A third cascode transistor has a source coupled to a drain of the first cascode transistor and a drain coupled to a bias current source. A gain boost amplifier has an output coupled to the gate of the third cascode transistor, a first input coupled to the drain of the first cascode transistor, and a second input coupled to the drain of the second cascode transistor.

Abstract: A comparator unit includes a first amplifier stage and a second amplifier stage. The first amplifier stage includes a differential amplifier having a pair of input nodes for receiving a differential signal and a pair of output nodes, a switch connected across the pair of output nodes, and a non-linear load connected across the pair of output nodes. The second amplifier stage is coupled to the pair of output nodes of the first amplifier stage. In one embodiment the second amplifier stage is a non-linear amplifier. In an alternative embodiment, the differential amplifier is a differential pair. In another alternative embodiment, the differential amplifier is a pair of differential pairs.

Abstract: Bi-Variant Coupled Pair (BVCP) circuits suitable for use in channel front-end low noise preamplifiers of magnetic storage devices are described. In a magnetic storage device, a BVCP circuit provides a DC bias voltage for a read transducer, low-noise amplification performance, and relatively small AC coupling capacitor values for reducing the cost of an integrated circuit (IC) in which the BVCP circuit may be embodied. The BVCP circuit also has a controllable input impedance for matching a transmission line impedance for high data rate applications.

Abstract: A sense amplifier structure for multi-level non-volatile memories reads the contents of the memory cells. In particular, a current drawn by a memory cell to be read is compared to a current drawn by a reference cell through a sense amplifier that has one input terminal connected to a circuit node to which said currents are led. Advantageously, the currents are compared at both inputs of the sense amplifier by connecting a second input of said amplifier to a circuit node to which said currents are led, with opposite signs. The method enhances the read precision of the sense amplifier for a given data acquisition time by doubling the differential input voltage.

Abstract: A method and circuits of a high isolation and high-speed buffer amplifier capable to handle frequencies in the GHz range have been achieved. The output to input isolation is primary dependent on the gate-source capacitance of the active buffer transistor. Having two or more in series and by reducing the impedance between them a high isolation can be achieved. The input signals are split in several signal paths and are amplified in the push-pull mode using source follower amplifiers. Then the amplified signals are being combined again. The amplified output current is mirrored applying a multiplication factor. Said method and technology can be used for buffer amplifiers having differential input and differential output or having single input and single output or having differential input and single output. A high reversed biased (output to input) isolation and a reduced quiescent current have been achieved.

Abstract: An input buffer circuit includes a first differential circuit, a second differential circuit, a pull-up circuit, and a pull-down circuit. An input voltage and a reference voltage are provided to the first and second differential circuits. The first differential circuit detects rising edges of the input voltage and causes the pull-up circuit to quickly drive an output voltage to logic high. The second differential circuit detects falling edges of the input voltage and causes the pull-down circuit to quickly drive the output voltage to logic low.

Abstract: In an integrated circuit, a low voltage swing logic communication bus has N+2 data wires for N data signals. Each of the N data signals is carried on its own wire. The communication bus includes two other reference signals.

Abstract: A sense amplifier for use in a memory device and in a memory-resident system. The sense amplifier operates on a lower voltage consistent with the voltage range of the differential input data and the sense amplifier further operates on a higher voltage to level-shift the output signal concurrently with the sensing operation. The sense amplifier includes a pair of differential cross-coupled inverters whose inputs are coupled to receive the data from the memory. Once the input nodes of the cross-coupled inverters are charged, the cross-coupled inverters are further coupled to pull-up and pull-down circuits that span the higher voltage range for performing the level-shifting functionality. In order to recondition the sense amplifier for a subsequent sensing process, a clamp circuit shorts the level-shifted outputs together to prevent a higher voltage level from being inadvertently passed to the memory device when isolating pass gates are reactivated.

Abstract: The present invention provides a semiconductor integrated circuit device equipped with an input circuit capable of stably performing a high-speed operation up to a low voltage. A rail to rail circuit constitutes a differential input circuit, and a circuit similar to such a differential input circuit is used to constitute a bias circuit. A pair of output terminals of a differential circuit constituting such a bias circuit is commonly connected to form a bias voltage corresponding to a middle point. The bias voltage is supplied to the gates of current source MOSFET and the gates of cascode-connected MOSFETs in the differential input circuit, and the gates of the corresponding current source MOSFETs and cascode-connected MOSFETs in the bias circuit corresponding to itself.

Abstract: A differential capacitance sense amplifier capable of measuring a small difference-signal capacitance in the presence of circuit mismatches and large unequal interconnect capacitances. The sense amplifier includes three sections: a common-mode section applies a ‘read’ voltage to two capacitors in a manner that rejects unequal interconnect capacitance, a difference-mode section generates a signal proportional to the capacitance difference between the two capacitors, and an offset-canceling section compensates for circuit mismatches in the difference-mode section. The amplifier can be adapted for use as a sense amplifier for a ferroelectric differential capacitance memory unit.

Abstract: Disclosed is a wide common mode range differential receiver comprising an input stage adapted to receive an input signal and its complement with wide common mode and output said signals as current signals; a plurality of self-cascode biasing stages adapted to receive said current signals and output a first analog differential voltage in phase with said input signal and a second analog differential voltage out of phase with said input signal; and a self-bias differential amplifier adapted to receive said first and second analog differential voltages and output an output signal with substantially reduced jitter.

Abstract: A circuit for controlling a reference node in a sense amplifier switchable between an operating mode and a stand-by mode is provided. The reference node provides a reference voltage in the operating mode. The circuit may include circuitry for bringing the reference node to a starting voltage upon entry into the stand-by mode, circuitry for keeping the reference node at a pre-charging voltage in the stand-by mode, and circuitry for providing a comparison voltage closer to the pre-charging voltage than the starting voltage. Pulling circuitry may also be included for pulling the reference node toward a power supply voltage. Further, a controller may activate the pulling circuitry upon entering the stand-by mode, and disable the pulling circuitry when the voltage at the reference node reaches the comparison voltage.

Abstract: A device for converting an input signal having a bipolar pulse with a positive part and a negative part of same duration, into a difference signal includes a delay member with an input for receiving the input signal and an output. The delay member delays the input signal in order to obtain a delayed signal and outputs the delayed signal to the output. The device further includes a differential amplifier with a first input for receiving the input signal, a second input for receiving the delayed signal, and an output for outputting the difference signal formed from the input signal and the delayed signal.

Abstract: Described is a differential clock receiver comprising a converter, a differential input stage, and a differential output stage. The converter converts a control signal indicative of a timing relationship into a DC offset signal. The differential input stage receives a differential clock signal and the DC offset signal. The differential input stage generates an intermediary differential signal from the differential clock. The intermediary differential signal has a DC offset resulting from the DC offset signal. The differential output stage receives the intermediary differential signal and generates at least two output signals from the intermediary differential signal. The output signals have a timing relationship determined by the DC offset of the intermediary differential signal.

Abstract: Presence or absence of a differential clock is detected. The voltage of each differential clock line is compared to the common-mode voltage and integrated over time by a capacitor. The capacitor is discharged during the portions of the clock cycle that the differential line is over the common-mode voltage. If the clock stops pulsing the capacitor is charged by a current source to activate a clock-loss signal. The clock-loss detector is ideal for high-frequency operation since each differential clock line is applied to only one transistor gate. The common-mode voltage generates a bias voltage for a differential amplifier that receives the true and complement differential clock lines. Diodes prevent capacitor charging by reverse current flow from the differential amplifier when the clock is inactive. The averaged peak voltage or envelope of the differential input signals is detected.

Abstract: A base bias circuit generates a bias voltage for a bipolar transistor. The base bias circuit includes a current mirror circuit which tracks current through a current source which drives emitter current through the bipolar transistor. A primary biasing bipolar transistor and a secondary bipolar transistor have a &bgr; which tracks the &bgr; of the bipolar transistor. The primary biasing bipolar transistor receives current from the current source through a current mirror circuit to develop the bias voltage. A bias resistor coupled between the bias voltage and the base of the primary biasing bipolar transistor tracks resistance variations in the base resistor. The secondary biasing transistor tracks changes in base current to the bipolar transistor and supplies additional current to the primary biasing transistor to compensate for changes in &bgr;.

Abstract: A sense amplifier having improved common mode rejection has a differential input and a differential output. A first level shifting transconductance circuit is connected to receive the differential input. A gain and compensation circuit is connected to the level shifting transconductance circuit, and a buffer is connected to the gain and compensation circuit. The differential output of the sense amplifier is taken at an output of the buffer. A feedback network is connected between the output of the buffer and an input of the gain and compensation circuit. The feedback network includes a divider circuit connected to the output of the buffer and a second level shifting transconductance circuit connected between the divider circuit and the input of the gain and compensation circuit. The first and second level shifting transconductance circuits are preferably matched to one another for distortion cancellation.

Abstract: A differential capacitance sense amplifier capable of measuring a small difference-signal capacitance in the presence of circuit mismatches and large unequal interconnect capacitances. The sense amplifier includes three sections: a common-mode section applies a ‘read’ voltage to two capacitors in a manner that rejects unequal interconnect capacitance, a difference-mode section generates a signal proportional to the capacitance difference between the two capacitors, and an offset-canceling section compensates for circuit mismatches in the difference-mode section. The amplifier can be adapted for use as a sense amplifier for a ferroelectric differential capacitance memory unit.

Abstract: A sensor for a switching circuit detects the logical state of the switching circuit by monitoring the current flow through the switching circuit. The current flow is conditioned by one or more current limiters and a voltage regulator, coupled in series with the switching circuit. The sensor also includes a current limit control circuit coupled to each of the current limiters. The sensor is effectively shielded from the effect of parasitic capacitance in the switching device because the current flow through the switching circuit reacts immediately and without regard to the level of parasitic capacitance whenever the switching circuit makes a state change.

Abstract: A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.

Abstract: The invention provides a method and apparatus for performing a voltage to current conversion. In particular, the invention provides a voltage to current converter configured to vary its transconductance (Gm). Such a converter is configured to receive a voltage input signal combined with a reference voltage signal to be converted to a current output. Optionally, the reference voltage signal may be provided by a parabolic impedance network that includes a bank of resistors and a plurality of corresponding current sources. Each current source corresponds to each node between two resistors, and may be varied in order to program changes in the comparator's Gm. Each resistor and corresponding current source is configured to create an individual reference voltage reference having a value that occurs in a parabolic manner in relation to other voltage references occurring across the impedance network.

Abstract: A circuit including a differential sense circuit and a latch, the differential sense circuit and the latch coupled so as to form a differential sense latch such that, in operation, an electronic signal stored in the latch is retained for at least one clock cycle.

Abstract: An optimized read data amplifier for the output data path of integrated circuit memory arrays comprises a fast, low power and small on-chip area consuming circuit which is advantageously effectuated through the combined application of “current sensing” and “voltage sensing” techniques. In a particular embodiment disclosed herein, an amplifier enable signal is timed with the column read address so that the amplifier is turned “off” when not in use and both data read lines (“DR” and “DRB”) are precharged “high”. No clocking of the read data amplifier is required in order to obviate undesired clock latencies and pipelining and a simple mechanism is implemented such that control of power-up and power-down results in further power savings.

Abstract: A device according to the invention includes memory cells and a current sense amplifier. It also includes a feedback circuit to adjust a gain of the current sense amplifier. The gain is adjusted depending on relative delays of data stored in different ones of the memory cells to be read on the current sense amplifier.

Abstract: In a conventional variable-gain amplifier, when high-frequency signals are fed in, leak current flows through the collector-emitter parasitic capacitance of transistors, making it impossible to attenuate the gain sufficiently. A variable-gain amplifier of the invention has a controller for controlling the operation of input transistors so as to reduce the leak current that flows through transistors because of their collector-emitter parasitic capacitance when high-frequency signals are fed in and thereby prevent saturation of gain attenuation. Another variable-gain amplifier of the invention has a plurality of variable-gain amplifier circuits connected in parallel, and has a current control circuit for controlling the bias current sources provided within each of the variable-gain amplifier circuits so as to reduce the leak current that flows through transistors because of their collector-emitter parasitic capacitance when high-frequency signals are fed in and thereby prevent saturation of gain attenuation.

Abstract: A sense amplifier having a sampling circuit to sample the amplifier input signal; a reference node storing a reference signal corresponding to the input signal; and a timing circuit activating the sampling circuit for a predetermined interval, and admitting the reference signal to the reference node. The sense amplifier also can include a pump capacitor substantially maintaining a value of the reference signal; and a gain circuit coupled with the reference node and disposed to adaptively adjust gain of an output signal produced by the sense amplifier. The sense amplifier can be a single-ended sense amplifier.

Abstract: An input receiver controls an offset voltage by using an output feedback signal to improve a sense speed. The input receiver includes a pre-amplifier that controls an offset voltage in response to a feedback signal and amplifies an input signal with reference to a reference voltage. A sense amplifier amplifies an output signal and an inverted output signal of the pre-amplifier in response to a clock signal. A latch circuit latches an output signal and an inverted output signal of the sense amplifier. An inversion circuit uses the reference voltage as a power supply voltage and inverts an inverted output signal of the latch circuit. In addition, an output signal of the inversion circuit is supplied as the feedback signal. Alternatively, the output signal of the latch circuit may be directly supplied to the pre-amplifier as the feedback signal while not using the inversion circuit.

Abstract: A comparator circuit includes a differential amplifier including load resistors, for amplifying difference between two input voltages of the comparator circuit; an emitter follower circuit for applying positive feedback with respect to a differential amplifier and outputting an output voltage of the comparator circuit; and a grounded-base amplifier, and outputting an output voltage of the comparator circuit, for realizing both voltage output and current output. A grounded-base amplifier includes two transistors each of which has a base supplied with a reference voltage. The differential amplifier includes two load resistors respectively connected to each emitter of the transistors of the grounded-base amplifier. The load resistor flowing a current which is obtained through a collector of the transistor as an output current of the comparator. With this arrangement, it is not necessary to provide a current switch circuit for obtaining current output of the comparator circuit.

Abstract: An amplifier in a semiconductor integrated circuit includes a current-mirror typed differential amplifier and a cross-coupled differential amplifier, whereby a minute voltage difference from a bit line signal or a data bus signal is amplified. The amplifier for generating an amplified signal includes a load for coupling to a first voltage potential, a first sense amplifier responsive to a first data signal, and a second sense amplifier responsive to a second data signal. The first and second sense amplifiers are commonly coupled to the load, and the amplified signal of the first or second data signal is generated.

Abstract: A multiphase comparator circuit includes a first differential stage; a first switching arrangement for connecting an output of the first differential stage to an input of a load circuit; and two or more regeneration stages. Each regeneration stage is connected to a load circuit and to the first switching arrangement. A clock-controlled second switching arrangement selectively provides an operating current to the regeneration stages. The first and second switching arrangements have switches that are driven so as to operate the regeneration stages in a manner temporally offset from each other.