Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.

Abstract: The present invention relates to a differential ring oscillator stage, comprising differential delay means (Q1, Q2) having a first input (IN+) and an inverse second input (IN−) and a first output and an inverse second output, a first output buffer means (34a) having its input connected to the first output of said delay means (Q1, Q2), and a second output buffer means (34b) having its input connected to the second output of said delay means (Q1, Q2), and further comprising a first controllable current source means (M6) which is connected to the output (OUT+) of said first output buffer means (34a) and controlled in accordance with the signal from said second output of said delay means (Q1, Q2), and a second controllable current source means (M5) which is connected to the output (OUT−) of said second output buffer means (34b) and controlled in accordance with the signal from said first output of said delay means (Q1, Q2), said controllable current source means (M5, M6) supplying currents t

Abstract: There are provided a transmission circuit capable of stabilizing high-speed data transfer by driving current, a data transfer control device, and electronic equipment. An HS current driver (transmission circuit) included in a data transfer control device has a current source connected between a first power supply AVDD and a node ND, and switching devices SW1 to SW3, one ends of which are connected to the node ND. The other end of the switching device SW1 is connected to a DP terminal. The other end of the switching device SW2 is connected to a DM terminal. The other end of the switching device SW3 is connected to a DA terminal. The DA terminal is connected to a second power supply AVSS inside or outside the transmission circuit. The transmission circuit is configured so that impedances of each current path from the node ND through the switching devices SW1 to SW3 become substantially equal when the switching device is turned on.

Abstract: A method and circuit for reducing correlated noise in imagers is disclosed. According to an aspect, correlated noise is reduced by coupling the reference inputs of imager amplifiers to common voltage sources. The reference inputs of differential amplifiers on the imager can be coupled to common noise sources such as the imager low gate voltage and array bias voltage through suitably chosen capacitances.

Abstract: A sense amplifier is provided for sensing an input voltage level of a data signal. Such a sense amplifier pre-charges, and subsequently discharges, a pair of nodes through a respective pair of discharge paths. Each of those discharge paths is capable of performing the discharge operation at a rate that is related to either a system voltage supply or an input logic level of the data signal. Because the discharge path that is associated with the data signal includes a greater amount of conductance, it can perform the discharge operation at a faster rate, even where the input logic level does not exceed the voltage of the system voltage supply. A determination is made as to which of the discharge is the faster and, responsively, a rail-to-rail output signal having the same polarity as the data signal, is generated. The input data signal is conveyed to the sense amplifier by a single wire. Also, the sense amplifier does not require a specialized reference voltage for proper operation.

Abstract: A sense-amplifier based on current-source-evaluation. Compared to Conventional sense-amplifiers, a design based on static-current sources scales better to small transistor geometries. The design has lower power consumption, reduced noise, and improved clock scaling.

Abstract: A flip-flop including a first stage and a second stage. The first stage receives a pair of differential signals to generate a set and reset signal. The complement of the set and reset signal generates output signals Q and {overscore (Q)}′. These signals have rising and falling transistors with the same delays for the Q signal and the {overscore (Q)} signal. The second stage has symmetrical pull-up and pull-down circuits.

Abstract: An integrated circuit interconnection comprising a transmission line having a low characteristic impedance, and including a first end and a second end. A driver is coupled to the first end of the transmission line, and the transmission line is terminated with a current sense amplifier having an input impedance corresponding to the characteristic impedance of the transmission line. A plurality of components selected from the group consisting of capacitive elements, inductive elements and a combination of capacitive and inductive elements are connected at spaced intervals to the transmission line between the first and second ends.

Abstract: A current sense amplifier includes a pair of cross-coupled transistors, each transistor being connected between a respective input signal line and a respective output signal generating node, for amplifying voltage difference between the output signal generating nodes. Additionally, the current sense amplifier may include a constant current circuit connected between the output signal generating nodes and a common node for allowing current to flow between the common node and the output signal generating nodes in response to a bias voltage; and a voltage generating circuit for causing a voltage difference between the output signal generating nodes by being turned on in response to a respective output signal.

Abstract: A sense amplifier (40) uses a body shorting device (60) to selectively electrically short circuit the bodies of two transistors (44, 48) that function as a differential sensing pair. Equalization of charge injected into the bodies functions to minimize offset voltage between the two bodies. The body shorting device selectively shorts the bodies in response to a body control signal after a sense operation and after asserting a precharging signal to initiate precharging of the sense amplifier's outputs.

Abstract: A single-ended sense amplifier having a precharge circuit for maintaining a stable voltage on a bitline, a sensing circuit coupled to the bitline for sensing an amount of current flowing into the bitline, a direct current amplification circuit electrically coupled to the sensing circuit for amplifying the current sensed on the bitline, a current-to-voltage conversion circuit for converting the sensed current to a voltage and a voltage amplification circuit for amplifying the voltage at the sense amp output. The sense amplifier can be implemented using standard CMOS components and provides improved access time at low power supply voltage, high robustness to process variations, and the ability to sense very low currents.

Abstract: The input buffer circuit includes an input stage providing a switching point voltage based on a predetermined switching point set between a first and second reference voltages that maximizes the high and low noise margins of the input buffer. The input buffer circuit further includes an output stage. The output stage is coupled to the input stage. The output stage receives the switching point voltage from the input stage and amplifies the switching point voltage to a full logic level voltage.

Abstract: To prevent a resistive delay in a bitline disconnecting circuit, an NMOS latch composing a part of a CMOS latch is composed of four series NMOS transistors, two of which have respective gate electrodes cross-coupled directly to a pair of bitlines without the interposition of the bitline disconnecting circuit therebetween and the other two of which have respective gate electrodes cross-coupled to a pair of first-stage output nodes in a stage subsequent to the bitline disconnecting circuit.

Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mix, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.

Abstract: A magneto-resistive memory is disclosed that includes a high-speed sense amplifier, that can reliably operate at low signal levels. The sense amplifier includes offset cancellation to reduce or eliminate the internal offsets of the amplifier. The offset cancellation is controlled by one or more switches, which during operation, selectively enable the offset cancellation of the amplifier and store the offsets in one or more coupling capacitors.

Abstract: A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.

Abstract: A sense amplifier having three inputs determines the state of a memory bit cell by converting a bit input voltage, a high reference voltage, and a low reference voltage to respective current values. Current differences are formed between a bit current and a high reference current, and between a low reference current and a bit current. Current mirrors (154, 158 and 170, 166) and loads (160 and 168) are used in conjunction with current steering circuitry (150, 140, 142 and 162) to form the difference of the bit current and the high reference current and also form the difference of the low reference current and the bit current. Additionally, the sense amplifier drives differential outputs (OUT and OUT13B) to reflect the difference between the two current differential quantities.

Abstract: A sense amplifier having a sampling circuit to sample the amplifier input signal; a reference node storing a reference signal corresponding to the input signal; and a timing circuit activating the sampling circuit for a predetermined interval, and admitting the reference signal to the reference node. The sense amplifier also can include a pump capacitor substantially maintaining a value of the reference signal; and a gain circuit coupled with the reference node and disposed to adaptively adjust gain of an output signal produced by the sense amplifier. The sense amplifier can be a single-ended sense amplifier.

Abstract: A sense amplifier in which its output nodes provide a full voltage swing between the supply and return nodes. The sense amplifier further includes a reset circuit to selectively equalize the first and second output nodes. An output of the sense amplifier is coupled to either a digital logic gate or a flip-flop to receive the full swing. Each field effect transistor (FET) of the input pair in the sense amplifier is either zero body biased or forward body biased, so that a bulk-source junction of each FET is either zero biased or forward biased.

Abstract: A method and apparatus for sensing logic signals is described. A single-ended sense amplifier may include a differential input with a data input transistor and a dummy input transistor. A controlled offset in the size of the data input transistor and the dummy input transistor may increase noise immunity and other performance attributes. A dummy complimentary path may include a partial set of complimentary transistors to a data set of transistors.

Abstract: A multi-stage differential amplifying circuit (100) is disclosed. Multi-stage differential amplifying circuit (100) may include initial stage differential amplifying circuits (SN1 and SP1). Initial stage amplifying circuits (SN1 and SP1) may receive an input signal at input terminals (H01 and H02) and provide a differential output signal at nodes (N9 and N13). An amplitude controlling transistor (ND) may provide a controllable impedance path between nodes (N9 and N13). Amplitude controlling transistor (ND) may have a control gate connected to a current supply node (N10). The controllable impedance path may be controlled so that a magnitude of a differential output signal at nodes (N9 and N13) may be more consistent even when an offset voltage of an input signal at input terminals (H01 and H02) varies. A next stage differential amplifying circuit (SOP) may receive the differential output signal at nodes (N9 and N13) and provide an output signal at an output terminal (N01).

Abstract: A mixer driver circuit including a differential pair, a differential current supply and a switched current sink. The differential pair has a differential input for receiving a differential input signal. The differential current supply provides a differential output and switches in response to switching of the differential pair to provide a differential output current. The switched current sink biases the differential current supply and sinks current to drive the differential output signal. The differential pair may be a resistive-loaded differential pair of transistors biased by a constant current sink. The differential current supply may include a pair of emitter follower buffers. The mixer driver may further include a pair of constant current sinks and a second pair of emitter follower buffers, where the second pair of emitter follower buffers is biased by the pair of constant current sinks and provides a voltage level shifting drive for the switched current sink.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic with inductive broadbanding fabricated in conventional CMOS process technology. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with inductive broadbanding/C3MOS logic with low power conventional CMOS logic. The combined C3MOS logic with inductive broadbanding/C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A sense amplifier circuit has two inputs for connection to complementary bit lines and an output terminal. The circuit comprises control circuitry responsive to control input for selectively tristating the output terminal.

Abstract: A current mode driver includes a tail current device, a differential pair of input transistors, cascode output transistors, and pre-charge circuits to charge cascode nodes between the differential pair of input transistors and the cascode output transistors. The current mode driver is driven by CMOS drivers that alternately turn the input transistors on and off. A wide-swing bias circuit provides bias voltages for the current mode driver. This bias voltage for the tail current device is closely matched to provide current matching between the bias circuit and the current mode driver.

Abstract: An integrated circuit operational amplifier (op amp) is protected from input voltage levels which may cause output phase reversal of the op amp. Voltage comparators monitor the input voltages to the op amp differential input transistor pair. The op amp and comparators may be fabricated on an integrated circuit substrate and packaged in an integrated circuit package When the input voltage is of such a value which may cause output phase reversal, a comparator senses same and is coupled to circuits within the op amp which prevent the op amp output voltage from going into phase reversal.

Abstract: An analog-to-digital converter includes a plurality of comparators that each have an output, two analog data inputs coupled to a differential analog data input, and two reference voltage inputs. The two reference voltage inputs are each coupled to a resistor ladder that contains a plurality of resistors coupled in series. Importantly, the two reference voltage inputs of each comparator are positively biased, meaning that the positive reference voltage input is coupled to a point on the resistor ladder at a relatively higher potential than the negative reference voltage input. The outputs of the comparators are coupled to an encoder that encodes signals at the outputs into a digital signal. By positively biasing the differential reference voltage inputs of the comparators in this manner, the differential gain, dynamic voltage range, and voltage symmetry of the comparators are advantageously improved.

Abstract: A sense amplifier having a sampling circuit to sample the amplifier input signal; a reference node storing a reference signal corresponding to the input signal; and a timing circuit activating the sampling circuit for a predetermined interval, and admitting the reference signal to the reference node. The sense amplifier also can include a pump capacitor substantially maintaining a value of the reference signal; and a gain circuit coupled with the reference node and disposed to adaptively adjust gain of an output signal produced by the sense amplifier. The sense amplifier can be a single-ended sense amplifier.

Abstract: A current sense amplifier including a transconductance amplifier to measure a current passing through a sense resistor and generate a reference current indicative of the measured current. A current mirror circuit is connected to the transconductance amplifier and receives the reference current for amplification to generate an amplified output current. A cascode circuit is connected serially to the current mirror circuit to boost an output impedance for the amplifier at the output of the generated amplified output current. The current mirror circuit and cascode circuit of the current sense amplifier are each formed from a pair of transistors sharing a common control node, with the transistors realized using with bipolar or MOS technology.

Abstract: An input-output line sense amplifier of a semiconductor memory device that consumes a small amount of current and direct current (DC), includes a current sensing circuit for sensing only a portion of the current through the input-output line and the complementary input-output line, a first amplifier operating from another portion of the sensed current and of the complementary current to amplify and invert a first detected output signal of the current sensing circuit, a second amplifier operating from yet another portion of the sensed current and of the complementary current to amplify and invert a second detected output signal of the current sensing circuit.

Abstract: A sense-amplifying circuit 10 which comprises a pair of inverters (TP0, TN0, TP1 and TN1), wherein an output of each inverter is connected to an input of the other inverter, drains of sensing transistors TN2 and TN3 are respectively connected to each source of the pair of inverters in series, the gates of both sensing transistors TN2 and TN3 are connected to differential input signal lines 12 and 14, and the sources of both sensing transistors TN2 and TN3 are connected through a common node with a transistor TN4, which works not only as a constant current source but also as an operation switch for the sense-amplifying circuit.

Abstract: A sense amplifier in which its output nodes provide a full voltage swing between the supply and return nodes. The sense amplifier further includes a reset circuit to selectively equalize the first and second output nodes. An output of the sense amplifier is coupled to either a digital logic gate or a flip-flop to receive the full swing. Each field effect transistor (FET) of the input pair in the sense amplifier is either zero body biased or forward body biased, so that a bulk-source junction of each FET is either zero biased or forward biased.

Abstract: An integrated circuit has a differential amplifier in a basic circuit having two input transistors, a load element and a power source. The power source has an N-type channel MOS transistor whose controlled path is connected to the input transistors and to a supply terminal of the power source. A control terminal of the transistor is connected to a potential that is positive with respect to a reference potential. The supply terminal of the power source is connected to a potential which is negative with respect to the reference potential and which is made available by a voltage source for switching off cell field transistors of a DRAM memory. The gate-source voltage that is increased in this way improves the behavior of the circuit with respect to fluctuations in potential and permits more favorable dimensioning of the transistor.

Abstract: A semiconductor integrated circuit includes a sense amplifier for amplifying an input signal and a complement of the input signal. The sense amplifier includes cross-coupled transistors. Each unique cross-coupled transistor is coupled to a corresponding unique transistor formed as a diode. A resistor is coupled in series between one cross-coupled resistor and an input port receiving the input signal, and another resistor is coupled in series between the other cross-coupled transistor and another input port receiving the complement of the input signal. Resistances associated with the sources of each cross-coupled transistor provide the resistance of the resistors.

Abstract: A sense amplifier inverts the output from the pass transistor to control a pre-charge transistor. The combination of the inverter and pre-charge transistor pre-charges the output to a level just below the flip level of the following data latch circuit. If the data cell read is a low threshold cell (conductive or “1”), the output level does not significantly change, and the data is rapidly latched and read. If the data cell is a high threshold cell (non-conductive or “0”), the pass transistor shuts off and the output is pulled up above the flip level of the data latch circuit through a pull-up path. The pre-charge level is near the flip level, so the output does not have to be pulled up very far, thus reading a “0” is also fast. In one embodiment, the pull-up transistor is a p-channel MOSFET with the gate grounded, thus providing more constant current than a diode-connected configuration.

Abstract: An output circuit is provided which exhibits a waveform having a higher edge rate, with less ringing and power consumption than many conventional differential amplifier output driver circuits. A pre-driver stage using a current-mode logic (CML) design eliminates the frequency dependent transfer characteristics associated with emitter follower amplifiers used with emitter-coupled logic (ECL)-pre-drivers. The final stage CML circuit has been modified to eliminate the Miller-effect capacitance, using cascode transistors to maintain a constant voltage at the collectors of the final stage CML circuit transistors. The cascode transistors isolate the switching noise of the final stage CML transistor pair. Further, the bases of the final stage CML transistors present a smaller load to the pre-driver stage output, permitting the pre-driver stage to be a CML rather than an ECL design. A method of amplifying a differential signal in accordance with the principles of the above-described circuit is also provided.

Abstract: A voltage regulator may include one or more features for generating high PSRR. For example, source follower devices may be included in the voltage regulator for providing current sources for the output voltage nodes. The source followers may be sensitive to power supply noise at the gate terminal. Filters are included on the gate terminals to filter the power supply noise, thus reducing the noise at the gate terminals. As another example, the voltage regulator may employ current sources on the output voltage nodes which produce current inversely proportional to the current drawn by the load. In one embodiment, the voltage regulator may include a power control circuit used to provide overvoltage protection during power up. The power control circuit provides a voltage during power up, and ceases providing the voltage after a time interval so that the circuit may operate.

Abstract: A differential sensing amplifier for content addressable memory is disclosed. In the differential sensing amplifier there is a detection circuit for detecting at an input node a change in an input signal comprising, a differential amplifier having a sense node and a reference node, a means for alternating the differential amplifier between a precharge phase and a sense phase, a precharge means for providing an input signal precharge voltage to the input signal via an input device, said input device selectively coupling the sense node to the input signal upon a change in the input signal, and a reference means for providing the reference node with a reference signal that continuously tracks the input precharge voltage during the precharge phase and actively maintains the input signal precharge voltage during the sense phase.

Abstract: A current tail circuit and method for a differential transistor pair affords the capability of sensing an input differential signal having a low common mode voltage when using, for example, an NMOS differential transistor pair. A current source device and a capacitor may be employed to provide at the common node of the differential transistor pair what appears to be a constant current source connected to a “negative voltage.” In one embodiment particularly useful when using an NMOS differential pair, one terminal of a capacitor is precharged to VDD and the other terminal is precharged to VSS (i.e., ground). When the amplifier needs to sense its differential input signal, a control signal turns off precharge transistors and couples the capacitor terminal previously precharged to VSS to the common-source node of a differential transistor pair.

Abstract: An integrated circuit including a comparator circuit and a vertical voltage control switch element formed on a single substrate. The comparator circuit including a differential amplifier circuit having a current mirror circuit M, a differential amplifier circuit D1 with two current paths L1 and L2, and an inverter INV. The output section of the current mirror circuit M is used as a constant current source for the differential amplifier circuit. The current mirror circuit M includes a load MOS transistor 1, a MOS transistor 2 constituting an input section, and a MOS transistor 10 constituting an output section. The current path L1 of the differential amplifier circuit D1 includes a load MOS transistor 11, an amplifying depletion type MOS transistor 13, and an input terminal in1. Similarly, the current path L2 includes a load MOS transistor 12, an amplifying depletion type MOS transistor 14, and an input terminal in2. The inverter INV is constructed with a load MOS transistor 3 and a switching transistor 4.

Abstract: A sense amplifier includes a pair of differential input terminals and a pair of differential output terminals. Each of a pair of precharge circuits connects a respective one of the differential output terminals to precharge potential and has a clocking input. The precharge circuits maintains the respective differential output terminals at ground in response to a precharge state of a signal at the clocking input. The sense amplifier also may include a pair of evaluation circuits, each connecting a respective one of the differential output terminals to an evaluation potential and coupled to a respective one of the differential input terminals. The evaluation circuits may transition the respective output terminal to an evaluation voltage in response to an evaluation state of a signal at the respective differential input terminal.

Abstract: A memory module comprises at least one memory device, a clock generator providing clocking signals, and a clocking topology providing the clocking signals to said at least one memory device.

Abstract: An edge-triggered latch that incorporates pass-transistor logic (PTL) in the data and clock generation paths. In accordance with one embodiment, an edge-triggered latch includes a data input and at least one data path PTL transistor that passes data from the data input into a storage node in response to a latch trigger signal. A latch trigger circuit generates the latch-trigger signal in response to a clock signal transition.

Abstract: A sensor for measuring a current passing through a load. The sensor has a power transistor having a first terminal connected to substantially constant voltage and a second terminal connected to the load. The sensor can sample a voltage difference with a variable capacitor, and a controller can be configured to cause a variable capacitor in the current sensor to have a capacitance inversely proportional to a resistance of the power transistor, whereby a charge stored on the variable capacitor is proportional to the current passing through the power transistor when the sampling switches are opened. A comparator can compare the current through the power transistor to a known reference current to generate a digital output signal. The sensor can include a power transistor, reference transistor and amplifier connected and configured so as to generate a signal on a reference line having a current of known proportion to the current passing through the load.

Abstract: A sense amplifier in which its output nodes provide a full voltage swing between the supply and return nodes. The sense amplifier further includes a reset circuit to selectively equalize the first and second output nodes. An output of the sense amplifier is coupled to either a digital logic gate or a flip-flop to receive the full swing. Each field effect transistor (FET) of the input pair in the sense amplifier is either zero body biased or forward body biased, so that a bulk-source junction of each FET is either zero biased or forward biased.

Abstract: An input-output line sense amplifier of a semiconductor memory device that consumes a small amount of current and direct current (DC), includes a current sensing circuit for sensing only a portion of the current through the input-output line and the complementary input-output line, a first amplifier operating from another portion of the sensed current and of the complementary current to amplify and invert a first detected output signal of the current sensing circuit, a second amplifier operating from yet another portion of the sensed current and of the complementary current to amplify and invert a second detected output signal of the current sensing circuit.

Abstract: The invention provides an apparatus, method and means for capturing data. In an aspect, a differential and complementary input folded-cascode clocked amplifier is provided. In an aspect, the invention provides rail-to-rail input common-mode voltage range. In an aspect, the invention provides a setup/hold time window that is smaller than the setup/hold time window of a conventional clocked amplifier and a conventional input amplifier with a separate amplifier and latch. In an aspect, the invention provides high common-mode rejection as compared with conventional clocked sense amplifiers.

Abstract: A sense amplifier circuit includes a first voltage-controlled current source to supply current proportional to a first bias voltage to a reference node and a second voltage-controlled current source to supply current proportional to a second bias voltage to a sensing node. The first and second bias voltages are internally generated in response to an externally applied sense amp control signal. A current mirror circuit is also provided for the sense amplifier circuit. The current mirror circuit commonly deliver current proportional to the voltage level of the reference node to the reference and sensing nodes. A differential amplifier amplifies a difference voltage between reference and sensing nodes.

Abstract: An integrated level shifter circuit converts an input signal having a first voltage potential to an output signal having a second voltage potential. The level shifter circuit provides circuit operation between the sections when the voltage potential of the input logic signal is converted to the output logic signal having lower voltage potential. For logic signals transmitted between sections of an integrated circuit operating with different supply voltages. The level shift circuit for each input includes two transistors and a voltage divider circuit having two resistors in series. The values of the resistors are selected to yield a desired output voltage at a node between the two resistors. In effect, the resistors lessen a full 0.9 volt diode drop to yield a level shift which is a fraction of a diode drop. A capacitor in parallel with the resistor provides a path for AC signals and increases both the speed and bandwidth of the level shifter.

Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells interconnected at least one interconnection node and connected between a first signal input of a first cell and an output terminal of the second cell, each cell comprising a pair of transistors which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference through respective bias members. The structure further comprises a circuit leg connecting a node of the first cell to the output terminal and comprising a transistor which has a control terminal connected to the node of the first cell, a first conduction terminal connected to the output terminal, and a second conduction terminal coupled to a second voltage reference through a capacitor.