Abstract: The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference between a first and a second signal, a first circuit adapted to generate a control signal based upon the determined phase difference, and a second circuit. The second circuit is adapted to receive a third signal, receive a fourth signal, modify the fourth signal based upon the control signal, and provide the third signal and the modified fourth signal to the phase detector as the first and second signals.

Abstract: Delay-locked loop (DLL) integrated circuits include digital phase comparators that are unaffected by variable duty cycle ratios. These phase comparators determine a shortest direction to phase lock before establishing a value of a compare signal (COMP) that specifies the shortest direction. The phase comparator is responsive to a reference clock signal REF and a feedback clock signal FB. These clock signals have equivalent periods and may have equivalent non-unity duty cycle ratios. The phase comparator is configured to determine whether a first degree to which the reference clock signal REF leads the feedback clock signal FB is smaller or larger than a second degree to which the reference clock signal REF lags the feedback clock signal FB. Based on this determination, the phase comparator generates a compare signal COMP that identifies a direction in time the feedback clock signal FB should be shifted to bring it into alignment with the reference clock signal REF.

Abstract: A phase-locked loop circuit has a fractional-frequency-interval phase frequency detector, a charge pump, an oscillator, and a divider. The fractional-frequency-interval phase frequency detector has a phase frequency detector unit that is utilized as or comprises a plurality of phase frequency detector units. The divider is responsive to the oscillator and provides divider values for dividing an oscillator frequency by the divider values to provide a feedback frequency of a feedback loop signal of the phase-locked loop circuit. A reference input frequency is input as a first input into the phase frequency detector unit. The feedback frequency is input and selectively delayed as second inputs into the phase frequency detector unit so that the second inputs are aligned for input according to the reference input frequency and an oscillator frequency is, in effect, responsive to the phase frequency detector units and allowed to be divided by a fractional-integer divider value.

Abstract: The present invention relates to a device for comparison CMP, which is designed to emit a control signal Vcnt, which is representative of a difference which exists between the input signal frequencies Vdiv and Vref. The device according to the invention includes a phase/frequency comparator PD, which supplies a regulation signal Tun, which is subjected to pulse width modulation according to the difference observed. The device also includes a current source, which is designed to emit a charge current Ics, with a value which is controlled by the regulation signal Tun. The device further includes a capacitive element Cs, which is designed to generate the control signal Vcnt, under the effect of the charge current Ics. By means of a regulation signal Tun, which has a frequency which is virtually constant, the invention makes it possible to impose high-frequency variations on the control signal Vcnt.

Abstract: A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be grouped into two pairs of true and complement signals. By selectively re-assigning the inputs to different signal pairs, the differential logic gate can be made to provide one of either simultaneous AND/NAND logic operations or simultaneous OR/NOR logic operations. The differential D-flip-flop is implemented following a master/slave configuration and is response to the true and complement forms of an input clock signal, an input reset input, and input data signal, and also provides true and complement forms of an output signal. All components within the phase and frequency detector are exemplified in CML circuit configuration.

Abstract: An apparatus comprising a first circuit configured to generate (i) a pump up signal in response to a reference signal and a reset signal and (ii) a pump down signal in response to an input signal and said reset signal and a second circuit configured to (i) generate said reset signal in response to said pump up signal and said pump down signal.

Abstract: A phase detector and control signal generator responds to a reference signal and a feedback signal to produce a non-delayed up and down signal. A programmable delay unit delays the non-delayed up and down signal to provide up and down signals for a charge pump. A divider configured to respond to the up and down signals provides a divided clock signal. A non-overlapped clock generator configured to respond to the divided clock signal to provide non-overlapped hold even and hold odd signals for the switched-capacitor ripple-smoothing filter.

Abstract: A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

Abstract: A structure and associated method for reducing a static phase error in a phase-locked loop circuit. The phase-locked loop circuit comprises a voltage controlled oscillator and a phase frequency detector. The voltage controlled oscillator is adapted to provide a first clock signal comprising a first frequency. The phase frequency detector is adapted to compare the first clock signal comprising the first frequency to a reference clock signal comprising a reference frequency. The phase frequency detector comprises a programmable circuit adapted to vary a minimum pulse width of an increment pulse and a minimum pulse width of a decrement pulse. The programmable circuit is further adapted to reduce a static phase error of the phase locked-loop circuit.

Abstract: A phase comparison of timing signals is made by combinational circuitry which receives the timing signals and a window signal, the window signal identifying edges of the timing signals to be compared. The comparison may result in a charge pumped output which can be fed back to control the phase of one of the timing signals. The phase comparator and charge pump circuit can be included in a multiplier circuitry in which the phase of an input signal is directly compared to the phase of an edge of the multiplied signal.

Abstract: An apparatus is disclosed that is an analog phase detector where a summation technique is used to determine the phase difference of the two input waveforms of the phase detector. Instead of multiplying the two signals—a technique used in the prior art—a difference amplifier subtracts one waveform from the other. The difference amplifier produces a waveform whose maximum peak-to-peak amplitude is directly proportional to the phase difference. Feeding this waveform into an envelope detector followed by a low pass filter, we are able to get a DC voltage level that is directly proportional to the phase difference of the two input waveforms.

Abstract: A phase frequency detector with a narrow control pulse comprises mainly two substantially equivalent phase latches with a narrow control pulse, and a reset signal generating unit. Each phase latch of a narrow control pulse has a clock pulse input end and a signal output end. Both latches also are connected to the reset signal generating unit. The logic value of each signal output end is decided by which clock pulse input appears first. The reset signal generating unit decides whether or not to generate a reset signal according to the logic values of both signal output ends. The reset signal is then sent to both phase latches of a narrow control pulse, if generated. The present invention can be implemented by a simple circuit. Comparing with the RS NAND PFD or master-slave D PFD, the PFD of the invention has the advantages of faster speed, saving more power and smaller IC chip area.

Abstract: A phase locked loop that includes a receiver that is adjustable to substantially match delay of a system clock and a feedback clock at an input of the phase locked loop is provided. The receiver employs system clock path circuitry to input the system clock and feedback clock path circuitry to input the feedback clock, where current flow and load resistances associated with the system clock path circuitry and current flow and load resistances associated with the feedback clock path circuitry are responsive to one or more bias signals that are adjustable using one or more adjustment circuits that are operatively connected to the receiver. The control of the one or more bias signals via the one or more adjustment circuits facilitates the generation of substantially delay matched system and feedback clocks.

Abstract: A phase detector is described that includes a load circuit that presents both a high differential impedance and a low common mode impedance. The load circuit is coupled to (1) a power supply and (2) a first node and a second node. The first and second nodes form an output of the phase detector. A capacitive circuit has (1) a first capacitor coupled to the first node and ground and (2) a second capacitor coupled to the second node and ground. A first circuit is coupled to the first and second nodes for detecting a phase difference between a first signal and a second signal. A second circuit is coupled to the first and second nodes for detecting the phase difference between the first and second signals and for minimizing phase detection error of the first circuit such that the phase difference between the first and second signals can be detected with minimized phase detection error. Each of the first and second circuits receives the first and second signals and a reference signal.

Abstract: A circuit includes a signal generator and a discriminator. The signal generator generates a plurality of reference signals where a majority of the reference signals have the same phase. The discriminator generates a regulated signal that has the same phase as the majority of the reference signals. Therefore, if an environmental disturbance such as a single-event transient (SET) shifts the phase or phases of a minority of the reference signals, the discriminator maintains the regulated signal at a stable frequency and phase by generating the regulated signal with reference to the undisturbed majority of the reference signals.

Abstract: An object of the present invention is to provide a phase comparing circuit capable of outputting a signal in accordance with phase difference with a high degree of accuracy, even if the phase difference is small. The phase comparing circuit according to the present invention has a feed forward circuit connected between a frequency phase comparator and a charge pump. The feed forward circuit has a capacitor connected between each Q output terminal of flip-flops in the frequency phase comparator and the current path of the charge pump circuit. The capacitor couples capacitively the Q output terminals of the D flip-flops with the current path of the charge pump circuit, in order to quickly provide the Q output voltages of the D flip-flops to the charge pump circuit.

Abstract: A phase frequency detector (PFD) circuit (516) compares two clock signals and generates a number of outputs to indicate a phase difference between these two clock signals (513, 519). The phase frequency detector has more than three states. The PFD circuit may be used in phase locked loop (PLL) or delay locked loop (DLL) circuit in order to maintain or lock a phase relationship between the two clock signals. The PFD circuitry will allow for a fast lock acquisition time, even when there is a relatively wide frequency range between the two clock signals.

Abstract: In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop filter capacitor nor for a large loop filter capacitor to be integrated on the same integrated circuit die as the PLL. In a preferred embodiment, an analog phase detector is utilized whose phase error output signal is delta-sigma modulated to encode the magnitude of the phase error using a digital (i.e., discrete-time and discrete-value) signal. This digital phase error signal is “integrated” by a digital integration block including, for example, a digital accumulator, whose output is then converted to an analog signal, optionally combined with a loop feed-forward signal, and then conveyed as a control voltage to the voltage-controlled oscillator.

Abstract: A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuous regions. The amount of phase modification of the transmitted signal is allowed to fluctuate during one cycle of the operational frequency of the circuit. Determination of whether or not the reception signal during this interval can be received is continued, and the distribution of amount of phase modification that can be normally received is detected. The detected amount of phase modification defines continuous regions, and an optimum phase region is specified by selecting a region having a width of a specified value or more or the region having the greatest width. The optimum amount of sampling phase modification is determined from the upper and lower limit values of this region.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present (i) a pump up signal in response to a reference signal and a reset signal and (ii) a pump down signal in response to an input signal and the reset signal. The second circuit may be configured to (i) switch a pull up signal in response to the pump up signal, (ii) switch a pull down signal in response to the pump down signal, and (iii) present the reset signal in response to switching the pull up signal and the pull down signal.

Abstract: An improved DDLL containing a majority filter counter circuit is disclosed. The majority filter counter circuit is located between the phase detector and the shift register of the DDLL. The majority filter counter circuit receives shifting commands from the phase detector and filters the shift commands from reaching the shift register until a predetermined number (e.g., 16) have been received from the phase detector before transmitting a shift command (either shift right or shift left) to the shift register. Once the shift register receives the shift command, the shift register directs the delay line to shift by one tap in either a shift right or a shift left direction depending upon the phase relationship between CLKIn and CLKOut. By waiting for e.g., 16 shift commands, the majority filter counter circuit ensures that a premature shift command is not delivered to the shift register in the case of a noise event.

Abstract: A time discrete PLL-tuning system includes a phase detector and a voltage-controlled oscillator (VCO) for tuning the frequency (fVCO) thereof to a frequency equal to N/M times a reference frequency (fREF), with M being a factor indicating the number of frequency steps in which a transmitter/receiver channel distance is divided, and N being the number of frequency steps in which the oscillator frequency is divided. The sampling frequency of the phase detector is substantial equal to the reference frequency (fREF).

Abstract: A phase detector includes a Gilbert block for outputting a signal proportional to a phase difference between first and second input signals to a first output terminal, and a current source for determining a current in the first output terminal. The current source is controlled by a reference current signal. A converter outputs a current to a second output terminal in response to the signal output from the first output terminal. A variable current source varies the current output to the second output terminal. A controller controls the variable current source in response to the first and second input signals.

Abstract: A phase comparator which eliminates jitter in a clock signal extracted in a phase locked loop. The phase comparator includes: a flip-flop circuit which inputs input data and the clock signal and stores the input data in response to the clock signal; a delay circuit which inputs the input data and delays the input data by a predetermined angle of 0° through 180°; a first logic gate which inputs the input data and an output signal of the flip-flop circuit and which outputs an output signal by taking an exclusive OR or exclusive NOR thereof; and a second logic gate which inputs the data and the output signal of the delay circuit and which outputs an output signal by taking an exclusive OR or exclusive NOR thereof.

Abstract: A phase detector is described that includes a load circuit that presents both a high differential impedance and a low common mode impedance. The load circuit is coupled to (1) a power supply and (2) a first node and a second node. The first and second nodes form an output of the phase detector. A capacitive circuit has (1) a first capacitor coupled to the first node and ground and (2) a second capacitor coupled to the second node and ground. A first circuit is coupled to the first and second nodes for detecting a phase difference between a first signal and a second signal. A second circuit is coupled to the first and second nodes for detecting the phase difference between the first and second signals and for minimizing phase detection error of the first circuit such that the phase difference between the first and second signals can be detected with minimized phase detection error. Each of the first and second circuits receives the first and second signals and a reference signal.

Abstract: Phase-reset circuits provide first and second frequency-divided input signals to a phase/frequency detector (PFD) used in a phase-locked loop (PLL). The phase-reset circuits receive first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD generates control signals based on the phase difference between the frequency-divided input signals. Normally, the phase-reset circuits frequency divide the first and second input signals using divisors N and M, respectively. If other circuitry detects that the PFD has missed a clock cycle in the first or second clock-divided input signals, the corresponding phase-reset circuit alters its divider so that the next clock edge on the corresponding input signal clocks through to the PFD. This causes the PFD to quickly set its affected control signal to what it would have been had the clock cycle not been missed.

Abstract: A semiconductor integrated circuit comprises a phase control unit for shifting the phase of an input signal by two or more different fixed phases so as to generate two or more output signals out of phase. A phase detector detects phase differences among the two or more output signals from the phase control unit, and generates one or more correction signals each having a value corresponding to a deviation of one of the detected phase differences from a desired phase difference. The phase detector feeds the one or more correction signals back to the phase control unit so as to make the detected phase differences equal to desired phase differences, respectively.

Abstract: A phase detector includes a Gilbert block for outputting a signal proportional to a phase difference between first and second input signals to a first output terminal, and a current source for determining a current in the first output terminal. The current source is controlled by a reference current signal. A converter outputs a current to a second output terminal in response to the signal output from the first output terminal. A variable current source varies the current output to the second output terminal. A controller controls the variable current source in response to the first and second input signals.

Abstract: The detection circuit comprising: a first D-type flip-flop circuit F/F1, to which the data signal D1 and the clock signal C1 are input; a first delay circuit DL2 which delays the clock signal C1 by a prescribed amount of time, so as to generate a delayed clock signal C1′; a second D-type flip-flop circuit F/F2, to which the output signal Q1 of the first D-type flip-flop circuit F/F1 and the delayed clock signal C1′ are input; a second delay circuit DL1 which delays the an output signal Q2 of the second D-type flip-flop circuit F/F2 so as to generate a first delayed signal Q2′, a third delay circuit DL3 which delay the an output signal Q1 of the first D-type flip-flop circuit F/F1 so as to generate a second delayed signal Q1′, a fourth delay circuit DL4 which delays the data signal D1 so as to generate a delayed data signal D1′, a first AND circuit AND2 which calculates a logical product of the first delayed signal Q2′ and the second delayed signal Q1′ so as to output

Abstract: A phase detector is described that includes a load circuit that presents both a high differential impedance and a low common mode impedance. The load circuit is coupled to (1) a power supply and (2) a first node and a second node. The first and second nodes form an output of the phase detector. A capacitive circuit has (1) a first capacitor coupled to the first node and ground and (2) a second capacitor coupled to the second node and ground. A first circuit is coupled to the first and second nodes for detecting a phase difference between a first signal and a second signal. A second circuit is coupled to the first and second nodes for detecting the phase difference between the first and second signals and for minimizing phase detection error of the first circuit such that the phase difference between the first and second signals can be detected with minimized phase detection error. Each of the first and second circuits receives the first and second signals and a reference signal.

Abstract: The present invention relates generally to the field phase detectors and particularly to a phase detector being formed by a flip-flop.

Abstract: In a phase locked loop arrangement of a frequency synthesiser, a signal outputted from a voltage controlled oscillator is locked to a reference oscillator. A phase detector is arranged so that the frequency of the reference oscillator is a multiple of the frequency of the voltage controlled oscillator, which significantly reduces the phase noise emitted by the voltage controlled oscillator.

Abstract: A phase locked loop (PLL) is used in a radio communication system such as a frequency mixer, a carrier frequency and the like. The phase locked loop (PLL) includes a phase/frequency detector for comparing a phase/frequency of a reference signal and a feedback signal. The phase/frequency detector includes: a NAND gate logic circuit for NANDing a first signal and a second signal to output a NANDed signal; a first latch unit for latching the NANDed signal and outputting the first signal in response to a reference frequency; and a second latch unit for latching the NANDed signal and outputting the second signal in response to a feedback frequency. The phase locked loop (PLL) further includes a filter controller for changing a bandwidth of a low pass filter in response to an output signal of the phase/frequency detector.

Abstract: A radio device includes phase discriminator with a phase locked loop. Where when there is no phase locking, the output voltage of the phase discriminator remains constant, which provides considerable gain for loop. When there is phase locking, the phase discriminator produces an error proportional to the phase difference. An output of the phase discriminator has a constant amplitude with an input signal and a reference signal have different frequencies.

Abstract: A phase comparator for comparing the relative phase of a first input signal and a second input signal. The phase comparator detects a slipping condition, the slipping condition present if the first input signal leads the second input signal in phase and the first input signal is delayed for at least one cycle such that a first rising edge of the first input signal lags a first rising edge of the second input signal by greater than 180°. The phase detector resets at least one output of the phase comparator upon the detection of the slipping condition. Also described are circuits to implement the phase comparator and a transconductance compensation circuit for a filter, and methods of comparing phase and transconductance compensation.

Abstract: A process of clock recovery during the sampling of computer-type signals, wherein the sampling clock is generated from a phase locked loop or PLL which multiplies a given frequency by an integer number, includes gauging the position of the edges of the computer-type signals with respect to the sampling clock with the aid of an analog ramp triggered by the rising edges of the said signals in such a way as to obtain a first position-dependent value, carrying out a sampling clock phase correction and then carrying out a sampling clock frequency correction by using a processor.

Abstract: The present invention provides a phase comparator provided in a phase locked loop circuit, the phase comparator converting a phase difference between first and second input signals into a current signal, wherein the phase comparator has: a lock detector for detecting locked and unlocked states of the phase locked loop circuit to generate a detected signal which indicates one of the locked and unlocked states; and a current source connected to the lock detector for receiving the detected signal from the lock detector and varying a supply current based on the detected signal, so that if the detected signal indicates the unlocked states, then the current source increases the supplying current.

Abstract: An object of the present invention is to provide a phase comparing circuit capable of outputting a signal in accordance with phase difference with a high degree of accuracy, even if the phase difference is small. The phase comparing circuit according to the present invention has a feed forward circuit connected between a frequency phase comparator and a charge pump. The feed forward circuit has a capacitor connected between each Q output terminal of flip-flops in the frequency phase comparator and the current path of the charge pump circuit. The capacitor couples capacitively the Q output terminals of the D flip-flops with the current path of the charge pump circuit, in order to quickly provide the Q output voltages of the D flip-flops to the charge pump circuit.

Abstract: A phase comparison of timing signals is made by combinational circuitry which receives the timing signals and a window signal, the window signal identifying edges of the timing signals to be compared. The comparison may result in a charge pumped output which can be fed back to control the phase of one of the timing signals. The phase comparator and charge pump circuit can be included in a multiplier circuitry in which the phase of an input signal is directly compared to the phase of an edge of the multiplied signal.

Abstract: In an high-frequency LSI chip, a clock signal generating circuit establishes accurate synchronization between an input clock signal and an internal clock signal to prevent an input circuit from causing a synchronization shift. The clock signal generating circuit includes an input circuit for amplifying an input signal and outputting an amplified signal as a first internal signal; a variable delay circuit, on the basis of a control signal, for delaying the first internal signal and outputting a delayed signal as a second internal signal; a phase comparator for finding a phase difference between the input signal and second internal signal and outputting a phase difference signal indicative of the phase difference; and a control circuit for generating the control signal on the basis of the phase difference signal. Thus, the influences of a delay caused by the input circuit, which would not be avoided in the prior art, can be avoided and the accurate internal clock signal can be generated.

Abstract: An improved digital phase detector is provided for detecting and compensating for a cycle slip between a reference signal and a frequency source signal, the reference and frequency source signals each comprising pulses, each pulse defined by a leading edge and a trailing edge. The digital phase detector includes a detector circuit for detecting a cycle slip where two successive leading edges of one of the reference and frequency source signals are received before a leading edge of the other signal is received. An output circuit is operatively coupled to the detector circuit for developing a correction signal responsive to said detecting.

Abstract: The present invention provides a phase detector without dead zone, which can reduce clock jitter and provide higher tolerance for data random jitter. It can output a plurality of control signals (up,dn) through the function of a plurality of multi-phase clock signals to detect the transition edge of data signals. Therefore, the relation between the phase error &thgr;e and the voltage Vd of a phase-locked loop can be adjusted to be nearly linear dependent. In this way, the phase-locked loop in accordance with the present invention has no dead zone, clock jitter can be reduced and tolerance for data random jitter can be enhanced.

Abstract: Provided are a phase comparator (BBD) 10 for generating a pulse of a signal UP0 or DOWN0 depending on lead or lag of the falling edge of a clock recovered from DATA, relative to the edge of DATA, an overrun detector circuit 20 activating an overrun signal OVR while the circuit 20 detects that lead or lag of the falling edge of the clock exceeds &pgr;/2, a state latch circuit 30 latching a state of either a signal UP0 or DOWN0 being active before the signal OVR transits active, and a selection circuit 40 outputting the signals UP0 and DOWN0 as signals UP and DOWN while the signal OVR is inactive, and outputting the signals UP0 and DOWN0 as the signals DOWN and UP while the signal OVR is active.

Abstract: A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer.

Abstract: A circuit monitor performance of an integrated circuit. The circuit includes a clock signal and a phase delay detection circuit. The clock signal is used by the integrated circuit to generate an output signal on an output pin of the integrated circuit. The phase delay detection circuit detects relative phase difference between the clock signal and the output signal on the output pin of the integrated circuit. The phase delay detection circuit includes a digital signal generator and an integrator. The digital signal generator is connected to an output pin of the integrated circuit. The digital signal generator generates a digital signal. Changes in phase delay between the output signal on the output pin of the integrated circuit and the clock signal used by the integrated circuit are encoded in a duty cycle of the digital signal generated by the digital signal generator. The integrator is connected to the digital signal generator and integrates the digital signal to produce an integrated signal.

Abstract: Network elements of a synchronous digital communications system have a clock generator for generating a clock signal locked to an input signal. Such a clock generator comprises a tunable oscillator (OSC) and a phase comparator (PK) for comparing the phase of the input signal (IN) with the phase of the clock signal (CLK) and for generating a correction signal which serves to tune the oscillator (OSC). To avoid phase transients due to interruptions and disturbances in the input signal (IN), means (WD) are provided for determining an expectancy window, for deciding whether the correction signal lies within the expectancy window, and for tuning the oscillator with the correction signal if the correction signal lies within the expectancy window.

Abstract: A phase detector and a method for detecting phase difference between two high frequency signals, the phase detector is adapted to receive a reference signal REF, a high frequency signal ICOS, and a signal FD synchronized to ICOS. REF, ICOS and FD have opposite edges. The phase detector comprising of: An asynchronous phase detector circuit, for providing an asynchronous control signal CTP, for representing a time interval between a time of occurrence of an edge of REF and the time of occurrence of a corresponding edge of ICOS. A synchronous phase detector circuit, for providing an synchronous control signal TC, for representing a time interval between a time of the occurrence of the corresponding edge of ICOS and the time of occurrence of a corresponding edge of FD.A combing circuit, for receiving TC and CTP and providing an error signal ERS, representing the phase difference between REF and FD.

Abstract: An output of a flip flop (21) at a first stage is connected to a D-input of a flip flop (22) at a second stage, and an inverted-output of the flip flop (21) is connected to a D-input of a flip flop (23) at a third stage. A reference clock BCK is supplied to the D-input of the flip flop (21), and an oscillation clock OCK is inputted to each T-input of the respective flip flops (21) to (23). An XOR of the reference clock BCK and an output signal Q1 of the flip flop (21), and a logical product of an output signal Q2 of the flip flop (22) and an output signal Q3 of the flip flop (23) are used as a first comparison output PDU and a second comparison output PDD, respectively. With this arrangement, phase comparison can be achieved using a clock of any duty ratio.

Abstract: A phase detector for measuring phase differences between K input signals is provided. The phase detector includes a counter, K first registers and a first subtractor. Each first register receives the counter signal of the counter and a respective input signal for updating a counter value in response to timing information on the input signal. The first subtractor receives the counter values to generate phase difference representing values. A frequency detector is also provided. The first subtractor is substituted by a second subtractor and K second registers are included. Each second register is connected to a respective first register. Each second register receives the counter value of its first register and the same input signal as that of its first register for backing-up the counter value as a back-up counter value in response to the timing information on the input signal.

Abstract: A phase frequency detector comprises means for providing Up/Down signals in order to detect a phase difference between detector input signals, and output control means having Up/Down signal inputs for providing a detector output signal containing a measure which is proportional to said detected phase difference, and having capacitor means for providing the detector output signal whose measure depends instantaneously on said detected phase difference.This allows a loop filter which is present in a phase locked loop to have reduced averaging properties and to have a broader bandwidth resulting in a cleaner output frequency signal of a voltage controlled oscillator in the phase locked loop.