Abstract: A synchronization signal generation device includes a circuit that enables a phase difference between a synchronization signal and an input signal with intermittent edges to be arbitrarily and continuously varied. The synchronization signal generating device is of the second order phase locked loop and has a phase detector with the following elements: a circuit for generating pulses with widths corresponding to the phase difference between the input signal and the synchronization signal only upon occurrence of an edge of the input signal; a circuit for generating pulses with a constant width only upon occurrence of an edge of the input signal or the synchronization signal; a variation circuits which varies one or both of the amplitudes of the aforesaid pulses; and a combining circuit which adds or subtracts the pulses from the variation circuits to derive a phase comparison signal.

Abstract: A phase-locked loop circuit includes a voltage-controlled oscillator, a pre-scaler, a main counter, a shift register, and a phase comparison section. The oscillation frequency of the voltage-controlled oscillator is controlled on the basis of phase different information. The pre-scaler frequency-divides an oscillation frequency output from the voltage-controlled oscillator by one of frequency division ratios of 1/j (j is a positive integer) and 1/(j+1) which is selected in accordance with an external control signal. The main counter frequency-divides a frequency division output from the pre-scaler by a frequency division ratio of n (n is a positive integer). The shift register generates .alpha. (.alpha. is an integer equal to or larger than two) time series pulse strings which are synchronized with the output from the pre-scaler and have phases sequentially delayed by one period on the basis of a frequency division output from the main counter.

Abstract: A circuit for recovering a clock signal from incoming data and for retiming the incoming data comprises circuitry for generating a plurality of phased clock signals responsive to a selected frequency and clock recovery circuitry for generating a recovered clock from the plurality of phased clocks and the incoming data. The recovered clock is used to retime the data, which may be either RZ or NRZ data. To recover clock from the incoming data, the presence of a logic "1" is detected in one or more data streams and the phase of the data relative to the phased clocks is determined. Hold circuitry stores the phase information during the interval between logic "1" bits and aligns the phase information with the leading phased clock. Compare circuitry and counter circuitry detect changes in phase information to insure that a change is not merely the result of a metastable anomaly.

Abstract: A phase comparison circuit used in a phase locked loop circuit which realizes a stable phase locked loop circuit without changing the output frequency of a voltage-controlled oscillator, even if an input pulse is missing. The phase comparison circuit includes a circuit for generating a first pulse at each rising edge of an input signal, a circuit for generating a second pulse at each falling edge of the input signal, a circuit for generating a third pulse at each falling edge of a reference signal, a circuit for generating a first output signal from the first pulse and the second pulse, and a circuit for generating a second output signal from the first pulse and the third pulse. The output signals are not increased even if an input pulse is missing so that the operation of the phase locked loop circuit remains stable.

Abstract: A phase comparator circuit in which an output synchronized with the input signal may be accurately produced without producing a malfunction even in the absence of the synchronization signal, in which a detection unit 11 detects the phase information of an input signal, an error detection unit 12 detects the phase error with respect to the phase of the input signal, a switch 13 switches between the phase error from the error detecting unit and plural fixed values of the phase error +.DELTA..alpha. and -.DELTA..alpha.

Abstract: An integrated circuit utilizing a symmetric phase detection circuit for detecting a phase relationship between a reference clock signal and a delayed clock signal. The integrated circuit described herein features a control block circuit coupled to receive the reference clock signal and an enable check signal. The control block circuit generates an enable signal which provides the present invention with the ability to detect the phase difference between signals having the same frequency or signals that differ in frequency by a rational factor. The control block circuit generates the enable signal in response to the enable check signal and the reference clock signal. The enable signal, the reference clock signal, and the delayed clock signal are coupled to the phase detection circuit. In response to the enable signal, the phase detection circuit then determines the phase relationship between the reference clock signal and delayed clock signal.

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 consisting of a shift register 53 and an adder 54; and a comparator 55. In response to the output of the frequency converter 50, the phase comparator 60 outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator 60 includes: an exclusive OR element 61; an absolute phase shift measurement means 62 consisting of an adder 63 and D flip-flop arrays 64 and 65; and a D flip-flop 66 serving as a phase shift polarity decision means.

Abstract: A phase comparing circuit includes a first device for generating a detection signal in response to a multi-level signal. The detection signal represents whether or not the multi-level signal is in a given level. A second device connected to the first device is operative for generating a first control signal in response to the detection signal generated by the first device and a clock signal. The first control signal represents a time interval between a leading edge of a pulse in the detection signal and a strobe point of the clock signal which immediately follows the leading edge of the pulse in the detection signal. A third device connected to the first device is operative for generating a second control signal in response to the detection signal generated by the first device and the clock signal. The second control signal represents a time interval between the strobe point of the clock signal and a trailing edge of the pulse in the detection signal.

Abstract: A method and apparatus determine an instantaneous phase difference (207) between a reference signal (103) and a controlled signal (120). The reference signal (103) is derived by frequency dividing a first signal by a counter (106) including an output (107) having K sequential states, wherein K is an integer value equal to the frequency of the first signal (103) divided by the frequency of the desired reference signal, and wherein the output (107) changes by no more than one bit between any adjacent states of the K sequential states. The output (107) of the counter (106) is recorded (206) at a time concurrent with a first predetermined event occurring in the controlled signal (120), thereby generating a recorded count value that is free from metastability induced errors. The recorded count value is decoded (208) to produce a sequential state number S.sub.E corresponding to the first predetermined event. The instantaneous phase difference (207) is then calculated (210) from S.sub.

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 consisting of a shift register 53 and an adder 54; and a comparator 55. In response to the output of the frequency converter 50, the phase comparator 60 outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator 60 includes: an exclusive OR element 61; an absolute phase shift measurement means 62 consisting of an adder 63 and D flip-flop arrays 64 and 65; and a D flip-flop 66 serving as a phase shift polarity decision means.

Abstract: A frequency lock indicator (10) comprises a first delay (14), second delay (20), first sampler (24), second sampler (28), third sampler (32), fourth sampler (34), and lock indicator (36). The first delay (14) delays a rising edge of a frequency reference (12) which clocks the first sampler (24) on a rising edge and the third sampler (32) on a falling edge. The second delay (20) delays a rising edge of a feedback signal (18) to produce a delayed feedback signal (22) which clocks the second sampler (28) on a rising edge and the fourth sampler (34) on a falling edge. The first and third samplers sample an up-pump signal (26) and the second and fourth samplers sample a down-pump signal (30). The lock indicator (36) produces a lock indication signal (38) when the sampled up-pump signal substantially equal to the sampled down-pump signal.

Abstract: A method of monitoring abnormality of a clock driver in an electronic apparatus having a clock supply unit that supplies a clock signal and a plurality of function executing units to which the clock signal is inputted for executing prescribed functions at an identical clock, wherein each function executing unit is provided with a clock driver which, on the basis of the clock signal, oscillates internally to reproduce a clock signal, includes monitoring cut-off of an input clock signal and cut-off of an output clock signal of the clock driver, and outputting an alarm upon judging that the clock driver is abnormal in a case where the output clock signal has been cut off but the input clock signal has not.

Abstract: A device checks the skew between two clock signals among a plurality of clock signals having the same frequency. The two clock signals of each possible pair of clock signals respectively enable two successive flip-flops that are initially set at distinct states. The whole set of the flip-flops is connected in a looped shift register configuration. An alarm signal is provided by an Exclusive-OR gate receiving the outputs of two successive flip-flops of the shift register.

Abstract: A frequency monitor and error detector circuit that processes an input ac signal to be monitored, comparing the input ac signal with an internally generated reference center frequency, and outputting a "Go/No-Go" signal indicating whether the monitored ac signal frequency is within a pre-selected tolerance band or is out of tolerance. The reference frequency is provided by a highly accurate crystal oscillator. An adjustable delay circuit is provided, capable of being adjusted to produce a frequency tolerance band of from +/-0.05% to 0.1% of the center frequency. The device has three output signals which may be logic high or logic low, and are used for activating illuminated indicators or as frequency signal inputs to other equipment. The device is small in size, accurate and reliable over a wide range of frequencies.

Abstract: A phase-locked variable frequency oscillator arrangement includes a voltage controlled oscillator (VCO) which is controlled by a control signal produced by charging or discharging of a capacitor in a charge pump circuit, the charge pump circuit including current sources driven by up or down command signals from a phase detector which detects the phase of the VCO output. When the command signals are simultaneously active, a logic gate circuit supplies a reset pulse to the phase detector via a delay device which is adapted to the rise times of the current in the current sources. The delay device includes a transistor (the "annexed" transistor) which forms a switched pair with one of the transistors which form the current sources. The reset signal is produced when the current of the annexed transistor reaches a selected fraction of its normal current, after being turned on by the logic gate circuit.

Abstract: A timing acquisition circuit using a phase locked loop with programmable damping for either Type A or Type B phase detectors is described. In the damping scheme for a Type A phase detector, a resistance (R1) is simulated by adding an equivalent voltage Veff to the capacitor voltage. The equivalent voltage Veff is generated internally, so that programmable damping is made possible. In Type B phase detectors, a variable gain amplifier is used to control the effective resistance (R1) of the loop filter.

Abstract: A detector (100) determines whether an input signal (10) comprises a first signal or a second signal. A first local signal (207) is generated based on the first signal and a second local signal (307)is generated based on the second signal. A first error (211) is formed based on the first local signal and a scaled input signal (50), and a second error (311) is formed based on the second local signal and the scaled input signal. A first distance (215) between the scaled input signal and the first local signal is formed based on the first error, while a second distance (315) between the scaled input signal and the second local signal is formed based on the second error. Whether the input signal comprises the first signal or the second signal is determined by comparing (60) the first distance to the second distance.

Abstract: A signal transmitter-receiver system comprising first and second transmitter-receiver units interconnected by a signal transmission line, a first transmitter-receiver unit including a first transmission circuit for delivering a selected one of a plurality of a.c. signals each having a distinct phase difference with respect to a reference a.c. signal to the signal transmission line at each of successive predetermined communication time interval, the second transmitter-receiver unit including a second receiving circuit for identifying the phase difference of the a.c. signal or the signal transmission line with respect to the reference a.c. signal at each communication time interval, the second transmitter-receiver unit including a second transmission circuit for changing the combination of positive and negative amplitudes of the a.c.

Abstract: A signal processing circuit measures the phase difference between digitally formated reference tone and telephone line signals over a prescribed number of signal periods so as to provide to an attendant processor an average value of phase differential. The reference tone and line signals are conditioned as square wave signals, and applied to a first exclusive-OR circuit and to respective divide-by-two flip-flop circuits, which produce square wave signals having a frequency which is half the frequency of the conditioned square wave signals. The output of the first exclusive-OR circuit represents the half-cycle phase difference between the two sine waves. The full-cycle square wave signals are applied to a second exclusive-OR circuit, which produces a series of pulses, each representing a respective full-cycle phase difference between the reference and line sine waves.

Abstract: A phase/frequency comparator includes: two inputs which respectively receive first and second logic signals; a first logic gate which is at an active state during a duration equal to the phase advance of the first signal with respect to the second signal; and a second logic gate which is at an active state during a duration equal to the phase advance of said second signal with respect to the first signal. The phase/frequency comparator also includes: a first switching element operated by the active state of the second gate to prevent transmission to the first gate a state liable to switch the first gate to its active state; and a second switching element operated by the active state of the first gate to prevent transmission to the second gate a state liable to switch the second gate to its active state.

Abstract: A phase-locked-loop (PLL) with stable phase discrimination includes a charge pump with a current source and current sink to control a VCO, and a phase discriminator to compare the VCO's signal to a stable reference signal for controlling the charge pump. The phase discriminator includes a resettable D-flipflop to provide the current source control signal and a resettable D-flipflop to provide the current sink control signal. The reset signal keeps both sink and source temporarily alive to avoid a dead zone region. The reset signal is produced under the combined control of the sink and source control signals and, in addition, of the reference signal to enhance stability.

Abstract: A clocked digital signal processing system includes apparatus for unambiguously indicating the phase of an input signal relative to a reference clock signal. In particular, the disclosed apparatus reduces timing uncertainty between the reference clock, and the output signal of a phase detector representing the phase relationship between the input signal and the reference clock. A phase detector including a logic network provides plural comparison signals representing a phase relationship between the input and reference signals. The comparison signals are conveyed via first and second latch circuits, in respective groups, to a clocked downstream stage. The first and second latch circuits are clocked by different phases of the reference clock and provide outputs synchronous with the reference clock. The downstream stage responds to the reference clock for conveying output signals front the first and second latch circuits to an output at which the unambiguous indication appears.

Abstract: A zero-power sense amplifier for implementing a wide or multiple input NOR gate for receiving a product term of a group of array cells in a programmable logic device (PLD). In a sleep mode, or low power mode, the zero-power sense amplifier latches its previous state while drawing negligible power rather than returning to one particular state, such as a low state, as in previous devices, enabling recovery time to be reduced after entering an awake mode. The zero power sense amplifier further reduces recovery time upon powering up from a sleep mode by maintaining the product term voltage close to a threshold input voltage during sleep mode while still drawing negligible power.

Abstract: A phase-locked loop circuit includes a phase comparator for comparing a phase of an input signal with a reference input, connecting circuits having circuit elements arranged in signal paths to be selectively operative, output circuit for supplying an output of the phase comparing means to the connecting circuits, and control circuit located between the output circuit and phase comparator for making a signal path operative by controlling the output circuit.

Abstract: A phase locked loop (PLL) (40) simultaneously has both relatively-low power consumption and relatively-low jitter on a clock output signal. The PLL (40) includes a phase detector (41) and a phase error accumulator (42) connected to the output of the phase detector (41). The phase error accumulator (42) samples an output of the phase detector (41) at a relatively-high clock rate, but accumulates these samples and provides an output thereof to a loop filter (43) at a relatively-low clock rate. Thus the PLL (40) captures short periods of phase delay to maintain low clock output signal jitter, while at the same time, however, the loop filter (43) need only adjust its output periodically, at the relatively-low rate, thereby saving power. The phase detector (41) detects a metastable condition on a phase detector latch (60) and resolves to an up pulse or a down pulse to further reduce clock output signal jitter.

Abstract: A frequency discriminator of the horizontal synchronizing signal for a multi-mode monitor has a plurality of filter capacitors connected to horizontal synchronizing signal lines for rejecting noises of a direct current component of the horizontal synchronizing signal. The frequency discriminator also includes a plurality of phase comparator means respectively connected to the filter capacitors for comparing local oscillating frequencies set differently according to each mode with the inputted horizontal synchronizing signal to output one signal representative of the mode of the monitor.