Abstract: The present invention relates to a phase detector with no dead zone comprising two detecting means and two control logic circuits. The phase-frequency detector employs the control logic circuits to proceed with reset operation of the detecting means such that the existence of a phase difference between the reference clock signal and the feedback clock signal prevents the misdetection of the up, down signals (output signal), and the up, down signals will not be simultaneously at "1".

Abstract: To form a means preventing a logic circuit from outputting wrong data at uncontrolled, unstable state of power turn-on in a control circuit. The control circuit has two logic circuits therein and takes negative OR or negative AND of output thereof. A first input terminal is connected to an input of an inverter circuit and a second logic circuit; the output of the inverter circuit is connected to the input of the first logic circuit; a second input terminal is connected to the first logic circuit and the second logic circuit; outputs of the first logic circuit and the second logic circuit are connected to inputs of a gate circuit; the output of the gate circuit is connected to a output terminal; and the first logic circuit and the second logic circuit output the opposite level to each other, positive and negative.

Abstract: A digital phase locked loop includes a digital phase detector which provides a magnitude control signal to adjust the step size of up and down adjustments in the phase/frequency of a digitally controlled oscillator, resulting in shorter lock-in or acquisition time and smaller jitter as compared to conventional digital phase locked loop devices. In the disclosed embodiments, the digital phase detector includes multiple bit shift registers in both the up and down directions to count or measure a number of up or down minimum width pulses and provide a pulse magnitude control based on the value of the shift registers to the digitally controlled oscillator. The digitally controlled oscillator includes a charge pump and voltage controlled oscillator. In one embodiment, the charge pump provides programmable control over its output current pulses to a capacitor which controls the output frequency of the voltage controlled oscillator.

Abstract: A digital phase detector and charge pump circuit system reset circuit and method resets a digital phase detector according to the charge outputs between the charge pump circuits and a following loop filter. The sensing circuitry emulates portions of the circuitry of the digital phase detector and charge pump circuit system and minimizes deadband time. Current mirror portions of the charge pump circuit alternate between p-channel and n-channel devices to regularize output voltage levels produced by the charge pump circuit system.

Abstract: A slave clock generation system and method suitable for use with synchronous telecommunications networks generates one or more slave clocks from a selected reference clock using a direct digital synthesis technique. A multiplexer selects a reference clock from a number of available sources, each of which can be at its own spot frequency, based on a predetermined selection order. Toggle detectors monitor each of the available clock sources, and block the selection of any that are not within a specified frequency range. A local oscillator establishes short-term and long-term measurement periods; the cycles of the selected reference clock are counted over consecutive short-term measurement periods to determine the relative frequency of the selected clock with respect to the frequency of the local oscillator. The cycle counts are fed to a phase-to-clock converter, which produces a slave clock output having a frequency that varies with the relative frequency measured for the selected clock.

Abstract: A digital phase comparator comprises a first signal input (VCO) and second signal input (REF) as well as a first output (UP+) and second output (DOWN+). It is arranged so as to produce an output pulse (503, 504) to the first output and second output per each of the cycles of the periodic signals (501, 502) brought to the first signal input and second signal input. The duration of the output pulse produced to the first output is longer than the duration of the output pulse produced to the second output when the phase of the periodic signal brought to the first signal input is lagging with respect to the phase of the periodic signal brought to the second signal input. Correspondingly, the duration of the output pulse produced to the first output is shorter than the duration of the output pulse produced to the second output when the phase of the periodic signal brought to the first signal input is leading with respect to the phase of the periodic signal brought to the second signal input.

Abstract: The phase of a pulsed test signal is measured with reference to a reference signal of constant frequency by sampling the test signal at times determined by transitions in the reference signal and comparing the sampled test signal with the output of a phase accumulator clocked by the reference signal. A resulting measurement signal represents a difference in the number of transitions occurring in the sampled test signal and a reference state signal output by the phase accumulator. The measurement signal may be averaged and integrated to obtain an error signal which may then be filtered to provide a control signal for an oscillator. A digital frequency synthesizer is provided by frequency dividing the output of the oscillator by a constant multiple to obtain the test signal and integrating an offset signal in addition to the averaged measurement signal so that the operating frequency of the oscillator is offset from a nominal frequency by an amount determined by the offset signal.

Abstract: A wireless communication system (10) uses a phase detector (28) having a first pair of flip-flops (50, 56) for detecting the phase difference between an input frequency and a reference frequency. The first pair of flip-flops control current sources (66, 70) in the charge pump of the phase detector to modulate the error signal. A second pair of flip-flops (52, 58) detect when the input frequency is more than 2.pi. ahead of or behind the reference frequency. The second pair of flip-flops increment and decrement a counter (54) which in turn controls additional current sources (78-88) in the charge pump. The additional current sources extend the linear operating range of the error signal when the phase error exceeds .+-.2.pi..

Abstract: An extended frequency lock range is achieved in a PLL circuit based on sampled phase detectors by modifying a conventional PLL circuit to utilize a biased phase detector to achieve frequency acquisition of the oscillator output signal, without the need for a lock detector. A biased phase detector applies more phase error correction in one direction than in the other direction. For example, a positive biased phase detector applies more positive current, I.sub.UP, over time than negative current, I.sub.DOWN. For a positive biased phase detector, the VCO control voltage is initialized to a value below the lock-in voltage, and the positive biased phase detector will cause a steady increase in the VCO control voltage until the PLL locks, thereby causing the phase error to be approximately zero.

Abstract: A clock signal phase comparator includes a first delay unit for delaying a clock signal for a predetermined time, a first phase detector for comparing an output signal of the first delay unit and a reference clock signal and outputting a first high or low level output signal, a second delay unit for delaying for a predetermined time and outputting the reference clock signal, and a second phase detector for comparing an output signal of the second delay unit and the clock signal and outputting a second high or low level output signal. The phase comparator separately displays the phase comparison results in grades of fast, slow and locking, and when a locked phase is detected, the phase control system is partially or entirely disabled, for thereby reducing current consumption of the system.

Abstract: A method for determining the change in frequency of a clock signal (168). The method includes the step of counting the number of clock signal cycles (168) that occur over at least two time windows (162, 164). The number of clock signal cycles counted in the first time window (162) is compared to the number of clock signal cycles counted in the second time window (164).

Abstract: The invention relates to a phase detector, especially for a Phase Locked Loop of a desynchronizer of a digital transmission system for the transmission of signals of the synchronous digital hierarchy with a difference former (subtractor) connected to a comparator, to which can be conducted at the input side, via a first accumulator, a first input signal, and via a second accumulator a second input signal with the comparator being connected at the output side via a coder to a control input of the second accumulator.

Abstract: A shared path phase detector circuit for receiving a reference clock and an oscillator clock, the phase detector circuit providing an output signal for indicating a magnitude difference between a phase of the reference and oscillator clocks. The output signal is independently derived from the leading or lagging edge relationship of the reference and oscillator clocks. The output signal does not describe which signal leads, but only the width magnitude difference. The design provides a single path over which the output signal travels, without feedback, such that the circuit dependencies are greatly reduced.

Abstract: The present invention is a method and an apparatus for measuring phase differences between signals A and B using an absolute voltage value for each phase difference between .+-.180.degree.. This is accomplished using a third signal C, which is a signal having a phase approximately equal to the average phase between signals A and B. Signals C and A are subsequently amplitude limited and mixed to produce a fourth signal D, which is a signal having associated an absolute voltage value for each degree of phase difference between .+-.180.degree. for signals A and B.

Abstract: A phase detector circuit includes a first flip flop, a second flip flop, a first charge pump and a second charge pump. Outputs of the flip flops directly enable the charge pumps in response to received clocking signals. A first delay circuit delays the output signal from the first flip flop to an AND gate which combines the delayed output signal and the output signal from the second flip flop. The AND gate output is delayed in a second delay circuit to produce a delayed reset signal which resets both flip flops simultaneously and disables the charge pumps. The phase detector circuit balances the amount of charge provided to a phase locked loop near the in-phase condition to improve linearization of the phase detector.

Abstract: A phase correction circuit for correcting an antiphase component of a one-dimensional input signal is provided. The circuit contains a phase tracker, an antiphase detector, and an antiphase corrector. The phase tracker detects a decision error in the one-dimensional input signal having a phase error and outputs a phase-corrected signal in response to the decision error. The antiphase detector detects whether or not the phase-corrected signal is in antiphase and outputs a corresponding phase control signal. The antiphase corrector corrects a phase of the phase-corrected signal in accordance with the phase control signal. A method for performed by the phase correction circuit is also provided.

Abstract: An improved phase detector for detecting the difference between an information signal and a clock signal is provided. The information signal is divided into a plurality of N divided signals, the data rate of each divided signal being the data rate of the information signal divided by N. A plurality of N variable width difference pulse signals are generated each being responsive to the phase difference between a divided signal and the clock signal. One or more fixed width reference pulse signals having a width proportional to one-half clock period are also generated. A phase error signal is then provided in response to the N difference pulse signals and the one or more reference pulse signals. Preferably, N is equal to 2.sup.M, where M is a positive integer greater than or equal to one.

Abstract: A phase locked loop (PLL) circuit performs a frequency pull-in operation with a simple structure. The PLL circuit has an oscillating part which oscillates at a frequency corresponding to a control input signal and a phase comparing part which detects a phase difference between an oscillation output signal of said oscillator and an input frequency signal and produces an error signal responsive to a detection value. The PLL circuit further includes a forcible pull-in part which adds values of the error signal and a forcible pull-in signal, and provides a signal based on a result of addition as the control input signal. The forcible pull-in circuit includes a reference value generating circuit which supplies a reference value determining a unit change width of an oscillation signal of the oscillating part, and a computing part which computes a value of the forcible pull-in signal based on the reference value.

Abstract: A system for measuring a phase difference between two input signals, including a computer performing computations in the complex domain and operating on two complex signals indicative of the two input signals respectively to compute the phase difference. Alternately, the system for measuring the phase difference includes a computer operating on two input buses indicative of the two input signals respectively to generate a signal indicative of the phase difference, and wherein: A. each input bus includes at least two digital bits; B. the two input buses are indicative of the phase of each of the two input signals; C. the two input buses each has a different range of possible values and wherein the computer further includes a device for normalizing at least one of the buses so as to bring the two buses to the same range. A phase-lock loop includes the system for measuring the phase difference, a VCO and digital devices.

Abstract: A frequency shift detection circuit for detecting a frequency shift between a first signal and a second signal includes two or more delay circuits coupled to one another in series and two or more comparison logic circuits. The first delay circuit in the series receives one of the first and second signals and produces a delayed replica. Each of the other delay circuits receives the delayed replica produced by the previous delay circuit in the series and produces a further delayed replica. Thus, the signal produced by each delay circuit is delayed from the original signal by a different amount. Each comparison logic circuit receives one of the delayed replicas and receives the other one of the first and second signals, i.e., the one that is not received by the delay circuits. In response, the comparison logic circuit produces a frequency shift detection signal when it detects a phase difference between that other one of said first and second signals and the delayed replica.

Abstract: A phase-frequency detector (110) includes an output stage (300) and a control stage (200). The output stage includes a pump up switched current source (350), a pump down switched current sink (360), and a constant current source (325) that are coupled to a charge pump output node (111). The control stage generates, in response to a divided variable frequency signal (FV) (136) and a reference frequency signal (FR) (106), a pump up control signal (246) and a pump down control signal (216).

Abstract: A phase/frequency detector, such as may be used in a phase-lock loop (PLL), having reduced jitter at high frequencies by reducing or eliminating the dead zone. The detector generates two output signals (UP and DOWN) wherein one of the output signals (depending upon which input signal arrives first) has a pulse width which is equal to a time delay between the input signals. There is a dead zone associated with very small phase differences between the input signals, and the dead zone is reduced by increasing the durations of two output pulses, using several delay elements which operate on signals that are derived from the reference and feedback inputs. The circuit may be tuned to reduce the dead zone to less than one picosecond, making it particularly useful for very high speed (greater than one gigahertz) clock circuits. The phase/frequency detector uses self-resetting, complementary metal-oxide semiconducting (SRCMOS) gates.

Abstract: A phase detector produces a pulsed tri-state output signal representing a phase difference between first and second input signals. The pulse width of the output signal indicates the magnitude of the phase difference while the sign of the output signal pulses indicates whether the first input signal leads or lags the second input signal. The first and second input signals drive D and clock inputs, respectively, of a type D flip-flop, and also drive separate inputs of an XOR gate. An output of the flip-flop provides a signal input to a tristate buffer while an output of the XOR gate drives a tri-state control input of the tristate buffer. The tristate buffer produces the phase detector output signal.

Abstract: A phase-frequency detector provides a decreased blind spot near 360.degree. of phase error and a resulting increased phase error detection range. In one embodiment, the phase-frequency detector includes two latches that are set in response to the detection of positive transitions in respective input clock signals. A reset controller resets both latches when they both get set. The duration and sequence of the latch states are thereby indicative of phase errors between the input clock signals. Two edge-triggered pulse generators provide a sustained indication of a detected positive transition in the respective input clock signals. When the time duration of the sustained indications is set equal to the reset time required by the latches and reset controller, the blind spot of the phase-frequency detector is largely eliminated.

Abstract: A digital phase detector and charge pump circuit system reset circuit and method resets a digital phase detector according to the charge outputs between the charge pump circuits and a following loop filter. The sensing circuitry emulates portions of the circuitry of the digital phase detector and charge pump circuit system and minimizes deadband time. Current mirror portions of the charge pump circuit alternate between p-channel and n-channel devices to regularize output voltage levels produced by the charge pump circuit system.

Abstract: A PLL circuit is disclosed which can achieve a locked state in a short time. The PLL circuit has a phase comparator, a loop filter and a voltage controlled oscillator. The phase comparator is provided with frequency adjusting (or matching) circuits that are operative to charge the loop filter when it is detected that an oscillation frequency of the voltage controlled oscillator is lower than a frequency of an input signal, so as to increase the oscillation frequency of the voltage controlled oscillator, until it is detected that an oscillation frequency of the voltage controlled oscillator is higher than the frequency of the input signal.

Abstract: A lock detector (16) includes a set circuit (64), a reset circuit (120), and a latch circuit (80). The latch circuit (80) provides an output signal (82) in response to the temporal relationship of the first input signal (12) and the second input signal (14). The set circuit (64) initiates the transition of the latch circuit (80) to the locked state, while the reset circuit (120) initiates the transition of the latch circuit (80) to the not-locked state.

Abstract: A phase lock loop circuit includes a phase detector for receiving a reference clock and a feedback clock, a charge pump for receiving a Down pulse and an Up pulse from the phase detector, a loop filter for being charged and discharged by the output from the charge pump, and a voltage controlled oscillator for outputting a frequency signal according to the output voltage of the loop filter, the phase detector including a power cut input terminal, and when a power cut signal is input to the power cut input terminal, a Down pulse and an Up pulse output from the phase detector are forcibly changed to logic "L" level and logic "H" level, respectively, which reduces the power consumption in the phase locked loop circuit.

Abstract: A jitter detection method and apparatus for informing an adaptive equalizer that the correlated jitter of transmitted data exceeds a predetermined jitter value. In one embodiment of the present invention, a jitter detection circuit receives transmitted data symbol pulses and clock signal pulses. The jitter detection circuit then compares a specified edge (e.g., the falling edge) of an incoming data pulse with the corresponding specified edge (e.g., the falling edge) of a clock signal pulse to determine if an original phase error between the incoming data pulse and the clock pulse exists. Similarly, the jitter detection circuit detect subsequent phase errors between subsequent data pulses and subsequent clock pulses. The original detected phase error will then be compared against subsequently detected phase errors. Based on this comparison of the phase errors, the jitter detection circuit then informs the adaptive equalizer of the degree of phase and amplitude compensation that it needs to provide.

Abstract: A circuit configuration for measuring a phase difference between a reference signal and a clock signal includes a first shift register being clocked by the clock signal and having an input receiving the reference signal. A digital differentiator is connected downstream of the first shift register and has an output. A counter has an input receiving the clock signal and an output outputting a multidigit binary word. A buffer memory is connected to the counter and to the digital differentiator for storing the binary word at the output of the counter in memory upon an appearance of a corresponding output signal of the digital differentiator. The buffer memory has an output forming most significant bits of an output binary word. A second shift register is inversely clocked by the clock signal and has an input receiving the reference signal and an output. An analog differentiator has an input connected to the output of the digital differentiator and an output.

Abstract: A phase detector provides a digital output having a linear relationship to the phase difference between a reference signal and an applied input signal. The phase detector counts the number of cycles of the reference signal within a time interval determined by the difference in arrival times of corresponding amplitude transitions of the reference signal and the input signal. A digital output representing the number of counted cycles is produced. A dither generator adds random time variation to the time interval over which the reference signal cycles are counted to introduce a corresponding random variation in the digital output.

Abstract: A frequency synthesizer SYNT intended to supply an output signal Sout having an output frequency which depends on the average frequency, referred to as symbol frequency, of an input signal Sin beset with a strong phase noise. This synthesizer SYNT includes: a phase/frequency detector PHD comparing the symbol frequency with a predetermined fraction of the output frequency, and supplying a control signal; a low-pass filter LPF filtering the control signal; and an oscillator VCO supplying a signal Sout with a frequency which is adjusted by the filtered control signal Cs. Reference pulses having the symbol frequency are generated within the synthesizer SYNT by means of pulses from an internal clock, which pulses are validated by active states of the input signal Sin.

Abstract: A phase locked loop comprises a voltage controlled oscillator, a 1/n frequency demultiplier, a phase comparator, and a modulation circuit. The phase comparator is supplied with a first signal which varies according to a reference clock signal and a second signal which varies according to a feedback signal supplied from the 1/n frequency demultiplier, executes phase comparison between the two signals, and controls the oscillation frequency of the voltage controlled oscillator by varying a control voltage by outputting an up-control signal or a down-control signal depending on phase difference between the signals. The modulation circuit generates the first signal by periodically modulating the reference clock signal with a shift width which is larger than the dead zone width of the phase comparator, and supplies the phase comparator with the first signal.

Abstract: A phase detector responsive to a first signal having a carrier frequency and a second signal close to the carrier frequency, including a carrier suppression circuit which produces a carrier suppressed signal from the first and second signals, and a mixer responsive to the carrier suppressed signal and the carrier frequency to produce an output signal corresponding to the phase difference between the first and second signals.

Abstract: Magnification/reduction is achieved by a single FIR filter under the control of a Digital Differential Analyzer (DDA) as would be used to simulate a perfectly straight line on a two-dimensional raster. The single FIR filter combines the processes of interpolation, filter, and decimation. The DDA is programmed with the desired magnification/reduction ratio and provides signals that control shifting of input samples into the FIR filter and selection of FIR coefficients for the FIR filter.

Abstract: A phase meter and method of providing a voltage indicative of a phase difference between a reference signal and an input signal in which the amplitudes of the two signals are made approximately the same to cancel potential phase errors caused by different amplitudes, and the two signals are provided to two matched comparators, one receiving the input signal and the other receiving the reference signal. The two matched comparators are connected together so as to provide an output logic signal in accordance with a prescribed, unconventional, truth table. The output logic signal is a pulse whose duration is proportional to the phase difference. The output logic signal is converted to a voltage indicative of the phase difference between the reference signal and the input signal. The phase meter is relatively simple to make and a preferred embodiment measures phase shift directly with a 10 mV/degree output at up to 10 MHz.

Abstract: A quadrature phase detector includes a first load and a current source circuit. A first differential circuit and a second differential circuit coupled to the first load. In response to a first input signal, a first switching circuit couples the current source to the first differential circuit to form a first differential amplifier. The first switching circuit also couples the current source to the second differential circuit to form a second differential amplifier. The second differential amplifier is cross-coupled to the first differential amplifier. The first and second differential amplifiers are coupled to receive a differential second input signal, wherein the first and second input signals have a substantially different signal swing. A second switching circuit couples the current source to a second load in response to the complement of the first input signal.

Abstract: A phase lock loop includes a charge pump, a voltage controlled oscillator (VCO), and a phase frequency detector. The phase frequency detector has a dynamic logic structure. The phase frequency detector generates up and down signals for directing the charge pump to provide a voltage signal to the VCO to vary the frequency of the VCO clock. The difference between the up and down signals is indicative of the phase difference between the reference clock signal and the VCO clock. The phase frequency detector includes up and down signal generators for generating the up and down signals, respectively. The up signal generator includes a first p field effect transistor (FET) having a gate for receiving a set signal, a second p FET having a source coupled to the drain of the first p FET and having a gate for receiving a reference clock signal. A first n FET has a source coupled to the drain of the second p FET and has a gate for receiving the set signal.

Abstract: A phase comparator has a first comparing circuit and a second comparing circuit. The first comparing circuit produces a first output pulse having a duration equal to a phase lead of a first input signal with respect to a phase of a second input signal. The first phase comparator also produces a second output pulse equal in duration to a phase lag of the first input signal with respect to the phase of the second input signal. The second comparing circuit produces a third pulse equal in duration to a phase lead of a third input signal with respect to a phase of a fourth input signal. The second comparator also produces a fourth output pulse equal in duration to a phase lag of the third input signal with respect to the phase of the fourth input signal.

Abstract: A phase detector biased in a manner to alleviate the mismatch between the biasing current sources and the phase detector core bias currents. The bias setting resistors are coupled together at a common node that forms the negative input of a differential feedback amplifier. The positive input to the amplifier is referenced to a reference voltage, and the output of the amplifier controls the biasing current sources. The feedback amplifier forces the average voltage at the current source outputs to approximately match the reference voltage applied to its positive input. Thus the average bias current from the bias current sources is forced to track the average bias currents of the phase detector core.

Abstract: A phase detector for a phase-locked loop ("PLL") circuit under control of a local oscillating clock ("LOSC") signal and a method of operation thereof.

Abstract: A digital frequency synthesizer includes a digital-to-analog (1), a low pass filter (2), and a controllable oscillator (3), where the oscillator output is the synthesizer output. K number of RS flip-flops (101-108) produce error signals which are coupled to the DAC. The S inputs of the flip-flops come from a phase-splitter (8) which is driven by the more-significant bits unit of an accumulator (5) which is clocked by a reference frequency. The R inputs of the same flip-flops get input pulses from a pulse distributor (9) which is driven by the synthesizer output. The frequency resolution can be increased by adding a less-significant bits accumulator (15), coupled to the more-significant bits unit.

Abstract: An integrated circuit utilizing a symmetric phase detection circuit for detecting a phase relationship between a reference clock signal and a delayed clock signal. The integrated circuit described herein features a control block circuit coupled to receive the reference clock signal and an enable check signal. The control block circuit generates an enable signal which provides the present invention with the ability to detect the phase difference between signals having the same frequency or signals that differ in frequency by a rational factor. The control block circuit generates the enable signal in response to the enable check signal and the reference clock signal. The enable signal, the reference clock signal, and the delayed clock signal are coupled to the phase detection circuit. In response to the enable signal, the phase detection circuit then determines the phase relationship between the reference clock signal and delayed clock signal.

Abstract: Disclosed is a phase detection apparatus for accurately calculating the phase of an input digital complex baseband signal point independently of its amplitude value, without requiring any large-capacity arc-tangent table memory and within a practical calculation time. This phase detection apparatus rotates the phase of the input signal point in a clockwise direction and determines whether the rotated signal point agrees with a reference phase point. If the rotated signal point leads the reference phase point, the signal point is further rotated by an angle onehalf of the predetermined angle. If the rotated signal point lags behind the reference phase point, the signal point before the rotation is rotated by a half angle of the predetermined angle. Rotational angles, 180.degree., 90.degree., 45.degree., . . . , for the individual rotations are stored in a table.

Abstract: The present invention discloses a novel latching phase detector which eliminates prior art errors in phase detection due to DC and low frequency offsets present in reference and input signals. The invention also eliminates prior art errors in phase detection due to timing skews caused by unequal reference and input signal delay paths. The invention further eliminates the effects of logic element metastability. The invention comprises a reference signal differentiator and an input signal differentiator. Each differentiator has a corner frequency that is easily adjusted to block DC and low frequency offsets. The corner frequency can be adjusted to result in an n.pi./2 phase detector where 1.ltoreq.n.ltoreq.4. The invention also comprises an output latch that presents a delay path to the reference signal that is equal to the delay path presented to the input signal.

Abstract: In the present embodiment, digital phase detection of digital telecommunications signals is based on heterodyning. The frequency of two signals are scaled to different nominal values that are separated by a typically small but finite difference. The two frequencies are then mixed to generate a finite beat frequency. In mixing, phase is preserved and the finite beat frequency phase is in one-to-one correspondence with the signal phase. Phase detection is performed indirectly at the lower finite beat frequency with high resolution and greater ease than direct phase detection.

Abstract: A sequential phase-frequency detector circuit using precharged logic and a minimum number of transistors is suitable for use in a delay locked loop because of insensitivity to a stuck delay line output signal. The detector receives standard REFERENCE and LOCAL input signals and provides UP and DOWN output signals for control of a charge pump. In one embodiment, the detector includes a pulse generator for isolating the reset of the UP output signal from a stuck delay line output. This feature permits the UP output to be turned ON while the LOCAL input is stuck at a high level. The circuit exhibits improved gain at phase differences of less than 20 pico-seconds, resulting in reduced phase jitter. The isolating feature minimizes frequency acquisition time in applications in which the frequency of the REFERENCE signal is sometimes substantially reduced, such as during an Energy-Star.TM. power-conserving or Slow modes, which typically causes the delay line output to become stuck.

Abstract: A phase detector is disclosed that eliminates frequency ripple in a phase-locked loop circuit. The detector includes first and second circuits for providing UP and DOWN signals respectively. It also includes a delay element for setting the duration of the DOWN signal so as to eliminate phase jitter and static phase offset.

Abstract: A method and system are provided for detecting and measuring a phase difference, linearly over a range of 360.degree., between the output signals from a primary stratum clock module (100) and a standby stratum clock module (120) in a telecommunications system, calculating the amount of time needed to delay the standby clock signal (.o slashed.2) enough to cancel the phase difference, and controlling a digital delay line (132) to shift the phase of the standby clock signal (.o slashed.2) accordingly and thereby cancel the phase difference. Both the frequency and phase alignments of the two clocks are thus maintained. Therefore, when the system or user switches operations from the primary stratum clock module (100) to the standby stratum clock module (120), phase-related transients are not generated, which results in a significant increase in the overall performance and reliability of the system.

Abstract: There is disclosed an integrated circuit including a phase detection circuit having an exclusive gate having first and second gate inputs for receiving first and second gate input signals. The exclusive gate provides at an output, a gate output signal that is the exclusive combination of the first and second gate input signals. A first switched resistance is coupled between a first voltage source and a common node. A second switched resistance, coupled between a second voltage source and the common node, receives the gate output signal of the exclusive gate to control the effective resistance thereof. The first and second resistances develop a signal at the common node. A comparator has a first input coupled to the common node and a second input coupled to a threshold value.