Abstract: A display device including a display unit which has a plurality of pixels and a plurality of driving lines for driving the plurality of pixels; a driving circuit which drives the plurality of pixels through the plurality of driving lines; and a control unit which adjusts a driving capability of the driving circuit according to the number of simultaneous driving lines of the driving circuit.

Abstract: Provided is an inductor structure. In embodiments of the invention, the inductor structure includes a first laminated stack. The first laminated stack includes layers of an insulating material alternating with layers of a first magnetic material. The inductor structure includes a laminated second stack formed on the first laminated stack. The second laminated stack includes layers of the insulating material alternating with layers of a second magnetic material. The second magnetic material has a greater permeability than does the first magnetic material.

Abstract: Radio frequency switch circuitry is disclosed having first and second port terminals, a switch branch having first and second branch terminals, and a branch control terminal, wherein the switch branch is configured to pass an RF signal between the first and second branch terminals in an on-state and block the RF signal from passing between the first and second branch terminals in an off-state in response to a control signal that is coupled with the RF signal and received at the first port terminal. Control signal decoupling circuitry has a control signal input terminal coupled to the first port terminal to receive the control signal coupled to the RF signal and a control signal output terminal coupled to the branch control terminal, wherein the control signal decoupling circuitry is configured to decouple the control signal from the RF signal and provide the control signal to the branch control terminal.

Abstract: A coil that includes compensation.

Abstract: An amplifying unit includes a converter and a feedback mechanism. The converter has a supply input coupled to a supply node. The converter further has an input terminal configured to receive an input signal. The converter is configured to amplify the input signal from the input terminal to generate an output signal. The feedback mechanism is coupled to the input terminal of the converter and is configured to cause a constant bias current to flow from the supply node through the converter based on the input signal.

Abstract: An amplifier system includes a main amplifier, a cross-over current detector and a controller. The main amplifier includes at least a first driving transistor and a second driving transistor serving as a differential pair, wherein the first driving transistor and the second driving transistor are arranged to receive a first input signal and a second input signal, respectively. The cross-over current detector is coupled to the main amplifier, and is arranged for detecting a cross-over current of the main amplifier, wherein the cross-over current of the main amplifier is an overlapped current from the differential pair. The controller is coupled to the main amplifier and the cross-over current detector, and is arranged for generating a control signal to control a gain of the main amplifier according to an output of the main amplifier and the cross-over current of the main amplifier.

Abstract: Certain aspects of the present disclosure generally relate to using cross-coupled transistors for source degeneration of an amplification stage. For example, the amplification stage generally includes a differential amplifier comprising transistors, cross-coupled transistors coupled to the differential amplifier, and an impedance coupled between drains of the cross-coupled transistors. In certain aspects, the differential amplifier comprises a push-pull amplifier, and the transistors of the push-pull amplifier comprise cascode-connected transistors.

Abstract: An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals.

Abstract: An apparatus and method and system therefor relates generally to decision threshold control. In such an apparatus, an ac-coupler circuit is configured as a high-pass circuit path for a first frequency range. A buffer amplifier circuit is coupled in parallel with the ac-coupler circuit. The buffer amplifier circuit is configured as a low-pass circuit path for a second frequency range. An offset injection circuit is coupled to both the ac-coupler circuit and the buffer amplifier circuit and configured to inject an offset.

Abstract: A semiconductor device is provided. Gates of first PMOS and NMOS transistors are coupled together for receiving an input signal. Gates of second PMOS and NMOS transistors are coupled together. Gates of third PMOS and NMOS transistors are coupled together. Gates of fourth PMOS and NMOS transistors are coupled together. Drains of fourth PMOS and NMOS transistors are coupled together for providing an output signal. When the first, second, third and fourth NMOS transistors are connected in parallel and the first, second, third and fourth PMOS transistors are connected in parallel, the output signal is provided according to the input signal and a first logic function. When the first and second NMOS transistors are connected in serial and the first and second PMOS transistors are connected in serial, the output signal is provided according to the input signal and a second logic function.

Abstract: A display apparatus includes a timing controller, a data driver and a display panel. The data driver generates a positive polarity data voltage and a negative polarity data voltage based on image data compensated by the timing controller. The display panel includes a first pixel driven based on the positive polarity voltage and a second pixel driven based on the negative polarity voltage. The display panel receives a storage voltage applied to the first pixel and the second pixel. The timing controller compensates the image data when a variation on a level of the storage voltage occurs. The compensation shifts a level of the first data voltage from a first normal level to a first compensation level in a direction, and shifts a level of the second data voltage from a second normal level to a second compensation level in the same direction.

Abstract: Front-end integrated circuit for wireless local area network WLAN applications. In some embodiments, a semiconductor die can include a semiconductor substrate, and a power amplifier implemented on the semiconductor substrate and configured for WLAN transmit operation associated with a frequency range. The semiconductor die can further include a low-noise amplifier (LNA) implemented on the semiconductor substrate and configured for WLAN receive operation associated with the frequency range. The semiconductor die can further include a transmit/receive switch implemented on the semiconductor substrate and configured to facilitate the transmit and receive operations.

Abstract: A circuit includes a differential input pair stage including bipolar transistors and configured to receive an RF input signal; a cascode stage coupled between the differential input pair stage and an output node, the cascode stage including bipolar transistors; and a current source including a first bipolar transistor coupled to a first output of the differential input pair stage and a second bipolar transistor coupled to a second output of the differential input pair stage.

Abstract: An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals.

Abstract: In the example of a voltage regulator outputting a negative voltage, its feedback voltage will also be negative. The feedback voltage is typically created using a resistor divider. A controller IC is powered by only a positive voltage and receives the negative feedback voltage at a high impedance input of an inverting amplifier. Therefore, the inverting amplifier does not load the resistor divider, resulting in an accurate regulated output voltage. The inverting amplifier converts the negative feedback voltage to a positive feedback voltage for further processing by the controller IC. An error amplifier and a power good monitor receive both the original feedback voltage and the inverted feedback voltage and use whichever feedback voltage is the more positive one. Therefore, the controller IC may be used in voltage regulators that generate either negative or positive output voltages.

Abstract: A differential circuit includes a first constant current circuit, a second constant current circuit having the same constant current value as the first constant current circuit, a current mirror including a first transistor having a current sink terminal connected to the first constant current circuit, a current drain terminal to which a first input voltage is applied, and a gate short-circuited to the current sink terminal, and a second transistor having a gate connected to the current sink terminal of the first transistor and a current drain terminal to which a second input voltage is applied, and a current output terminal connected to a connection node between a part in which a current based on an output current of the current mirror flows and the second constant current circuit.

Abstract: A buffer circuit may include an amplification circuit, a main load circuit, and a sub-load circuit. The amplification circuit and the main load circuit may generate first and second output signals by amplifying first and second input signals. The sub-load circuit may compensate mismatch between rising timing and falling timing of the first output signal based on the first input signal.

Abstract: A power amplifier circuit includes an input that receives a first input signal having a first phase and a second input signal having a second phase, a first transistor that includes a source that is supplied with a first voltage, and a gate that receives the first input signal, a second transistor that includes a source that is supplied with the first voltage, and a gate that receives the second input signal, a first neutralizing circuit that neutralizes a parasitic element, a second neutralizing circuit that neutralizes a parasitic element, N third transistors, N being an integer equal to or higher that 1, N fourth transistors, and an output that is connected between a drain of the N-th third transistor and a drain of the N-th fourth transistor and outputs a first output signal having a third phase and a second output signal having a fourth phase.

Abstract: An inductive device is formed in a circuit structure that includes alternating conductive and insulating layers. The device includes, in a plurality of the conductive layers, traces forming a respective pair of interleaved loops and at least one interconnect segment in each of the plurality of the conductive layers. In each layer among the plurality of the conductive layers, at least one loop in the respective pair is closed by jumpers to an interconnect segment formed in another layer above or below the layer.

Abstract: A sort-and-delay time-to-digital converter (TDC) is provided, made up of a plurality of serially connected sort-and-delay circuits. Each sort-and-delay circuit accepts a time-differential input signal with a first edge separated from a second edge by an input duration of time. The first and second edges are selectively routed as a time-differential output signal with a delayed edge separated from a trailing edge by an output duration of time representing a compression of the input duration of time. Each sort-and-delay circuit also supplies a TDC coded bit (e.g., Gray code) indicating the order in which the first and second edges are routed as leading and trailing edges. The TDC outputs a digital output signal representing the initial input duration of time associated with the initial time-differential input signal received by the initial sort-and-delay circuit. Associated TDC, sort-and-delay, and time amplification methods are also provided.

Abstract: A method for pre-amplifying an input voltage signal to a pre-amplified voltage signal. The method includes receiving the input voltage signal; obtaining a high-pass filtered voltage signal by applying a high-pass filter to the input voltage signal; processing the high-pass filtered voltage signal to a current signal that corresponds to the high-pass filtered voltage signal; transmitting the current signal through a differential transmission line; converting the transmitted current signal to a converted voltage signal that corresponds to the high-pass filtered voltage signal; and outputting the converted voltage signal as the pre-amplified voltage signal. An integrated circuit chip implementing the method is also disclosed.

Abstract: The present disclosure relates to a liquid crystal panel and the driving circuit. The liquid crystal panel includes a plurality of source driving circuits and a plurality of sub-pixel rows extending along a row direction. Each of the sub-pixel rows includes a plurality of sub-pixels of different colors and the sub-pixels are arranged periodically along the row direction. Within one scanning frame, polarity of driving voltage of at least one sub-pixel within the arranging period is opposite to that of other sub-pixels. Each of the source driving circuit includes at least two output ends respectively connecting to at least two sub-pixels having the same polarity of driving voltage within the same scanning frame to provide the driving voltage of the same polarity to the at least two sub-pixels. In this way, the power consumption of the source driving circuit may be reduced.

Abstract: There are provided a touch sensing device and a touchscreen device. The touch sensing device includes: a driving circuit applying a driving signal having a predetermined first period to a node capacitor; a buffer circuit converting capacitance of the node capacitor into a voltage signal; a buffer capacitor being charged and discharged depending on an output voltage from the buffer circuit; and an integration circuit integrating voltages charged in the buffer capacitor, wherein, in a normal touch mode, the buffer circuit integrates capacitance of the node capacitor to generate the voltage signal, and, in a proximity touch mode, the buffer circuit generates the voltage signal by following the voltages charged in the node capacitor.

Abstract: An analog amplifier is provided. The analog variable amplifier includes a first amplifier stage configured to amplify a bias current to output a first output voltage and a second output voltage that respectively depend on a magnitude of a first input voltage and a second input voltage, a second amplifier stage configured to receive the first output voltage and the second output voltage of the first amplifier stage as inputs and to amplify the received first output voltage and the second output voltage, and at least one auxiliary bias current source coupled to an electrical connection between the first amplifier stage and the second amplifier stage through which the second amplifier stage receives the first output voltage, and coupled to an electrical connection between the first amplifier stage and the second amplifier stage through which the second amplifier stage receives the second output voltage.

Abstract: A low-noise amplifier comprises first and second input ports respectively configured to receive a positive and negative input voltages; first and second resonance circuit, first and second transistor; wherein a first voltage output port of the first resonance circuit is connected to the second transistor, and a second voltage output port of the second resonance circuit is connected to the first transistor, the first and second voltage output ports are crossed coupled to a second node of both the first transistor and the second transistor via a first and second capacitor respectively; the second node of the second transistor is connected to both the second input port via a third capacitor and a third node of the first transistor, and the second node of the first transistor is connected to both the first input port via a fourth capacitor and a third node of the second transistor.

Abstract: A differential input circuit (FIG. 3A) is disclosed. The circuit includes a first input terminal (drain of 310) and a second input terminal (drain of 312). A first input transistor (310) has a first control terminal and has a current path coupled to the first input terminal. A second input transistor (312) has a second control terminal and has a current path coupled to the second input terminal. A third transistor (306) has a third control terminal and has a current path between a first differential input terminal (Vin+) and the first control terminal. A fourth transistor (308) has a fourth control terminal and has a current path between a second differential input terminal (Vin?) and the second control terminal.

Abstract: A negative impedance circuit including: a first and a second bipolar transistors having a common collector, a base of the first transistor being connected to an emitter of the second transistor; a third and a fourth bipolar transistors having a common collector, a base of the third transistor being connected with an emitter of the fourth transistor; and at least one first impedance formed of one or of a plurality of passive components coupling the common collector of the first and second transistors to the common collector of the third and fourth transistors, a base of the second transistor being coupled to the collector of the third and fourth transistors and a base of the fourth transistor being coupled to the collector of the first and second transistors.

Abstract: A data transfer device compresses and transfers data according to a priority given to a CPU-constraint process imposing a constraint to a compression processing speed over a NW bandwidth-constraint process imposing a constraint to a transfer processing speed. It is necessary to select a compression algorithm, applied to the CPU-constraint process or the NW bandwidth-constraint process, based on a NW bandwidth, compressibility, and compression processing speed maximizing an effective throughput. When the amount of compressed data held in a temporary hold part is smaller than the predetermined value, the compressed data of the NW bandwidth-constraint process is stored in a temporary hold part. When the amount of compressed data held by the temporary hold part is larger than the predetermined value, the compressed data of the CPU-constraint process is stored in the temporary hold part. Thus, it is possible to improve an effective throughput by effectively using NW bandwidths.

Abstract: A data communications receiver including a receiver coil, a first amplification stage coupled to the receiver coil, the first amplification circuitry to differentially amplify at least part of signal received by the receiver coil relative to a threshold, a second amplification stage coupled to receive the differentially amplified signal from the first amplification stage, the second amplification stage comprising a current mirror, and hysteretic level shifting circuitry to shift a level of part of the signal received by the receiver coil, the threshold or part of the signal received by the receiver coil and the threshold such that, in response to the at least part of the signal received by the receiver coil having crossed the threshold, a threshold crossing in the other direction is delayed.

Abstract: Methods and apparatus are described for a differential active inductor load for inductive peaking in which cross-coupled capacitive elements are used to cancel out, or at least reduce, the limiting effect of the gate-to-drain capacitance (Cgd) of transistors in the active inductor load. The cross-coupled capacitive elements extend the range over which the active inductor load behaves inductively and increase the quality factor (Q) of each active inductor. Therefore, the achievable inductive peaking of the load is significantly increased, which leads to providing larger signal swing across the load for a given power or, alternatively, lower power for a given signal swing.

Abstract: Disclosed here is an apparatus that comprises an amplifier having first and second input nodes, first and second resistors, a first electrostatic discharge protection circuit coupled between the first input node and the first resistor, and a second electrostatic discharge protection circuit coupled between the second input node and the second resistor.

Abstract: Systems and methods for interference cancellation in a receiver of wireless signals include receiving a signal comprising an aggressor and a desired signal. The received signal is amplified in a low noise amplifier (LNA) to generate an amplified received signal. The aggressor is extracted from the received signal in a feed-forward path between an input of the LNA and an output of the LNA, to generate an extracted aggressor and the extracted aggressor is subtracted from the amplified received signal to provide the desired signal. An amplify and rotate block in the feed-forward path is used to align a phase of the aggressor to a phase of the amplified received signal in order to enable the subtraction.

Abstract: When the offsets of the first and second differential units have polarities different from each other, the first and second differential units are both set to a normal connection state, i.e., a state in which the input voltage is supplied to the first input terminal of each of the first and second differential units and the output voltage is supplied to the second input terminal of each of the first and second differential units. When the offsets of the first and second differential units have the same polarity, on the other hand, the first differential unit is set to the above normal connection state and the second differential unit is set to a chopping connection state in which the output voltage is supplied to the first input terminal and the input voltage is supplied to the second input terminal.

Abstract: A data processing apparatus includes a compressor and an output interface. The compressor generates a compressed display data by compressing a display data according to a compression algorithm. The output interface appends first indication information in a first output bitstream, appends second indication information in a second output bitstream, and outputs the first output bitstream and the second output bitstream via a display interface. The first output bitstream is derived from the compressed display data. The first indication information is set in response to the compression algorithm employed by the compressor. The first indication information is different from the second indication information. The display interface is arranged for coupling to a driver circuit.

Abstract: An envelope tracking system is employed in a power amplification module that supports multiple frequency bands. The power amplification module includes multiple power amplification circuits, each of which includes: a first transformer to which a radio frequency signal is input; a differential amplification circuit, in which a first radio frequency signal output from transformer is input to a control electrode and in which a second radio frequency signal output from the transformer is input to a control electrode, the differential amplification circuit outputting an amplified signal obtained by amplifying a difference between the first and second radio frequency signals; and a second transformer for supplying, to the first differential amplification circuit, power-supply voltage varying according to the amplitude of the radio frequency signal and to which the first amplified signal is input.

Abstract: An analog signal processing circuit of a microphone includes a bias circuit including a first sub-circuit which receives a signal from the microphone to output a first signal and a second sub-circuit which receives a reference voltage to output a second signal. A fully differential circuit receives the first signal and the second signal to output a fully differential signal. Each of the first sub-circuit and the second sub-circuit includes a bias sub-circuit to apply a bias voltage.

Abstract: There is provided a switching circuit for an active mixer. The switching circuit comprises a first pair of parallel switching devices and a second pair of parallel switching devices. The first and second pairs of parallel switching devices are arranged in a stacked configuration between an input node at which an input current comprising a first input frequency signal is received and a pair of differential output nodes. The first pair of switching devices are controlled by a second input frequency signal. The second pair of switching devices are controlled by a phase-shifted counterpart of the second input frequency signal. A common node between the first switching devices of the first and second pairs of switching devices is electrically coupled to a common node between the second switching devices of the first and second pairs of switching devices.

Abstract: A method involving a communication device, which comprises sending a request to a communication device; receiving a response from the communication device over a local communication path; deriving a received data set from said response; determining at least one data set that had been previously transmitted to the communication device over a wireless portion of a second communication path different from the local communication path; and validating the response based on the received data set and the at least one previously transmitted data set.

Abstract: An apparatus is disclosed for providing a common mode voltage to the inputs of a first differential amplifier which outputs the difference between two signals. A second differential amplifier receives the output of the first differential amplifier, and the output of the second differential amplifier is fed back to the inputs of the first differential amplifier as a common mode voltage. Since both inputs of the first differential amplifier receive the fed back common mode voltage, the first differential amplifier still outputs only the difference in the two signals, but the presence of the common mode voltage allows the first differential amplifier to operate with lower noise if the voltage levels of the inputs to the first differential amplifier vary. The second differential amplifier may be of significantly lower quality and cost than the first differential amplifier, without affecting the performance of the first differential amplifier.

Abstract: A differential amplifier is disclosed. The differential amplifier includes: a pair of input terminals externally receiving an input signal; a first differential pair including a first transistor, a second transistor, a first resistor, and a second resistor and configured to generate a first signal; a second differential pair including a third transistor, a fourth transistor, a third resistor, and a fourth resistor and configured to generate a second signal; a current source connected to the first, second, third, and fourth resistors and configured to provide a current to the first and second differential pairs; a pair of level shifters configured to generate a shifted signal from the input signal; and a pair of output terminals externally outputting an output signal containing the first and second signals, wherein the first and second transistors receive the input signal and the third and fourth transistors receive the shifted signal.

Abstract: A system for amplifying a signal with active power management according to one embodiment includes a first digital to analog converter (DAC) circuit configured to provide a modulated carrier signal; a amplifier circuit coupled to the first DAC, where the amplifier circuit is configured to amplify the modulated carrier signal; an output stage circuit coupled to the amplifier circuit, where the output stage circuit is configured to provide the amplified signal to a network; a second DAC circuit configured to provide a full wave rectified envelope of the modulated carrier signal; and a switching regulator circuit including a voltage reference input coupled to the second DAC circuit, where the switching regulator circuit is configured to provide a supply voltage to the output stage circuit and the supply voltage is modulated in response to the envelope received at the voltage reference input.

Abstract: A phase interpolator circuit includes differential pairs of transistors, current source circuits, and a transimpedance amplifier circuit. Each of the current source circuits is coupled to provide current through one of the differential pairs of transistors. The transimpedance amplifier circuit converts the current through the differential pairs of transistors into a voltage signal.

Abstract: A method for optimizing migration efficiency of a data file over network is provided. Specifically, a total time of compression time of the data file, transfer time of the data file over the network, and decompression time of the data file, is minimized by adaptively selecting compression methods to compress each data block of the data file. For selecting a compression method for a data block, information entropy of the data block is analyzed, and a real status of computing and system resources is considered. Further, trade-off among the resource usage, compassion speed and compression ratio is made to calculate an optimized transmission solution over the network for each data block of the data file.

Abstract: A primary differential input pair of transistors and a secondary differential input pair of transistors are capable of operating in parallel to provide load current. A level-shifting pre-stage to the secondary differential pair downwardly level-shifts rail-to-rail input signals. Doing so prevents the secondary differential pair from entering cut-off. A tail current shunt device provides tail current to the secondary differential pair as the primary differential pair approaches cut-off when a common-mode component of the input signals approaches the positive voltage rail. Consequently, the sum of currents through first differential input transistors associated with the primary and secondary differential input pairs remains constant to the first load. Likewise, the sum of currents through the second differential input transistors associated with the primary and secondary differential input pairs remains constant to the second load.

Abstract: A circuit module for a silicon condenser microphone of the present disclosure includes a transducer, a charge pump, an isolator, a first amplifier, a second amplifier, a reaction circuit, a first bias circuit, and a second bias circuit. The charge pump electrically connects to an input port of the transducer, and an output port of the transducer electrically connects to an input port of the first amplifier via the isolator. An output port of the first amplifier electrically connects to an input port of the second amplifier. The reaction circuit is arranged between the output port of the first amplifier and the input port of the transducer. The isolator isolates the direct-current components of the first electrical signal, and therefore, the oscillations of the direct-current components will not affect the performance of the first amplifier.

Abstract: An amplifier includes a pair of transistors connected in a differential stage, and a bias current source connected to a common node of the differential stage. A slew-rate compensation circuit is configured to derive from the common node a dynamic compensation current during a phase in which the voltage of the common node varies.

Abstract: A differential amplifier having a tunable filter is disclosed. The tunable filter may attenuate some common-mode signals while not affecting amplification of differential signals. The tunable filter may include a resonant circuit to select frequencies of common-mode signals to attenuate. The resonant circuit may include a variable capacitor series-coupled to an inductor. A resonant frequency of the resonant circuit may be determined, in part, by a capacitance value of the variable capacitor.

Abstract: A signal modulation circuit includes a feedback circuit configured to generate the feedback signal for feeding back a drive signal from a driver circuit to an input signal. The feedback circuit includes at least first and second resistors connected together in series, the second resistor having a higher resistance value than that of the first resistor. One end of the first resistor is connected to a subtracter, and one end of the second resistor is connected to the driver circuit. A first line distance as the line length between one end of the first resistor and the subtracter and a second line distance as the line length between one end of the second resistor and the driver circuit are set shorter than a third line distance as the line length between the other end of the first resistor and the other end of the second resistor.

Abstract: Provided is a low noise amplifier. The low noise amplifier includes an input transistor receiving and amplifying a signal, an output transistor amplifying the signal amplified by the input transistor, and an inverting unit inverting the signal which is amplified by the input transistor and applying the inverted signal to a gate of the output transistor.

Abstract: A low dropout regulator comprises an output transistor with a controlled section between a first supply terminal and an output terminal, and a differential amplifier comprising a feedback input coupled to the output terminal, a reference input receiving a reference voltage, an output connected to a control terminal of the output transistor, and a pair of input transistors connected to a tail current source. A control terminal of a first transistor is connected to the reference input. A control terminal of a second transistor is connected to the feedback input. A first capacitive element is coupled between the output terminal and common connection of the input transistors of one pair with their tail current source. A second capacitive element is coupled between a second supply terminal and the common connection of the input transistors of one pair with their tail current source.