Abstract: A VCO circuit includes a temperature detector circuit, a voltage generator circuit, a switch, a resonance circuit and an oscillator. The temperature detector detects a temperature, and the voltage generator circuit generates a voltage for coarse adjustment corresponding to the detected temperature and outputs the same voltage. The switch selects one of a DC voltage for fine adjustment and the voltage for coarse adjustment. The resonance circuit includes a varactor diode having a capacitance value adjusted based on the voltage selected by the switch, capacitors and an inductor, and has a predetermined resonance frequency. The oscillator generates an oscillation signal having an oscillation frequency corresponding to the resonance frequency by using the resonance circuit and outputs the same signal.

Abstract: In a clock generating circuit, while a PLL (Phase-Locked Loop) circuit and a modulator are employed, when a frequency dividing ratio of a feedback-purpose frequency divider in the PLL circuit is changed in accordance with modulation data produced based upon a modulation profile of the modulator to perform a frequency modulation so as to spread a spectrum, a turning point of the modulation profile is moved so as to disperse a degree of frequency, so that the spread spectrum is re-spread. Also, a clock generating circuit is constituted by a PLL circuit and a modulator, a multiple modulation profile generating circuit is provided in the modulator, and a turning point of a modulation profile is moved so as to disperse a degree of frequency, so that a spread spectrum is re-spread.

Abstract: A system and method for generating a highly stable holdover clock utilizing an integrated circuit and an external OCXO is presented. The integrated circuit comprises an input reference clock receiver, a phase and frequency detector that generates an error signal between the input reference clock signal and a feedback clock signal, a data storage block that stores model parameters to predict frequency variations of the OCXO, an adaptive filtering module that includes a digital loop filter and algorithms for updating the model parameters and predicting frequency variations based on the model, a switch that enables the system to operate in normal or holdover mode, a digitally controlled oscillator, and a feedback divider.

Abstract: A multi-band VCO module includes a multi-band VCO and a controlling module. The multi-band VCO is for selecting a specific band from a plurality of bands according to a band selecting signal, and for outputting an oscillating signal according to a predetermined voltage and the specific band. The controlling module, coupled to the multi-band VCO, is for setting the band selecting signal according to a reference frequency of the reference signal and an oscillating frequency of the oscillating signal. A related method and a PLL circuit utilizing the multi-band VCO module are also disclosed.

Abstract: Increasing loop gain is a common practice for reducing lock time of phase locked loops. Very high loop gains, however, often result in increasing the lock time or causing loop instability. For very high loop gains, delaying the feedback clock signal along the feedback path of a phase locked loop decreases lock time and prevents instability. A delay circuit may be used at any location along the feedback path of the phase locked loop.

Abstract: It is an object of the present invention to provide a PLL apparatus outputting a frequency signal from a voltage-controlled oscillation unit in synchronization with an external reference frequency signal, in which the fluctuation of the frequency is reduced even when the external reference signal has a trouble. As a concrete means for solving the problem, as a result of monitoring the signal level of the external reference frequency signal, when its signal level falls within a set range, data regarding a phase difference created by a phase difference data creating means is used for the PLL control, but when the signal level does not fall within the set range, it is recognized that the supply of the signal has been stopped or the supplied signal has abnormality and the data regarding the phase difference stored in a storage unit, for example, the stored latest data or the pre-created data is used instead for the PLL control.

Abstract: Techniques to compensate for nonlinearity of a tuning function of an oscillator are described. The tuning nonlinearity of the oscillator may be modeled as a disturbance input to the oscillator and may be compensated with an equal but opposite disturbance. In one design, a nonlinearity correction signal to compensate for the tuning nonlinearity may be generated, e.g., based on a phase error signal in a phase-locked loop (PLL) and a scaling factor determined adaptively. The nonlinearity correction signal may compensate for the n-th (e.g., second) order tuning nonlinearity, and an n-th order (e.g., squared) modulating signal may be used to derive the scaling factor and the nonlinearity correction signal. A control signal for the oscillator may be generated based on the nonlinearity correction signal and possibly one or more other signals. The control signal may be applied to the oscillator to adjust the oscillation frequency of the oscillator.

Abstract: To provide a phase locked loop circuit that is capable of performing an automatic adjustment that satisfies a desired characteristic not depending on a process variation and an environmental variation. The phase locked loop circuit has a phase frequency comparator, a charge pump, a loop filter, a frequency divider, a selector, and a voltage controlled oscillator. The frequency divider inputs an output signal and a reference signal, divides the output signal, and outputs a feedback signal, and also outputs a select signal, a trimming signal, and a limit signal from the output signal. The voltage controlled oscillator inputs the control voltage, the base voltage, the trimming signal, and the limit signal, changes the output signal frequency according to the control voltage so as to limit the upper limit frequency of the output signal.

Abstract: A voltage-controlled oscillator (VCO) of ring-connected stages, where each stage in the VCO has a first set of differential inverters biased by variable bias voltages, and a second set of differential inverters biased by fixed bias voltages. The differential inverters in each stage are connected in parallel with each other. Each set of differential inverters in a stage may contain only one differential inverter. The variable bias voltages are provided by charge pumps and associated circuits as used in well-known self-biasing schemes for phase locked loops. The fixed bias voltages are provided by a biasing circuit, matched to the circuits associated with the charge pumps, but where a fixed control voltage is applied to provide the fixed bias voltages.

Abstract: A first phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal from an oscillator, a controllable oscillator circuit supplying an oscillator output signal, and a multi-modulus feedback divider circuit. A second control loop circuit is selectably coupled through a select circuit to supply a digital control value (M) to the multi-modulus feedback divider circuit of the first loop circuit to thereby control the oscillator output signal. While the second control loop is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between the oscillator output signal and a reference signal coupled to the second control loop circuit at a divider circuit.

Abstract: An apparatus for providing Phased-Locked Loop (PLL) synthesis comprises a phase detector, at least one switchable filter, an oscillator controlled by a control voltage (uPLL) and a divider. The controlled oscillator has two inputs, wherein the control voltage (uPLL) is coupled to a first input, and a selection voltage (uSET) for rough frequency adjustment is coupled to a second input. Both voltages establish the frequency of the oscillator.

Abstract: A voltage control oscillation (VCO) circuit and an adjusting method for the same, which enables an adjustment for suppressing the dispersion of the output characteristic in spite of the manufacture-related dispersion of element characteristics, using a simple circuit configuration, are provided. A low-pass filter 15 and a high-pass filter 16 are composed of the elements that have the same structure as elements composing the VCO circuit 11, and a prescribed correlation is established between both elements. A corrective element 14 is connected in parallel to a main element, in which an oscillation frequency control signal VT is input, in the VCO circuit 11. Respective frequency-gain characteristic lines of the low-pass/high-pass filters 15 and 16 have gradients reverse to each other and cross at a target gain TG. When the capacitance value lowers in dispersion, the level of an output signal SL2 becomes higher than that of an output signal SH2 at a reference frequency fREF to form an output level difference LD2.

Abstract: A frequency synthesizer capable of high speed, low power, wideband operation including a method of gain compensation, and a method of fast voltage controlled oscillator (VCO) band calibration. In addition, the frequency synthesizer may include two or more switchable independent loop filters to facilitate wideband operation. Such a frequency synthesizer may be used in many applications, and in one example, may be particularly suitable for use in a multi-band, multi-standard transmitter or radio transceiver.

Abstract: Embodiments of present invention provide a circuit including a voltage regulator, a phase frequency detector, a charge pump, a low pass filter a control-voltage generating circuit and a voltage controlled oscillator. In a first mode of operation the voltage controlled oscillator produces an output clock in accordance with a control voltage produced from the control-voltage generating circuit and the output voltage of the voltage regulator. In a second mode of operation, the voltage controlled oscillator produces an output clock in accordance with a control voltage from the low pass filter and the output voltage of the voltage regulator.

Abstract: The present invention provides a circuit, a control system, an IC, a transmitting and receiving apparatus, a control method, and a program which can reduce a phase error and simultaneously suppress a high-frequency jitter component and a low-frequency wander component. A PLL1 unit which is a high-frequency jitter suppression unit, a PLL2 unit which is a low-frequency wander suppression unit, and a PLL3 unit which is a reproduction clock unit are connected to form a multiloop synthesizer configuration.

Abstract: A control system for a mechanical oscillator having a sinusoidal drive signal with a frequency that is a fractional multiple of a frequency of a signal of the mechanical oscillator. The drive signal may be in phase and in registration with the signal from the mechanical oscillator. A sense signal may be picked off from the oscillator and be demodulated to obtain a parameter sensed by the oscillator. The drive signal to the oscillator may be selected or blanked out while receiving and demodulating the sense signal.

Abstract: Embodiments of a phase lock loop and a method for compensating a temperature thereof can output an initial tuning digital value for a voltage controlled oscillator configured to output a desired phase lock loop frequency compensated according to a temperature change. Embodiments of a phase lock loop and a method for compensating a temperature thereof can simultaneously perform a digital coarse tuning and an analog fine tuning to compensate for a temperature in a limited time.

Abstract: A phase-locked loop (PLL) architecture (100) is provided that includes a voltage-controlled oscillator (VCO) (116). The PLL architecture (100) also includes a digital calibration loop (132) coupled to the VCO (116). The digital calibration loop (132) implements a digital filter (126) to provide a digital control to the VCO (116) for centering a VCO frequency output. The PLL architecture (100) also includes an analog calibration loop (130) coupled to the VCO (116). The analog calibration loop (130) provides an analog control to the VCO (116) for adjusting the centered VCO frequency output.

Abstract: Aspects of a method and system for a fast-switching Phase-Locked Loop using a Direct Digital Frequency synthesizer may include generating a second signal from a first signal by: frequency translating an inphase component of the first signal utilizing a filtered fast-switching oscillating signal generated using at least a direct digital frequency synthesizer (DDFS), and frequency translating a corresponding quadrature component of the first signal utilizing a phase-shifted version of the generated and filtered fast-switching oscillating signal. The inphase and quadrature components of the first signal may be multiplied with the filtered fast-switching oscillating signal and a phase-shifted version of the filtered fast-switching oscillating signal, respectively.

Abstract: The present invention provides novel systems and techniques for the calibration and fast tuning of VCOs in PLLs. Information for coarse tuning before normal operation are calculated and stored. Therefore, these systems and techniques decrease significantly the time needed for a PLL to transition from one frequency to another. These techniques include the steps of: determining a digital code Dc, to coarse tune to a calibration frequency, FC; dividing the operating frequency band of the PLL into a plurality of sub-bands; determining and storing the information needed to generate the offsets for each sub-band. In tuning to a desired frequency, the following steps are taken: determining the sub-band corresponding to the desired frequency, F, generating the offset for that sub-band, calculating the digital code for coarse tuning the VCO to the desired sub-band, coarse tuning to a frequency within the desired sub-band, and fine tuning to the desired frequency.

Abstract: An oscillator circuit can generate a periodic signal, and a frequency adjustment circuit can adjust the frequency of the periodic signal. The periodic signal may include phase jitter. In one aspect of the invention, the phase jitter may be mitigated by connecting other circuitry to the oscillator circuit and allowing the other circuitry to draw current. In one embodiment, the other circuitry is connected in parallel with the oscillator circuit. In one embodiment, the other circuitry is configured to draw greater current to mitigate more phase jitter and to draw less current to mitigate less phase jitter. In one embodiment, a greater portion of the other circuitry is connected to the oscillator circuit for higher frequencies and a lesser portion of the other circuitry is connected to the oscillator circuit for lower frequencies.

Abstract: A phase locked loop circuit comprises a voltage controlled oscillator with a control input to which a variable control voltage is applied and a phase-frequency discriminator with an output connected to a loop filter to produce the control voltage. To provide the phase locked loop circuit with a low loop gain and a wide frequency pulling range, a plurality of discrete capacitors is associated with the voltage controlled oscillator. A switch array selectively activates and deactivates each of the capacitors in the voltage controlled oscillator. Each number of currently activated capacitors determines one out of a plurality of partial ranges of frequencies through which the oscillator can be tuned by a variation of the control voltage in a range between predetermined upper and lower control voltage limits. A total frequency range through which the oscillator can be tuned is divided thus into a plurality of partial frequency ranges each defined by a different number of activated capacitors.

Abstract: An adaptive phase-locked loop (PLL) circuit produces an output signal having a frequency in reference to the frequency of a reference signal. The PLL circuit includes an oscillator configured to generate the output signal according to a frequency control signal, and a processing circuit configured to generate a feedback signal deriving from the output signal. An adjustable shift circuit is provided to time-shift the feedback signal. The PLL further includes a phase comparison circuit configured to generate a phase error signal indicating a phase error between the time-shifted feedback signal and the reference signal, and a control circuit configured to generate the frequency control signal based on the phase error signal. The adjustable shift circuit adjusts a time-shift amount to time-shift the feedback signal according to the phase error signal.

Abstract: A system and method for reducing the transient responses in a phase lock loop (PLL) (100) with variable oscillator gain is disclosed. The system includes a charge pump (104) having an adapt mode and a normal mode of operation. The charge pump (104) also includes controlled trickle currents from current sources (208), (210) which are applied to the output (105), (107) of charge pump (104) to minimize the transient responses of the PLL (100). A programmable delay is provided in the charge pump (104) and is configured using a controller (122) based on the variable oscillator gain for the PLL (100). The configured programmable delay is used in the adapt mode of operation for adding a trickle current from the current source (210) to the adapt mode output (107).

Abstract: A phase-locked method includes: generating a selection signal according to a detection result of a phase/frequency detector (PFD) of a phase-locked loop (PLL); generating a plurality of oscillation signals according to at least a first oscillation signal generated by the PLL, wherein the plurality of oscillation signals respectively correspond to a plurality of phases; and from the plurality of oscillation signals, selecting an oscillation signal as an output signal of the PLL according to the selection signal.

Abstract: A multi-Gigahertz, low jitter phase locked loop (PLL) with adjustable gain is disclosed. In one embodiment, properties of a fVCO signal of a PLL can be acquired. Properties can include the occurrences of different types of jitter on the fVCO signal and the lock status of the PLL. A gain control module can control at least a portion of the PLL based on an analysis of the acquired properties. For example, when the loop is locked or when there is loop filter leakage, the gain of a charge pump in the PLL can be reduced. When a charge pump mismatch is detected based on the acquired properties, additional control signals can be provided to the charge pump to correct the mismatch.

Abstract: The present invention relates to a method for stabilising the operation of a voltage controlled oscillator driven by a phase locked loop, the voltage controlled oscillator delivering an RF signal and receiving through at least one spurious path a harmonic component of a frequency equal or proximate to that of the RF signal, capable of disturbing its operation by injection pulling. According to the present invention, the method comprises a step of injecting into the voltage controlled oscillator an injection pulling compensation signal, the phase and the amplitude of which are adjusted so as to neutralise the effects of the spurious harmonic component. Application particularly to phase modulation IQ circuits in radiotelephony.

Abstract: A receiver circuit includes an oscillator circuit configured to generate a calibration tone and a phase locked loop (PLL) reference signal. An output frequency of the VCO may be divided by respective amounts to derive a desired calibration tone frequency and a desired PLL reference signal frequency. In addition to the oscillator circuit, the receiver circuit may further include a phase locked circuit configured to generate a PLL output signal that is phase locked in relation to the PLL reference signal. During a calibration mode, a quadrature generator may be used to generate quadrature mixer local oscillator signals dependent upon the PLL output signal, and an in-phase/quadrature mixer may be used to mix the calibration tone with the quadrature mixer LO signals.

Abstract: A phase locked loop (PLL) having a continuous bank calibration unit and a method of preventing unlocking of the PLL are provided. The PLL includes a main circuit, a voltage controlled oscillator (VCO), and a continuous bank calibration unit. The main circuit outputs a control voltage in response to an external clock signal and an oscillating signal. The VCO outputs the oscillating signal in response to the control voltage and the bank calibration signal. The continuous bank calibration unit compares the received control voltage with a window voltage having at least two comparison values to output the bank calibration signal. In the PLL having a continuous bank calibration unit, although the control voltage varies with external factors such as temperature, the bank of the VCO is immediately and suitably calibrated to prevent unlocking of the PLL, so that it is possible to Improve an output characteristic of the VCO.

Abstract: Circuits and methods for compensating a variable oscillator for process and/or operational variations. The circuit generally comprises (a) a replica oscillator, (b) a counter configured to count pulses of the replica oscillator and to produce a count signal, and (c) a compensation circuit configured to provide an adjustment signal to the variable oscillator in accordance with the count signal. The method generally comprises the steps of (a) counting the number of pulses of a replica oscillator signal, and (b) providing an adjustment signal to the variable oscillator in accordance with the number of pulses counted. The present invention advantageously provides a largely digital method to compensate a variable oscillator for process, voltage, and temperature variations.

Abstract: A PLL circuit according to an embodiment of the present invention includes: a phase comparator to output an up signal and a down signal based on a phase difference between a reference clock signal and a feedback clock signal; an offset correcting circuit to correct a pulse width of at least one of the up signal and the down signal to output a modified up signal and a modified down signal; a first charge pump circuit to increase or decrease a charge pump output voltage to be output in accordance with the modified up signal and the modified down signal; a loop filter to filter out noise of the charge pump output voltage and generate a filter voltage; and a voltage-controlled oscillation circuit having an oscillation frequency controlled based on a voltage value of the filter voltage and outputting an output clock signal.

Abstract: A technique provides a clock source that meets accuracy requirements, allows the use of a low cost resonator, provides a wide range of output frequencies, and provides suitable phase noise performance. The technique generates a clock signal having a target output frequency using a controllable oscillator having at least one continuous frequency range of operation. The technique dynamically adjusts a reference control value based on a voltage for adjusting a frequency of the clock signal around a frequency determined by the reference control value. The reference control value is adjusted to be approximately within the center of an actual pull range corresponding to the controllable oscillator and a voltage control input of the controllable oscillator. The effective pull range of the controllable oscillator is continuous across the at least one continuous frequency range of operation.

Abstract: A fast switching phase lock loop (PLL) device is provided. The PLL has a voltage controlled oscillator that generates a signal at a frequency according to a received voltage. A memory holds a set of adjustment values, with each adjustment value set to cause the VCO to pre-tune to a desired frequency. When a new frequency is required from the VCO, the PLL counters are set for the new frequency values, and the adjustment value associated with the new frequency is retrieved from memory. A voltage generator uses the adjustment value to generate a new control voltage, which pre-tunes the VCO to a frequency near the desired frequency. In this way, the VCO only needs to make minor adjustments through its loop feedback filter to lock to the new frequency. After the VCO is locked, the actual control voltage is measured and used to update the adjusted value for that frequency. In this way, the set of adjustment values are continually updated to adapt to changing environmental or circuit conditions.

Abstract: To provide dual loop PLLs capable of reducing the lock-up time in the initial start-up, and multiplication clock generators contributing to reduction of the power dissipation. The dual loop PLL comprises a dual loop PLL having a phase comparison loop having a phase comparator 1 for comparing phases, and a frequency comparison loop having a frequency comparator 7 for comparing frequencies, wherein the frequency comparator 7 carries out frequency comparison using an input signal inputted from a calibration clock line CLcal 18, the input signal being different from a reference clock signal inputted from an external reference clock line CLex 11, the reference clock signal being used for a phase comparator 1. Moreover, multiplication clock generators are configured using the dual loop PLL.

Abstract: An ensemble clock comprises: an input for receiving a reference signal; multiple free-running oscillators each configured to generate a corresponding free-running frequency; an output oscillator configured to generate a controlled frequency having a frequency responsive to a control signal; a differencer unit configured to derive difference measurements indicative of time and frequency-based errors associated with each of (i) the controlled frequency, and (ii) the free-running frequency, relative to the reference signal; and a controller configured to generate the control signal responsive to the difference measurements.

Abstract: A circuit and method are provided for calibrating an analog oscillator in the digital domain. The circuit and method disclosed herein centers an oscillation frequency of an analog oscillator by producing a binary signal to which the analog oscillator is responsive. Changes in the binary digital signal cause the oscillation frequency of the analog oscillator to shift in a desired direction to calibrate the analog oscillator. At the completion of the calibration process, the control of the oscillation frequency of the analog oscillator is switched to the analog domain so that the analog oscillator is responsive to an analog control voltage to shift the oscillation frequency.

Abstract: A phase locked loop (PLL) circuit, comprises a frequency integrator circuit that receives a target signal, a phase shift signal and a frequency gain correction parameter and that selectively disables tracking frequency offset based on a value of the frequency gain correction parameter. A phase integrator circuit communicates with frequency integrator circuit, that synchronizes phase with the target signal and generates a phase signal. A phase shift measurement circuit generates the phase shift signal based on the phase signal. A phase interpolator circuit generates the frequency gain correction parameter based on the phase signal.

Abstract: A Phase-Locked Loop (PPL) circuit includes a voltage controlled oscillator (VCO), a reference signal oscillator, first and second frequency dividers, a phase comparator, a charge pump and a loop filter. The VCO has a plural number of oscillation frequency boards and oscillates according to a control voltage in a selected band. The first frequency divider frequency divides the output signal of the VCO. The second frequency divider frequency divides the reference signal outputted from the reference signal oscillator. The phase comparator detects the phase difference between the output signal of the first and second frequency dividers and outputs a phase difference signal. The charge pump inputs and outputs a current generated by a gain that was set depending on the selected band based on the phase difference signal. The loop filter increases or decreases the voltage with a specified low pass filter.

Abstract: A clock recovery circuit includes a phase discriminating circuit for discriminating, at every edge of a received data signal, phase lead or phase lag of an identically directed edge of the clock signal, and outputting the phase discrimination signal; an edge detecting circuit for detecting edges of the received data signal, outputting an edge detection signal of a fixed pulse width, delaying the received data signal and outputting the delayed signal; an exclusive-OR gate for outputting, as an edge injection signal, an exclusive-OR signal between the phase discrimination signal and delayed signal; and a voltage-controlled oscillator for variably controlling frequency of ring oscillation, injecting the edge injection signal into the loop of ring oscillation, and outputting a clock signal locked to the received data signal.

Abstract: A phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal, a phase detector circuit coupled to receive the timing reference signal, a controllable oscillator circuit controlled according to an output of the phase detector circuit, and a feedback divider circuit having an output coupled to the phase detector and an input coupled to the controllable oscillator circuit. The phase-locked loop circuit is coupled to output one of a plurality of output signals having an arbitrary frequency relationship to each other according to a frequency selection mechanism, the frequency selection mechanism including one or more input terminals coupled to control a divide ratio of the feedback divider circuit. The frequency selection mechanism selects one of a plurality of stored values.

Abstract: A voltage controlled clock synthesizer includes a phase-locked loop (PLL) circuit that receives a timing reference signal, a controllable oscillator circuit, such as a VCO, providing an oscillator output signal, and a feedback divider circuit coupled to the oscillator output signal. The frequency of the oscillator output signal is determined in part according to a stored value used to generate a first digital control signal that determines a divide ratio of the feedback divider circuit. A control voltage present on a voltage control input adjusts the frequency of the oscillator output signal around a frequency determined by the stored value. The control voltage is converted to second digital signal and is utilized in determining the first digital control signal in combination with the stored value.

Abstract: A frequency synthesizer including frequency and phase locked loop that operates in either a frequency locked loop (FLL) mode or a phase locked loop (PLL) mode. In a first state, the frequency and phase locked loop operates in the FLL mode for initial frequency acquisition. Once the frequency and phase locked loop has locked in FLL mode, the frequency and phase locked loop transitions to the PLL mode for normal operation.

Abstract: An apparatus and method for synchronizing sampling frequencies of a receiver and a transmitter of a multi-carrier communication system is provided. The receiver includes an estimator for estimating a frequency offset by employing an additional angle rotation of a received signal in frequency domain. The apparatus includes a compensation loop filter for generating a first output in response to a frequency offset compensation, an adder for adding the estimated frequency offset and the first output to generate a second output, and a loop filter for generating frequency offset compensation according to the second output. The method repeatedly applies the apparatus to generate frequency offset compensation, and then feeds it back to an oscillator to compensate the sampling frequency of the receiver. The apparatus and method can also be applied to a communication system with a carrier frequency offset.

Abstract: An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.

Abstract: A clock generator circuit is provided wherein a comparison clock signal is generated by comparing a standard clock signal and an operating clock signal. The comparison clock signal is converted into a current signal. The current signal is converted to multiple current signals and an operating clock signal having multiple varying frequencies is generated based on the multiple current signals.

Abstract: The invention relates to a device, especially an active backscatter transponder, for generating an oscillator signal based on a base signal. It comprises an oscillator for actively constructing the oscillator signal by oscillations, an input for the base signal and an output for the oscillator signal produced. The oscillator can be induced by the base signal to generate oscillator signal in a quasi-coherent manner to the base signal. For the transmission of data, the device further has a data insertion device for inserting data or a data signal into the oscillator signal. A corresponding suitable receiver receives and processes the received signal that was generated and transmitted by such a device as a quasi-coherent signal. A separation device removes the signal portions of the oscillator from the received signal via the base signal of a receiver-side oscillator, with a data retrieval device for retrieving the inserted data.

Abstract: System for controlling the frequency of an oscillator. A first circuit is coupled to the oscillator and arranged for receiving an externally provided clock signal at a first input node. A second circuit coupled to the oscillator is arranged for receiving an externally provided frequency reference input at a second input node. The first circuit uses the clock signal received at the first input node to control the frequency of the oscillator. In absence of a clock signal received at the first node, the second circuit uses the frequency reference input received at the second input node to control the frequency of the oscillator. The frequency reference input is selectively at one of (a) a first or second fixed voltage level designating a first or second oscillator frequency, and (b) a variable signal level designating a frequency between the first and second oscillator frequencies.

Abstract: A high frequency sweep generator uses a DDS-PLL method for frequency sweep over wide frequency spans. A digital sweep generator produces a linear ramp signal using DDS techniques that is applied to a coarse tuning port of a high frequency tunable oscillator, such as a YIG tunable oscillator (YTO). A PLL has as inputs an accurate linear swept frequency sinusoid from a DDS and a linear swept frequency output signal from the YTO to produce an error correction signal that is applied to a fine tuning port of the high frequency tunable oscillator. The error correction signal compensates for any non-linearities introduced into the linear swept frequency output signal by the high frequency tunable oscillator.

Abstract: The frequency of a first voltage controlled oscillator is stabilized in a first PLL circuit part into which a reference frequency signal is inputted. In addition, a second PLL circuit part is formed by inputting a control voltage which is the same as the frequency control voltage of the first voltage controlled oscillator into a second voltage controlled oscillator having the same configuration as the first voltage controlled oscillator. The first PLL circuit part is provided with first and second variable frequency dividers which respectively divide the reference frequency signal and the output of the first voltage controlled oscillator. In response to an input signal into the second PLL circuit part, the free-running frequencies of the second and first voltage controlled oscillators are switched, and at the same time, the division ratio of first and second variable frequency dividers are switched.

Abstract: A phase-locked loop system, including a voltage controlled oscillator coupled with an error detector in a feedback configuration, so as to produce an output signal having a desired characteristic that is based on a reference signal. The system also includes a charge pump system coupled with the voltage controlled oscillator and configured to produce currents to control phase and frequency of the output signal. The charge pump system includes at least two charge pumps, one being configured to effect more rapid changes in the output signal than the other. This charge pump may be configured to deliver a higher charge pump current than the other charge pump, and/or may be activated intermittently upon detection of cycle slippage or another condition detectable during operation of the phase-locked loop system.