Abstract: A circuit for generating a control signal includes a frequency-determining element (C3), a clock generator for generating a clock signal and a control circuit coupled to the clock generator for generating a control signal as a function of the magnitude of the voltage at the frequency-determining element and for applying the control signal to the frequency-determining element. The control circuit includes a sawtooth generator having a sawtooth frequency-determining element (C1) for converting the clock signal into a second signal having a constant slope as a function of time, and a storage element (C2) which produces a voltage that depends on the amplitude of the sawtooth signal.

Abstract: A frequency synthesizer is designed to modify voltage value data read out of a memory in accordance with the output voltage of a filter, and apply a d.c. voltage corresponding to the modified data to a second variable-capacitance diode at the control input of a VCO, thereby allowing the VCO frequency switching without imposing a significant fluctuation of the application voltage to a first variable-capacitance diode and accomplishing a short channel switching time and stable operation against temperature fluctuation. The device is further designed to supply a voltage setup value read out of the memory to the second variable-capacitance diode thereby to reduce the frequency matching time at channel switching, and to determine such another voltage setup value as to reduce the time of phase matching based on the trend of change in the filter output voltage and supply the value to the second variable-capacitance diode.

Abstract: An improved fast-switching frequency synthesizer is disclosed. The fast-switching frequency synthesizer, according to the invention, utilizes presteering voltage injection at the voltage controlled oscillator ("VCO") with feedback to allow the VCO, and synthesizer, to quickly transition between two given frequencies. This presteering mechanism, with the feedback, allows the presteering voltage to track the variations in the VCO gain from device to device, and gain changes while in operation. This same information is used to implement a means of automatically adjusting the FM deviation of the transmitter since that information varies with the gain of the VCO as does the FM deviation.

Abstract: An oscillator circuit is coupled to receive first and second reference signals and includes a voltage-controlled oscillator for generating an oscillating signal. A difference frequency calculation circuit is coupled to the voltage-controlled oscillator to produce a count signal corresponding to a difference in frequency between the oscillating signal and the first reference signal. A feedback circuit is coupled to the difference frequency calculation circuit and coupled to receive the second reference signal which corresponds to a predetermined frequency for the oscillating signal. The feedback circuit provides a control signal as an input to the voltage-controlled oscillator to control the frequency of the oscillating signal.

Abstract: A coherent phase and frequency recovery method capable of rapidly recovering the phase and frequency of bursts of received signals from plural sources. The received signal is applied to a first input of a mixer, the output of which is amplified and applied to two feedback paths, one for frequency and the other for phase. The frequency path contains a loop filter driving a voltage-controlled oscillator, and the phase path a loop filter and amplifier. Initial estimates of the phase and frequency of the present burst are derived and injected into the respective feedback paths. The output of the phase path is applied to correct the phase of the output of the frequency path, which is then applied to a second input of the mixer.

Abstract: In a phase locked loop frequency synthesizer, the frequency of a VCO is switched by changing the division ratio of a variable ratio frequency divider in the feedback path of the loop. At the time of switching, a prepositioning voltage is applied to the VCO to realize fast frequency switching. To correct for nonlinear response of the VCO, the prepositioning voltage is adjusted according to information received from a voltage measuring circuit connected to the VCO control circuit.

Abstract: A transmitter includes a phase-locked loop (PLL) circuit whose output is frequency modulated with a modulation signal. The modulated signal is amplified by an amplifier which is turned on only during a signal transmission of the transmitter. At a time when the amplifier is turned, the output frequency of PLL circuit fluctuates. To depress this frequency fluctuation, the transmitter includes a frequency fluctuation depressing (FFD) circuit. Upon the turning-on of the amplifier, FFD circuit applies a voltage change to the modulation signal so that the frequency fluctuation is depressed.

Abstract: A method and means for setting the free-running frequency of a voltage controlled oscillator (VCO) without requiring laser trimming or the like is described. The VCO forms part of an interconnected phase-locked loop (PLL) and frequency-locked loop (FLL). At system power on, the PLL is automatically disabled and a digital-to-analog (DAC) in the PLL is set to a value corresponding substantially to the center of a preselected lock range. The FLL, which includes a second DAC, then operates to generate a bias voltage for incrementing or decrementing the VCO output frequency until the VCO pulse count stored in a register equals an expected count; whereupon the VCO will be set at its free-running frequency. When the PLL is enabled, a phase error generator generates a digital phase error signal from the input data. A digital integrator converts the phase error signal to a digital frequency error signal.

Abstract: Clocking circuitry for a character generator wherein a control microprocessor controls character generated by hardwired logic through an interface microprocessor, the clocking circuitry including an oscillator which supplies an output to a divider which supplies a reduced frequency signal to the control microprocessor. The output of the oscillator is also supplied to the output of a timing controller. The timing controller further receives a print signal from the interface microprocessor and supplies a plurality of timing signals to the hard wired logic character generator.

Abstract: In order to compensate for mechanical vibration that corrupts the RF output spectrum of a crystal oscillator, three accelerometers are mounted with the oscillator and aligned on mutually perpendicular axes. The outputs of the accelerometers are digitized and applied to adaptive transversal filters comprising a digital signal processor. The crystal oscillator is placed on a vibration table and its output is compared with an external frequency reference. The tap weights of the filters are then optimized so that the vibration components of the output spectrum of the oscillator are minimized. After the tap weights of the filters are determined and fixed, the filters provide vibration compensation for the oscillator. During operation of the crystal oscillator, the outputs of the filters are summed and applied to a varactor in the oscillator to compensate the output for the effects of mechanical vibration.

Abstract: The output of a local oscillator is applied to an external signal to produce a feedback error signal. The feedback error signal is utilized in adjusting the phase, frequency and amplitudes parameters of the local reference sine-cosine quadrature components which comprise the output of the local oscillator signal. Adjusting the parameters modifies the output of the local oscillator. The modified output of the local oscillator is applied to the external signal to continuously modify the feedback error signal, which in turn, continuously modifies the output of the local oscillator until the frequency and phase of the local oscillator signal is locked to that of the external signal.

Abstract: A frequency synthesizer with a voltage-controlled oscillator that can be tuned over its total frequency range in increments of a prescribed frequency range a frequency-dictating component. A reference oscillator emits a reference signal of a strictly prescribed frequency that is supplied as a first input signal to a comparator to which is simultaneously supplied a second input signal of a frequency that is a function of the frequency of the output signal from the voltage-controlled oscillator. The comparator generates a fine-tuning signal in accordance with the difference between the frequencies or between the phases of the first and second input signals and supplies the fine-tuning signal to the voltage-controlled oscillator.

Abstract: A phase-locked loop compares the loop output clock with the loop input clock in a digital phase detector to provide lead/lag error signal samples. A microprocessor utilizes the lead/lag error samples to track the input clock in a wideband mode matching the bandwidth of the input and in a very narrow band mode. When the system in which the loop is utilized switches to a new input clock source, the microprocessor resets the loop divider chain so that the loop feedback signal is phase coincident with the input reference. The microprocessor tracks the new clock for a predetermined number of error samples in the wideband mode and statistically estimates, from the samples, the frequency of the input. After the frequency estimation, the microprocessor controls the loop VCO to output the computed frequency and switches to the narrow band tracking mode.

Abstract: A frequency synthesizer of the fractional N type comprising a voltage controlled oscillator for producing an output signal which is afforded to a phase detector via a variable divider to provide a control signal for the voltage controlled oscillator in the presence of a phase difference between a reference signal from a reference source and the signal afforded thereto from the variable divider wherein the division ratio of the variable divider is set in dependence upon the output of an interpolator arrangement comprising combiner means for receiving a digital input, digital controller means for receiving an output from the combiner means, digital slicer means for receiving an output from the digital controller means, feedback means for affording the output of the digital slicer means to a component for varying the division ratio of the variable divider.

Abstract: For use in a radio synthesizer (110), a digital phase detector (118) indicates the phase error between a reference signal provided by a reference oscillator (117) and an output frequency signal (114) provided by a voltage controlled oscillator (112). The digital phase detector (118) includes four flip/flops (310, 312, 314 and 316) which receive the frequency signals (116 and 120) provided by the oscillators (117 and 112) to generate steering signals (126) which optimally indicate the phase error between the frequency signals (116 and 120) as well as providing optimal (maximum) frequency steering when a frequency difference between the frequency signals (116 and 120) exists. Responsive to the flip/flops, digital logic circuitry (306) is used to provide a non-integrated level-type indication when the frequency signals (116 and 120) are phase locked.

Abstract: A dynamic control system includes at least one control loop which contains a comparator, a correction device and an adjusting device with a control device wherein a controlled variable is determined and compared with a reference variable for forming a control difference, the correction and the adjusting device operating to provide a given characteristic, a controlled variable being derived by the adjusting device cooperating with a control variable derived from the control device as the output variable wherein the control loop can be coupled to at least one further control loop and/or variable of the dynamic control system, wherein the further control loop includes an adjusting device and wherein the control device contains at least two functional groups having different characteristics, of which at least one is intermittently connected in the signal path of the control difference for generating the controlled variable and a method for operating the dynamic control system.

Abstract: A fractional N synthesizer comprising a voltage controlled oscillator for producing an output signal which is afforded to a phase detector via a variable divider to provide a control signal for the voltage controlled oscillator in the presence of a phase difference between a reference signal from a reference source and the signal afforded thereto from the variable divider wherein the synthesizer is provided with first and second accumulators, the arrangement of the accumulators being such that an output signal from the arrangement is provided in which the interpolation sidebands of the first accumulator caused by quantization errors in the first accumulator are cancelled, means being provided for setting the division ratio of the variable divider in dependence upon the output signal.

Abstract: A signal generating device and method of control thereof for producing a desired output frequency, the generator having coarse and fine tuning controls capable of producing frequency changes over a limited range, wherein the output of the device is combined in a mixing device with a multi-component reference signal produced from an oscillatory generator circuit, a beat signal is detected by processing circuitry as the frequency controls are adjusted and the values of the frequencies of the control signals occurring on such detection are stored, and using a look-up table or algorithm the value of a correction signal is determined which, when combined with the stored values, will cause the output frequency of the device to be adjusted to the desired value via the fine tuner.

Abstract: A phase-lock loop includes a tristate phase detector, a filter and a voltage-controlled oscillator connected in a loop for regenerating clock signals in response to a sequence of data signals applied to the input terminal of the tristate phase detector and the loop. The tristate phase detector opens its output lead whenever a zero is applied to the input terminal of the loop. A resistor is interposed between the tristate phase detector and the loop filter to clamp excursions of a control signal, causing the filter to produce a consistent tuning control signal and forcing the voltage-controlled oscillator to oscillate at a frequency within a preselected frequency range independent of the ones density in the digital sequence applied to the input terminal of the loop.

Abstract: A clock recovery and data separator system of the type described in U.S. Pat. No. 4,456,890 is improved by the inclusion of a detector for detecting the trend of instantaneous media speed variation (ISV). The system includes a phase locked loop in which the ISV trend detector is placed between the output of the phase detector and the input of an up/down counter whose output is passed through a digital to analog converter to control the VCO. The ISV trend detector provides a signal which partially compensates phase shift, thereby permitting rapid data recovery performance.

Abstract: Generating clock signals of slightly different frequencies without the signals locking up in synchrony, by providing a voltage-to-frequency converter driven by the output of an integrator, which is supplied with a signal representative of the sum of a frequency-difference command and the difference in frequency between the two clocks.

Abstract: A frequency controlled oscillator arranged to be fabricated in integrated circuit form including a primary frequency controlled oscillator and a secondary frequency controlled oscillator with a counter arranged to periodically count pulses of the oscillation frequency of the secondary frequency controlled oscillator and to produce a first output signal if the count is less than a predetermined value and to produce a second output signal if the count is greater than a predetermined value, and control means providing a bias control signal in dependence on the output signals of the counter for tuning the oscillation frequency of both the secondary frequency controlled oscillator and the primary frequency controlled oscillator.

Abstract: A wide-band amplifier apparatus utilizing a low frequency and a high frequency phase lock loop to achieve low phase delay at the loop bandwidth. The bandwidth products of the low and high frequency loop paths are combined and applied to the voltage controlled oscillator to minimize phase delay and to achieve a more stable loop.

Abstract: A frequency stable RF oscillator 10 comprises a variable frequency RF source in the form of a microwave cavity 24 having a Gunn diode 26 and a varactor 28 mounted therein, and produces an RF output frequency f.sub.o. The output of a frequency stable reference oscillator 14 having a frequency f.sub.r is impressed upon the RF source. Through self-mixing action of the Gunn diode, an IF whose frequency is f.sub.IF =.vertline.nf.sub.r -f.sub.o .vertline. is generated, n being a high harmonic number. The IF is detected by an IF amplifier 18 which forms part of a frequency lock loop controlling the frequency of the RF source.

Abstract: A temporal pixel clock synchronization system with jitter correction for an optical scanning system having a continuously running pixel clock source, circuitry for generating timing error signals having an amplitude representing any phase error between start of scan and start of pixel count pulses and any phase error between end of scan and end of pixel count pulses and circuitry, including a switched filter circuit with two storage elements for each facet of the polygon of the system, for generating a frequency correction signal for the pixel clock source.

Abstract: An injection locked RF oscillator comprises a variable frequency RF source 12 having a Gunn diode 20 and a varactor 22, and a frequency stable reference oscillator 14 whose output f.sub.i is injected into the source to cause injection locking of the source. The output of a low frequency perturbation oscillator 30 is applied to the varactor and the resultant variation in the current consumption I.sub.o of the Gunn diode detected by amplifier 28 and filter 36 to provide a control signal which is effective to shift the resonant frequency f.sub.o of the source 12 towards the frequency f.sub.i of the reference oscillator, or a harmonic thereof. A sweep-and-lock circuit 44 is provided to acquire injection locking upon switch-on.

Abstract: The acquisition of phase lock to a reference frequency by a signal acquisition system is accomplished using a voltage controlled oscillator, a wideband frequency discriminator, a prepositioning circuit, and a phase lock loop. The voltage controlled oscillator is prepositioned within a loop bandwidth of the reference frequency by the prepositioning circuit and the wide band frequency discriminator which provide coarse tuning. The voltage controlled oscillator achieves phase lock with the reference frequency when it receives the fine tune signal from the phase lock loop. Using both the discriminator and the phase lock loop allows fast acquisition without the need to calibrate the voltage controlled oscillator. Since the discriminator pull-in range is much larger than the phase-lock loop bandwidth, the number of bits can be much smaller than in an acquisition circuit using a digital prepositioning circuit alone.

Abstract: A phase-locked loop frequency synthesizer apparatus for providing an output signal whose frequency jumps from one value to another, at regular intervals of time. Coarse tuning circuitry couples a prescribed signal to the apparatus' voltage-controlled oscillator (VCO), to drive the VCO immediately to the correct frequency each time a new frequency is selected, thereby substantially reducing the apparatus' settling time. In addition, adaptive coarse tuning circuitry continuously updates the values of stored coarse tuning information for each possible frequency, to correct for any drifts in the VCO's voltage/frequency characteristic. A VCO gain normalizer circuit amplifies the error signal coupled to the VCO by an amount that varies with the selected frequency, so as to correct for any non-uniformities in the apparatus' various elements, particularly the VCO, and to thereby provide a uniform loop gain.

Abstract: A phase-locked voltage controlled oscillator for generating frequency modulated waveforms having a programmable digital RF phase shifter to determine the phase difference between the output signal and a phase corrected reference signal to thereby generate the desired output waveform.

Abstract: A frequency synthesizer tuning circuit oscillator having an output signal frequency controlled by an input control signal is compared with the frequency specified by a source of data. The digital difference between the two compared frequencies comprises a multi-bit digital error signal of most and least significant bits. An error control signal for applying to the oscillator control input is derived by modulating the average pulse duration of a periodic pulse signal with the most significant bits of the digital error signal when the digital error signal is greater than a minimum frequency. The periodic pulse signal is amplitude modulated with the least significant bits of the digital error signal when the digital error is less than a maximum frequency. Both amplitude and pulse duration modulation of the periodic pulse signal occurs with the most and least significant bits of the digital frequency error signal when the frequency difference is between the maximum and minimum frequencies.

Abstract: An improved circuit for rapidly locking the phase of a reference signal e.sub.r of frequency f.sub.r with the phase of a signal e.sub.VCO in a phase locked loop which comprises a voltage controlled oscillator (VCO) for generating the signal e.sub.VCO of frequency f.sub.VCO, a divide-by-N circuit, for dividing f.sub.VCO by a variable N, a frequency/phase detector responsive to the phases of e.sub.VCO and e.sub.r to supply a control signal e.sub.c to the VCO, a loop filter circuit comprising a resistor and a capacitor for filtering e.sub.c, and logic for changing N to a new value N' in a time interval not less than T. Also provided is a circuit responsive to each change of N for coarse tuning the control signal supplied to the VCO and comprising a voltage generator responsive to each new value N' of N for generating a coarse tuned voltage having a magnitude which, when applied across the capacitor, will change the frequency f.sub.VCO /N to f.sub.VCO /N' to approximate f.sub.r.

Abstract: A disciplined oscillator system having a standard oscillator which is automatically corrected for both frequency errors and time error accumulation to a constant frequency signal which is derived from the WWVB carrier frequency and the WWVB TIME CODE to maintain overall frequency accuracy within one part in 10.sup.9 notwithstanding oscillator aging and in spite of jitter and distortion due to propagation delays and noise which may cause loss of, or time jitter in, the WWVB signals. Frequency errors are detected through the use of a counter (24) having a measurement accuracy greater than one part in 10.sup.10. An error detector (26) derives correction signals by averaging a plurality of frequency variances obtained in successive measurement cycles.

Abstract: A variable-frequency main oscillator of digitally tunable high output frequency f.sub.A is controlled by the integrated output voltage of a phase discriminator receiving on the one hand a relatively low comparison frequency and on the other hand a matching feedback frequency stepped down from output frequency f.sub.A by frequency division or by heterodyning with an auxiliary frequency f.sub.H of the same order of magnitude from an ancillary oscillator, a difference frequency f.sub.D =f.sub.A -f.sub.H is fed to a frequency discriminator delivering a corrective voltage, independent of that emitted by the phase discriminator through a filter network, to the control input of the main oscillator. A pair of frequency selectors varying the feedback frequency and/or the comparison frequency enable the output frequency f.sub.A to be adjusted in coarse and fine tuning steps, the coarse adjustments being also applied to the auxiliary frequency f.sub.H to limit the excursions of the difference frequency f.sub.D.

Abstract: A frequency prepositioning device for an indirect frequency synthesizer having switchable loops comprises an oscillator controlled by a voltage V.sub.N and at least one programmable prepositioning voltage generator. The device essentially comprises a memory device for storing the values of the prepositioning voltage at each transition to each frequency, thus making the device self-adaptive and capable of self-testing.

Abstract: Phase shifting apparatus is illustrated using a feedback loop to monitor the frequency and correct the phase shifting mechanism so that the desired amount of phase shift will occur at all frequencies. The phase shifter comprises a multistage storage means which samples the incoming signal periodically and outputs this information after a time delay. This time delay will vary for a given amount of phase shift depending upon the frequency. Thus, the feedback loop adjusts the sampling time whereby the time period of the sample times is electrically correct.

Abstract: In a frequency synthesizer phase locked loop including a reference oscillator, a variable reference divider (.div.M), a sample and hold phase detector, a loop filter, a voltage controlled oscillator and a variable divider (.div.N), a voltage converter for controlling the voltage of a control input to the voltage controlled oscillator is disclosed. In the preferred embodiment, the voltage converter has its input connected to the output of a first reference divider in the variable reference divider (.div.M) and its output connected to a control input (varactor diode) of the voltage controlled oscillator. The voltage converter clamps the divider reference signal from the first reference divider and provides a negative voltage level output to bias the varactor diode of the voltage controlled oscillator. Thus, the tuning range of the frequency synthesizer is increased.

Abstract: Apparatus for synchronizing the frequency of locally generated pilot signals with those of remotely generated pilot signals where frequency errors are introduced during transmission. A pair of demodulated pilot signals F1' and F2' are filtered and mixed to derive a third signal having a frequency equal to F2'-F1'. The difference frequency has no frequency error component so the third signal is used in a phase locked loop to regenerate a reference frequency (fr) signal.Two methods are disclosed to extract a control signal which is proportional to the error frequency. In one embodiment one of the received pilots (F1') is divided in frequency by 1/k1 and then subtracted from fr to yield 1/k1 times the error frequency df. By integrating this signal it becomes usable as an AFC signal to control a local oscillator.

Abstract: A frequency synthesizer having a delay line for a controlling element. The output frequency of a voltage controlled oscillator (VCO) is sampled with a directional coupler and input to an in-phase power divider. The first output of the power divider is input to a delay line to provide a delayed signal. The delayed signal and the non-delayed signal from the second output of the power divider are input to a phase detector. The output of the phase detector is a DC voltage representative of the phase difference between the delayed signal and the non-delayed signal. An analog gate inputs the phase detector output to an oscillator driver that controls the VCO. When the phase difference deviates from a predetermined level the oscillator driver outputs an error voltage to adjust the VCO until the proper phase difference is achieved which will be a condition of phase lock wherein the output frequency is phase locked to the delay line.

Abstract: The output frequency of a phase locked loop frequency synthesizer is measured by a counter which counts whole output cycles and a timer providing a signal proportional to a fractional output cycle during a sampling period. The counter output is stored into a latch at each sampling period. Calculated frequency is generated by an accumulator which is incremented a selectable integer N at the completion of each sampling period. The accumulator output is divided into a first part relating to whole cycles and a second part relating to fractional cycles. An adder takes the difference of the latch stored number and the accumulator output first part. The resulting difference, with the accumulator output second part restored thereto, comprises a coarse error signal in digital form. The digital coarse error signal is converted to analog and applied as one input to a summer. A second input to the summer is provided by the timer signal after being scaled proportionately to N in a multiplying D/A converter.

Abstract: A clock recovery system including a VCO responsive to a voltage signal for generating a clock signal. A phase detector includes a register and a PROM, the register counting the clock signal to derive the output clock signal. The PROM is responsive to input data and the count in the register to detect and store information concerning relative phase relationships. A counter contains a count from which the control voltage for the VCO is derived. The PROM is operable to alter the count in the counter, thereby performing frequency adjustments, and to alter the count in the register to perform phase adjustments. Also, a converter, operable by the phase detector, may also derive a voltage signal for damping purposes.

Abstract: An improved presettable integrator circuit is disposed in a fast frequency changing phase lock loop for presetting the voltage-controlled oscillator thereof as governed by a preset signal and a pulsed signal generated by a frequency controller. One input of the integrator circuit is coupled to the preset signal, another input is coupled to an integrator control signal, and the output is coupled to the voltage-controlled oscillator for use as a tuning signal thereof. A switch is included in the integrator circuit and is governed in a first state by the pulsed signal to cause the integrator circuit to respond rapidly to an applied preset signal to preset the output signal thereof. In a second state, the switch renders the integrator circuit responsive to an integrator control signal which is selected by a phase lock condition of the loop from either a reference signal or a filtered phase error signal, being coupled to the other input of the integrator circuit.

Abstract: A continuous wave pseudonoise radar system which employs a large word rate to avoid spillover and other noise. Spillover is the electromagnetic energy that is transmitted from the transmitting antenna directly to the receiving antenna. In other words, the spillover is not reflected from the target. The word frequency is thus made higher than the highest expected doppler. The high word rate would normally cause an ambiguous range indication because the word wavelength would be less than twice the maximum expected target range. However, this problem is solved by the use of coarse and fine range indicators. It is an outstanding feature of this invention that the coarse range is obtained by changing the transmitter bit rate. The difference between transmitter and receiver bit frequencies is then integrated over a selected period. The definite integral is directly proportional to range. However, the range turns out to be a function of the transmitter bit frequency only at the integral limits.

Abstract: A modulator for controlling the frequency of the power applied to a gyroscope to rotate the seismic mass (wheel) of the gyro so as to compensate for movement of the gyro case about the spin axis of the gyro is disclosed. The modulator includes a slow acting phase-locked loop that includes: a high frequency (e.g., 20 MHz) crystal controlled voltage controlled oscillator (VCXO); a divider for dividing the VCXO frequency down by several orders of magnitude (e.g., six); a phase comparator for comparing the relatively low frequency output of the divider with a low frequency reference signal; a loop filter for filtering the output of the phase comparator so as to give the loop its desired dynamic response chacteristic and bandwidth; and, a summing amplifier for summing the output of the phase comparator with a rate signal having a voltage level linearly related to the rate of movement of the gyro case about its spin axis.

Abstract: An automatic phase-controlled oscillator circuit for producing an output clocking signal whose phase and frequency vary with those of an input information signal applied thereto comprises an input circuit for receiving the input information signal; a variable-frequency tuning circuit for receiving a control signal and coupled to the input circuit for tuning on the basis of the frequency of the control signal to pass the information signal as a tuned signal; and a clocking signal generator, such as a phase-locked loop circuit, for providing the output clocking signal in dependence upon the phase of the tuned signal. The invention is favorably applied to a digital video tape recorder (DVTR) wherein the information signal is a digital signal reproduced from a tape as a result of relative motion between the tape and the DVTR, and the control signal is also reproduced from the tape to represent such relative motion.

Abstract: A signal of frequency value F.sub.IN is coupled to a discriminator and to one terminal of a voltage controlled oscillator (VCO) tuned to operate at a range of frequencies about F.sub.IN .div.N where N is a nonunity positive integer. The discriminator produces a voltage proportional to frequency F.sub.IN which is scaled and applied to a control terminal of the VCO to cause it to be tuned to approximately F.sub.IN .div.N. The signal of frequency F.sub.IN applied to the VCO causes it to be injection locked to frequency F.sub.IN .div.N.

Abstract: A microprocessor-controlled synthesizer has a low frequency section producing a first output frequency and a comb loop producing a second output frequency. The comb loop includes a multiplier which produces harmonics of 100 MHz one of which is selected and fed to a mixer in a phase-locked loop having a variable divider, the other input of the mixer being a VCO output frequency. At low values of the second output frequency, the phase detector locks to the difference output from the mixer, at higher values to the sum output. The output from the mixer is mixed in a second mixer with the output of a further VCO, and a second phase detector selects the sum output from the second mixer to cover the first half of each decade of MHz and selects the difference output to cover the second half of the decade.

Abstract: An improved automatic frequency control arrangement for a missile-borne inverse receiver is shown to include a reference oscillator and a voltage-controlled oscillator with control means for the latter, such means including a frequency-to-voltage converter responsive to the difference frequency between the two oscillators so that the latter may produce a signal representative of the Doppler shift frequency of a target. A starting circuit is also shown to ensure that the frequency of the reference oscillator is always lower than the frequency of the voltage-controlled oscillator.

Abstract: A phase locked loop tuning system for a television receiver includes a reference oscillator, a reference divider for dividing the frequency of the output signal of the reference oscillator, a voltage controlled local oscillator, a prescaler for dividing the frequency of the output signal of the local oscillator by a predetermined factor, a programmable divider for dividing the frequency of the output signal of the prescaler by a factor determined by the presently selected channel, a phase comparator for generating a series of pulses representing the phase and frequency relationships between the output signal of the reference divider and the output signal of the programmable divider and a low pass filter for deriving a control voltage for the local oscillator in response to the pulses generated by the phase comparator.

Abstract: The invention relates to phase locked loops in which a variable-frequency voltage-controlled oscillator (VCO) feeds a phase comparator via an adjustable divider having a division factor N. The comparator compares the phases of the divided frequency (Fd) and a reference frequency (Fr), and adjusts the VCO to produce phase equality. To enable the VCO frequency (FO) to be adjusted in smaller steps than Fr and yet maintain a loop bandwidth greater than the step size with good spurious performance (thus providing a "fractional N synthesizer"), Fo is made slightly more than N.Fr. The phase detector thus produces a phase error signal. At periodic instants, determined by the period of the frequency difference between Fo and N.Fr, a control unit temporarily increases N by unity so as to bring Fd and Fr into phase.

Abstract: A frequency synthesizer in which good resolution is obtained by a unity increase of the dividing ratio for a controlled proportion of the reference frequency cycles thus giving a fractional dividing ratio. Phase jitter that could be expected to result is eliminated by keeping a running count of the phase error produced by these changes of dividing factor and adding a corresponding voltage to the output of the phase comparator. Smoothing of the comparator output is thus no problem and the loop filter does not therefore have to have a narrow bandwidth. The loop bandwidth must be an order lower than the reference frequency and since now the loop bandwidth can be increased so can the reference frequency. The fractional dividing ratio ensures that the resolution is not limited by the reference frequency and thus the previously incompatible combination of fine resolution, wide loop bandwidth (for low phase noise) and a relatively unrestricted reference frequency is achieved.