Abstract: A clock recovery system includes a source of a data signal, and a free-running frequency adjustment circuit. The free-running frequency adjustment circuit includes an injection-locked oscillator having a free-running frequency and generating a clock signal and a phase locked loop, coupled in parallel with the injection locked oscillator, and generating a control signal adjusting the free running frequency of the injection locked oscillator.

Abstract: A high speed data communication system includes a receiver to recover data and clock signals from communicated data. The receiver circuit has a dual phase lock loop (PLL) circuit. A fine loop of the PLL includes a phase detector providing a differential analog voltage output. Transconductance circuitry converts the differential analog voltage output to a low current analog output. The transconductance circuitry has a variable gain which is controlled by an automatic gain adjust circuit. A coarse loop of the PLL allows for fast frequency acquisition of an internal oscillator.

Abstract: A frequency synthesizer that can accurately compensate for ripple current. The frequency synthesizer 1 having a PLL loop containing an oscillator 31 and a charge pump circuit 35 has a detector circuit 40 and a delay circuit 39. The detector circuit 40, by detecting a ripple current with a superimposed compensating current, detects the time difference between the output time of the compensating current and the output time of the ripple current, and since the delay circuit 39 delays one or both of the output time of the compensating current and the output time of the ripple current based on that detection result, the time difference for the output times can be made small, and if a compensating current is supplied that is equal to the ripple current, it becomes possible to accurately remove the ripple current.

Abstract: Methods and systems are disclosed for eliminating a phase transient of a controlled frequency oscillator, caused by replacing a first reference signal by a second reference signal when the first reference signal becomes corrupted or otherwise unavailable, and for running a controlled frequency oscillator in a frequency-controlled holdover mode. The contradictory requirements of using a relatively low-cost controlled frequency oscillator tunable over a relatively wide frequency range and achieving high stability of its frequency in holdover mode are satisfied.

Abstract: The Phase Locked Loop circuit of this invention has both a short locking time and a stable operation. This Phase Locked Loop circuit has two phase comparators. The inputs to these two comparators are a reference signal Vf and a feedback signal Vc. The first phase comparator has two separate outputs depending on the phase difference &dgr; between the signals Vf and Vc. The first output is a signal up1 when &dgr; is smaller than −&tgr;1, and the second output is a signal dn1 when &dgr; is larger than −&tgr;1. The second phase comparator also has two outputs depending on the phase difference &dgr; between the signals Vf and Vc. The first output is a signal up2 when &dgr; is smaller than −&tgr;2 (&tgr;2>&tgr;1), and the second output is a signal dn2 when &dgr; is larger than &tgr;2. The signals up1 and up2 are output when the &dgr; has positive polarity and large absolute value. When &dgr; has positive polarity and a small absolute value, only signal up1 is output.

Abstract: In the case of a tuning circuit for a YIG oscillator, wherein the output frequency of the YIG oscillator which is reduced by a frequency divider or mixer is compared in a phase detector with a lower reference frequency and via a loop filter the output voltage of the phase detector feeds the air-cored coil of the YIG oscillator serving for fine tuning, the main coil of the YIG oscillator is also fed by the output voltage of the phase detector.

Abstract: The invention relates to the locking of a phase-locked loop when the frequency setting (an) of the loop is changed. The locking speed of the loop is improved at the expense of noise characteristics so that these are momentarily degraded. When changing the frequency, the difference between the new frequency set for the VCO (430) and the actual frequency (fVCO) is measured and the VCO is immediately controlled according to this difference. To that end, counters (441, 444) dividing a reference frequency (fref) and the VCO frequency are made to simultaneously start counting from zero. Thus the length of the pulse issued by a phase difference detector (410) corresponds to the said frequency difference. After the setting of the new frequency value the loop filter (420) is turned into a purely capacitive circuit the output voltage (vc) of which changes proportionally to the length of the pulse from the phase difference detector.

Abstract: A self-biased phase-locked loop circuit includes a phase detector, first and second charge pumps, first and second loop filters, and a voltage-controlled oscillator (VCO). The phase detector is configured to measure a phase offset between two input signals, and to generate pulses corresponding to the phase offset. The first and second charge pumps are configured to provide charge corresponding to the pulses. The first and second loop filters are coupled to outputs of the first and second charge pumps, respectively. The filters operate to provide a control signal responsive to the charge. The VCO is configured to adjust its output frequency in response to the control signal. The second loop filter capacitor considerably improves the output clock jitter.

Abstract: A generator (50) able to be fitted to a clockwork system including a crystal (51a) used as a time base, includes a first oscillator (51) able to supply a first frequency (f1), a second oscillator (56) able to supply a second frequency (f2), a divider (60) able to supply a third frequency (f3) from the second frequency, a comparator (52) able to compare the third and first frequencies, and a control loop including a filter (54) connected to the comparator and able to control the second oscillator. The generator is characterised in that it includes a component (58) able to provide an indicator (LCK) containing the state of the loop, and in that the filter (54) can receive the indicator (LCK) and, in response, have a narrow (or respectively wide) band, when the loop is (or respectively is not) locked.

Abstract: In a frequency synthesizer 1 that has a high spurious component elimination ratio, if the integer frequency division value is changed and a fractional frequency division value is to be generated, rounding circuit 6 rounds the random number generated by random number generation circuit 7. Based on the integer value that is thereby generated, frequency division value control circuit 5 generates an integer frequency division value. Because the integer frequency division value changes based on a random number, there is no regularity, and spurious components are never generated in output signal OUT. Even if compensation circuit 37 generates a compensation current and superimposes it on the output of charge pump circuit 35, the influence of the ripple current output from charge pump circuit 35 cannot be completely eliminated.

Abstract: A voltage controlled oscillator circuit incorporating a closed loop coarse tuning mechanism. In this system, a reference oscillator is set with the desired frequency for the voltage controlled oscillator. A resulting voltage used to drive the oscillator is produced by a synthesizer connected in series with a loop filter. The resulting voltage is connected to a fine tune input of the voltage controlled oscillator and also to the input of an adaptive closed loop coarse tuning mechanism. The adaptive closed loop coarse tuning mechanism is comprised of an op amp configured in a noninverting feedback loop connected to a parallel resistor/adapt switch loop. The loop is followed by a shunt capacitor filter which is then connected directly to the coarse tune input of the VCO. If the adapt switch is closed, current from the coarse amp flows through a filter and to a coarse tune port of the VCO.

Abstract: Disclosed is a self-calibration device for calibrating a phase difference between output waveforms of a ring oscillator, comprising: a voltage-controlled oscillator adapted to adjust the transition time of an output signal according to an inputting of a control voltage for controlling the phase offset and generate the adjusted output signal; a divider adapted to divide a frequency of the output signal generated from the voltage-controlled oscillator by a fractional number to generate a plurality of output waveforms having different phases with them having an identical phase difference each other; a phase-locked loop (PLL) circuit adapted to correctly make a frequency and phase of the output signal of the divider coincident with those of a system clock, the phase-locked loop (PLL) circuit including at least a phase-frequency detecting means adapted to compare the frequency and phase of the output signal with those of the system clock and to output a result of the comparison; and a phase offset calibrating loop

Abstract: A voltage controlled oscillator circuit incorporating a closed loop coarse tuning mechanism. In this system, a reference oscillator is set with the desired frequency for the voltage controlled oscillator. A resulting voltage used to drive the oscillator is produced by a synthesizer connected in series with a loop filter. The resulting voltage is connected to a fine tune input of the voltage controlled oscillator and also to the input of an adaptive closed loop coarse tuning mechanism. The adaptive closed loop coarse tuning mechanism is comprised of an op amp configured in a noninverting feedback loop connected to a parallel resistor/adapt switch loop. The loop is followed by a shunt capacitor filter which is then connected directly to the coarse tune input of the VCO. If the adapt switch is closed, currentfrom the coarse amp flows through a filter and to a coarse tune port of the VCO.

Abstract: A frequency synthesizer has a voltage controlled oscillator comprising a voltage controlled capacitor having a first terminal and a second terminal. A positive control voltage is applied to the first terminal of the voltage controlled capacitor and a negative control voltage is applied to the second terminal of the voltage controlled capacitor, causing the varactor to operate in a reverse biased state. A circuit for generating a negative control voltage is provided in a phase-locked loop circuit. The circuit includes a negative DC generator for generating a negative DC voltage from an AC signal, and a programmable variable attenuator for selectably attenuating the negative control voltage.

Abstract: A phase lock loop (PLL) circuit has an oscillation circuit operating in synchronism with a horizontal synchronizing signal. The PLL circuit also has a DC level decision circuit for deciding the DC level of a vertical synchronizing signal during a return period, and a logic circuit for automatically selecting the oscillation circuit according to the DC level decided in the DC level decision unit. Thus, even if there is an increase in the oscillation characteristics, this PLL circuit can automatically select the necessary oscillation characteristics without a need for expanding an operation frequency of a voltage controlled oscillation circuit.

Abstract: A frequency synthesizer has a voltage controlled oscillator comprising a voltage controlled capacitor having a first terminal and a second terminal. A positive control voltage is applied to the first terminal of the voltage controlled capacitor and a negative control voltage is applied to the second terminal of the voltage controlled capacitor, causing the varactor to operate in a reverse biased state. A circuit for generating a negative control voltage is provided in a phase-locked loop circuit. The circuit includes a negative DC generator for generating a negative DC voltage from an AC signal, and a programmable variable attenuator for selectably attenuating the negative control voltage.

Abstract: A video display apparatus displays pictures from broadcast sources of standard or high definition pictures and may also display computer generated images. To display these sources a horizontal deflection signal generator is operable at a plurality of frequencies. The deflection signal generator comprises a controlled oscillator generating a output signal. A divider divides the output signal to form a horizontal frequency signal. A phase detector receives the horizontal frequency signal and a synchronizing signal and generates an analog signal for coupling to the oscillator. A digital to analog converter generates a voltage from a digital data word and couples the voltage to the oscillator. The voltage determines a center frequency of the oscillator and the analog signal controls the oscillator to synchronize with the synchronizing signal.

Abstract: There is described a stabilization process for the local oscillator frequency in wide-band tunable DROs employed in receivers of a digital microwave radio link. A microprocessor, already provided for normal operation control, cyclically reads the control voltage of a VCO inserted in PLL which reconstructs an intermediate frequency carrier used to coherently demodulate the received signal. The voltage read is compared with an optimal reference value by taking an error signal which controls a varicap diode of the DRO for tuning correction. With each reading, the optimal value can be modified on the basis of temperature data supplied by a heat sensor to cancel the effect of temperature on the reference.

Abstract: The disclosure describes a multi-stage phase comparator and a phase-locked loop incorporating such a comparator. The comparator measures a phase difference between a reference signal and an output signal using a periodic clock. The comparator is a two stage comparator comprising a fine and coarse comparator. The coarse comparator measures the number of full clock periods between a transition of the reference signal and the output signal. The fine comparator comprises a delay line generator that generates a plurality of delayed clocks. The delayed clocks are used to over sample the reference signal to determine a fine phase difference representing a remaining fraction of the clock period, between transitions of the reference and output signals. A phase locked loop using the multi-stage comparator allows for more accurate phase locking.

Abstract: A multi-band phase lock loop (PLL) device for use in a communication system. The PLL comprises a frequency reference oscillator, a reference frequency divider, a phase and frequency detector, a filter and compensation circuit, a microcontroller, a multi-band voltage controlled oscillator (VCO), and a feedback divider. A fast feedback signal is provided to the VCO for phase locking operation. A slow feedback signal is used by the microcontroller to generate a frequency adjust signal for frequency band centering for the VCO. The microcontroller also controls the VCO to change the frequency band of operation. The PLL device may be used in a communication system that operate in both the cellular frequency band and the PCS frequency band.

Abstract: A phase-locked loop circuit for locking the phase of an oscillator to the phase of a reference signal includes a multi-cycle phase detector (11) for detecting a phase difference between an input signal and said reference signal through multiple clock cycles and for sending a corresponding phase adjustment signal, and, a multiple current source charge pump (12) connecting to said phase detector for receiving said phase adjustment signal and sending a current signal depending upon said phase adjustment signal.

Abstract: A frequency standard generator for generating a high accuracy reference frequency by synchronizing a high accuracy atomic frequency standard or equivalent thereof and minimizing a phase difference between the generated reference frequency and the received atomic frequency standard.

Abstract: A system for compensating for reference frequency drift in a communications system. The inventive system includes a frequency source for providing a reference frequency. An error determination circuit determines if the reference frequency is within a predetermined range of a desired reference frequency and provides an error signal in response thereto. A frequency correction circuit steps the reference frequency up and/or down by a predetermined amount in response to the error signal until the reference frequency is within the predetermined range of the desired reference frequency. In a specific embodiment, the predetermined amount is twice the short-term capture range of the reference frequency which corresponds to approximately four parts per million. The predetermined range is the short-term capture range or two parts per million. The predetermined range is dependent upon the reference frequency band in which the receiver can successfully receive and decode the receive signal.

Abstract: A phase interpolated frequency synthesizer with on chip tuning includes a voltage controlled oscillator, a fractional-N divider, phase compensation and on chip tuning circuits, a phase detector, and a loop filter. The phase compensation and on chip tuning circuits compensate for the phase lag from the fractional-N divider. The phase compensation circuit can include a series of voltage controlled delay elements with the tuning circuit providing a control voltage.

Abstract: A phase-locked loop fabricated on an integrated circuit includes a phase/frequency detector, a charge pump, a filter node and a voltage-controlled oscillator (VCO) which are coupled together in series. The VCO has first and second frequency control inputs and a VCO output, wherein the first frequency control input is coupled to the filter node and the VCO output is coupled to the phase/frequency detector. The VCO has a first voltage-to-frequency gain from the first frequency control input to the VCO output and a second voltage-to-frequency gain from the second frequency control input to the VCO output. An off-chip filter input is coupled to the filter node for coupling to an off-chip loop filter. An on-chip loop filter is coupled between the first frequency control input and the second frequency control input and has a variable time constant. A time constant control circuit is coupled to the on-chip loop filter for controlling the variable time constant.

Abstract: Apparatus and methods for controlling the frequency spectrum of a clock signal, for example, to reduce EMI emissions. A PLL circuit receives a reference signal and generates an output clock signal. A modulating circuit is coupled to the PLL and generates a modulating signal. The PLL receives the modulating signal and accordingly varies the frequency spectrum of the output clock signal.

Abstract: A phase locked loop, which does not require a local reference clock to obtain a frequency lock. The circuit includes a frequency locked loop and a phase locked loop in which the frequency locked loop does not require a local reference clock. The frequency locked loop includes a transition counter having an input for data with an output connected to a charge pump. This charge pump is connected to a loop filter, which in turn is connected to a voltage controlled oscillator. The output of the voltage controlled oscillator is connected to a second input in the transition counter. The phase locked loop includes a phase detector with an input for data. The output of this phase detector is connected to a second charge pump, which has it output connected to the loop filter. The output of the voltage controlled oscillator also is connected to the input of the phase detector.

Abstract: A method and apparatus for biasing the voltage controlled oscillator (VCO) (110) of a Phase Locked Loop (PLL) (100) includes a bias circuit (114) providing a peak minimum/maximum voltage detector (202) tied to the control line (116) of the PLL (100). During operation, the detector (202) detects a minimum or maximum voltage on the VCO control line (116) as the bias control voltage (118) applied to the VCO (110) is varied. Detection of such a minimum or maximum voltage is equivalent to the detection of a minimum or a maximum frequency, which in turn equates to the detection of an optimal bias condition for noise.

Abstract: The invention provides a hybrid phase-locked loop (PLL) containing digital and analog portions for digital and analog adjustments, respectively, of an output signal. The hybrid PLL is simple in design. Off-the-shelf controlled oscillators, such as a current controlled oscillator (CCO) can be used with this hybrid PLL. The digital and the analog portions of the hybrid PLL are separate from the controlled oscillator. The digital portion is for a first adjustment of the frequency of the output signal, such as during a calibration. The analog portion is for fine phase and frequency adjustment of the output signal.

Abstract: A low-gain, low-jitter VCO circuit implemented in CMOS provides center frequency adjustment to overcome process variations. Further, noise immunity is improved by using a separate feedback loop to provide the nominal current biasing for the oscillator chain. This feedback loop coarsely sets the center frequency. The actual control of the oscillation frequency is achieved by a second current source, whose output is added to the nominal bias current to provide a total bias to the oscillator. This second current source "fine tunes" the oscillator frequency responsive to a control signal. Because two separate current sources are used, the circuit can realize a high oscillation frequency with a low VCO gain. Another feature provides for adjusting the center frequency in response to a digital input word provided via external pins, or from internal logic or memory. The center frequency thus can be calibrated by measurement at the time of manufacture, or changes later by the end user or by other circuitry.

Abstract: A 1-port tunable frequency discriminator that is incorporated into a frequency lock loop (FLL) for providing an improved FLL having reduced phase noise and settling times is provided. The invented 1-port tunable delay line discriminator reduces the phase noise generated by VCO's to approximately 105 dBc/Hz at 10 kHz, to better than 120 dBc/Hz at 100 kHz. The invention additionally reduces post tuning drift to less than 10 kHz after one microsecond. A secondary feedback loop, such as a conventional phase lock loop, can be incorporated into the invented FLL for providing phase and frequency coherency. The invention is formed by coupling a voltage controlled oscillator source (VCO) to a microwave signal detector and to an open ended delay line. When a microwave signal generated by the VCO reaches an end of the open ended delay line, a majority of the signal is reflected back along the line.

Abstract: A voltage controlled current source provides controlled current to a current controlled oscillator in a high frequency phase-locked loop clock generator. The voltage controlled current source receives a first control signal and a set of second control signals indicative of a phase difference between the output signal of the clock signal generator and a reference frequency. It uses those control signals to adjust the current-controlled oscillator. A level shifter coupled to the current-controlled oscillator amplifies the oscillator signals to full rail and adjusts the duty cycle at its output to 50% to produce the clock signal generator output signal.

Abstract: A self-tuning clock recovery phase-locked loop (PLL) includes a programmable divide-by-M, a phase-frequency detector, a programmable voltage-controlled oscillator (VCO), a programmable divide-by-N, and a PLL tuning circuit, which in normal mode operation, perform as a conventional PLL. When the frequency of an input clock signal to the PLL changes by more than a threshold value, however, the PLL tuning circuit causes the PLL to be retuned for the new frequency by adjusting offset and gain parameters in the PLL such that the input voltage to the VCO is mid-way in its input voltage range when the output clock frequency of the PLL is approximately equal to the input clock frequency multiplied by a closed loop gain of the PLL, so that the VCO is operating in a linear region having wide dynamic frequency range.

Abstract: A Radio Frequency (RF) transponder (tag), method, and system, whereby the tag has a low current tag oscillator, the oscillation frequency of the tag oscillator set by RF signal from a base station.

Abstract: A signal processing apparatus has a clock generator that generates a clock in accordance with the rate at which picture elements are scanned. The clock generator includes a first frequency divider for dividing the output frequency of a voltage-controlled oscillator for generating the clock, a second frequency divider for dividing the output frequency of a reference frequency oscillator, a phase comparator for comparing phases between the outputs of the first and second frequency dividers, means for applying the output of the phase comparator to the reference frequency oscillator as a control signal, and a third frequency divider for performing voltage division on the output of the voltage-controlled oscillator to obtain the clock. The clock obtained has a frequency determined as: ##EQU1## where M, N, and P represent the frequency-division ratios of the first, second, and third frequency dividers, respectively, and f.sub.x represents the reference frequency.

Abstract: A programmable apparatus is disclosed for generating a frequency modulated signal at a selected center frequency in accordance with digital data of at least first and second data levels. The modulating apparatus comprises a modulator having an input and an output and is responsive to an input modulation signal applied to its input for generating at its output the frequency modulated signal at a center frequency dependent on a quiescent voltage appearing at its input. A circuit is provided for sampling and storing a value of the quiescent voltage. An addressable memory stores a plurality of offsets. A programmable adding circuit adds a downloaded offset voltage to the stored value of the quiescent voltage to output a high modulation voltage. A programmable subtracting circuit subtracts a downloaded offset voltage from the stored value of the quiescent voltage to provide a low modulation voltage.

Abstract: A mechanism for reducing a frequency transient appearing at the output of a voltage controlled oscillator (VCO) in a frequency synthesizer when a load is connected to the VCO. In accordance with the present invention, the magnitude and direction of (a) the frequency transient and (b) the frequency deviation of the VCO signal in response to a reference input voltage may be measured, and those measurements used to generate a frequency correction voltage which would cause the VCO signal to deviate in an equal amplitude but in an opposite direction to the frequency transient. The frequency correction voltage then can be applied to the VCO when it is connected to the load so as to substantially cancel the frequency transient.

Abstract: A VCO (Voltage Controlled Oscillator) (10) operates in a phase-locked loop at a desired frequency. One input to the VCO is a variable control signal (24) that holds the VCO at the desired frequency. Another input is a bias input (40) that changes the operating point of a transistor (34) in the VCO and also tends to change the VCO's frequency. The value of the variable control signal (24) is sensed while the bias input (40) is changed until a desired, minimum value of the control signal is sensed. The value of the bias input at that point is held constant while operating the VCO at the desired frequency and with minimal side band noise.

Abstract: An integrated circuit phase-locked loop includes a phase/frequency detector, a charge pump, and a voltage-controlled oscillator (VCO) which are coupled together in series. The VCO has first and second VCO control inputs, and has a VCO output which is coupled to the phase/frequency detector. An off-chip loop filter input is coupled between the charge pump and the first VCO control input for coupling to an off-chip loop filter. An on-chip loop filter is coupled between the first VCO control input and the second VCO control input. The VCO has a lower voltage-to-frequency gain from the first VCO control input to the VCO output than from the second VCO control input to the VCO output.

Abstract: In a frequency synthesizer, a variable frequency divider divides the oscillation signal of a VCO while switching the frequency dividing ratio in accordance with an integral frequency dividing ratio generated by a frequency dividing ratio generating circuit. The VCO is controlled with an output of a loop filter. The frequency dividing ratio generating circuit includes multiple integrators connected in cascade and differentiators which differentiate the carry-out signals of the integrators, so that a phase error generated at the variable frequency divider is obtained from an output of an adder included in the final stage integrator of the frequency dividing ratio generating circuit. A phase error compensation value is output, and further a pulse width of a signal to be used for compensating for phase error is varied in accordance with the phase error compensation value to perform compensation for the phase error.

Abstract: A fractional N-frequency synthesizer includes an accumulator outputting an output value, and a spurious signal cancel circuit. The spurious signal cancel circuit includes a pulse forming circuit, receiving a spurious signal cancelling reference signal, a reset signal and the output value of the accumulator, and outputting, in synchronism with the spurious signal cancelling reference signal, a pulse voltage signal having a pulse width proportional to the output value of the accumulator from a time when the reset signal is received, and a constant current circuit controlled by the pulse voltage signal and outputting an output current of the spurious signal cancel circuit.

Abstract: The present invention provides an adaptive signal conditioning device for a CXO crystal oscillator comprising a means for sensing acceleration, a band filter and a means for magnitude and phase compensation, with the means for magnitude and phase compensation having and an analog circuit represented by a transfer function, H(s), which adjusts a tuning signal's magnitude and phase, according to specific vibration frequency ranges, and produces a vibration cancellation signal in the presence of varying vibration frequencies, matching the vibration cancellation signal's frequency response to the frequency response of unwanted vibration-induced phase noise. The desired magnitude and phase of the tuning signal are determined with an adjustable identification device that is vibrated.

Abstract: An oscillating apparatus includes a quartz crystal oscillator for outputting a reference frequency signal; a phase-locked loop for oscillating a desired frequency signal on the basis of an output from the quartz crystal oscillator, a unit for detecting vibration components added to the quartz crystal oscillator, a unit for variably controlling phases and levels of the detected vibration components, a unit for obtaining a correlation value between the detected vibration components and vibration components in the phase-locked loop to variably control the phases and the levels, and a unit for controlling the phase-locked loop on the basis of the phases and levels of the vibration components which are variably controlled.

Abstract: A method and apparatus for adjusting the parameters of a PLL in a communication system. The method measures the rate of transmission of clock reference information by measuring the time of arrival of successive clock references or the difference of the clock reference values. The method applies the measured transmission rate to a plurality of predefined transmission rate ranges to acquire the proper gain factor values. These gain factor values are used to control the responsiveness of the PLL to new clock reference information.

Abstract: A dual VCO phase-locked loop in which one VCO forms part of a standard phase-locked loop, the VCO being controlled by a loop control voltage and its output being divided and compared with an input reference signal for maintaining lock. A second VCO is indirectly controlled by the loop control voltage and tracks the output of the first VCO within .+-.5% over combined variations in power supply voltage from 3.0 V to 3.6 V, in ambient temperature from 20.degree. C. to approximately 125.degree. C., and in manufacturing process variations over 5 process corners (typical, fast-fast, slow-slow, slow-fast and fast-slow). A control current is developed for the VCO forming part of the closed loop and is coupled to the second VCO using a current mirror. An offset current is combined at the second VCO with the coupled control current. The offset current is intentionally made a compensating function of the variations in power supply voltage, ambient temperature and manufacturing process.

Abstract: A variable frequency oscillator circuit includes a ring oscillator circuit, a plurality of adjustment means for adjusting an output frequency of the ring oscillator circuit, at least one of the adjustment means having monotonic behavior, adapted to switch between first adjustment levels at a first rate and at least one of the adjustment means having non-monotonic behavior, adapted to switch between second adjustment levels at a second rate which is less than the first rate, such that the means having monotonic behavior adjusts for monotonicity errors which occur during switching.

Abstract: A PLL circuit (401), including a VCO (420) having a trimming port (418) and a tuning port (416), a PLL controller (404), a variable voltage source (408), a voltage measuring circuit (426) and a multiplexer (412, 414, 428), performs automatic trimming of the VCO (420). The PLL circuit (401) accomplishes this by initiating a trimming mode that controls the multiplexer so that it couples the output of the PLL controller (404) to the trimming port (418), and the output of the variable voltage source (408) to the tuning port (416), thereby to phase lock the VCO (420) to the reference frequency signal (421). The PLL circuit (401) then measures, by way of the voltage measuring circuit (426), a voltage at the trimming port (418), switches the PLL circuit (401) to an operational mode, and then adjusts the variable voltage source (408) to be substantially equal to the voltage measured.

Abstract: A programmable phase shift clock generator is disclosed including a phase comparator, an up-down counter, a ring oscillator, and an adjustable delay line for determining a digital signature of an input clock and precisely generating a phase shifted clock signal.

Abstract: An oscillating apparatus includes a quartz crystal oscillator for outputting a reference frequency signal, a phase-locked loop for oscillating a desired frequency signal on the basis of an output from the quartz crystal oscillator, a unit for detecting vibration components added to the quartz crystal oscillator, a unit for variably controlling phases and levels of the detected vibration components, a unit for obtaining a correlation value between the detected vibration components and vibration components in the phase-locked loop to variably control the phases and the levels, and a unit for controlling the phase-locked loop on the basis of the phases and levels of the vibration components which are variably controlled.

Abstract: An FM demodulator demodulating an FM modulated input signal through a PLL circuit, which includes a phase comparator a loop filter, a DC amplifier, a BB amplifier, and a VCO, and outputting the demodulated signal further includes a feedback circuit connected in parallel to DC amplifier and having a resistance which is a function of an external control voltage. The feedback circuit may be connected in parallel to both DC amplifier and BB amplifier. A PIN diode is typically used as a resistance variable element in the feedback circuit.