Abstract: Method and system are disclosed for automated calibration of the VCO gain in phase modulators. The method and system of the invention comprises synthesizing, in a phase modulator, a signal having a given output frequency using a controlled oscillator having a frequency control input, a modulation input, and a feedback loop. A frequency control signal is applied to the frequency control input, and gain variation of the controlled oscillator is compensated for outside of the feedback loop via the modulation input. The method and system of the invention may be employed in any telecommunication system that uses phase and amplitude modulation, including EDGE and WCDMA systems.

Abstract: In a dual loop PLL having a frequency comparison loop and a phase comparison loop, when an input control circuit 30 of an up/down counter 8 receives an UP signal from a frequency comparator 7, the input control circuit 30 outputs a positive value of a ½ of a previous addition/subtraction result value. When the input control circuit 30 receives a DOWN signal from the frequency comparator 7, the input control circuit 30 outputs a negative value of a ½ of the previous addition/subtraction result value. A register 33 stores a count value. The adder 31 adds the output of the input control circuit 30 to the output of the register 33. Thus, the up/down counter 8 increments or decrements by a ½ value of the previous addition/subtraction result value, and the dual loop PLL performs a frequency comparison based on a dichotomizing search method. Therefore, even when the output frequency is high, the frequency comparison is efficiently performed, and the lock up time is reduced.

Abstract: An improved coarse tuning process for fractional-N frequency synthesizers is provided. In general, a coarse tuning circuit controls a phase lock loop (PLL) of a frequency synthesizer. During coarse tuning, a reference signal used to control an output frequency of the PLL is provided to the coarse tuning circuitry and is divided by a factor M to provide a divided reference signal. A controllable oscillator (CO) output signal from a CO in the PLL is divided by an N divider in the PLL to provide a divided CO signal. The periods or, equivalently, frequencies of the divided CO signal and the divided reference signal are compared, and the result is used to select an appropriate tuning curve for the CO. In order to reduce a period comparison error, synchronization circuitry operates to synchronize the N divider of the PLL and an M divider of the coarse tuning circuit.

Abstract: A reference timing signal apparatus with a phase-locked loop (PLL) has a computer algorithm which adaptively models the multiple frequencies of an oscillator following a training period. The oscillator is part of a PLL and the oscillation frequency thereof is controlled in response to the phase detector output. The computer algorithm processes the control signal applied to the oscillator. The computer algorithm updates the characteristics of the model relating to the aging and temperature of the oscillator, using for example, a Kalman filter as an adaptive filter, in accordance with a cumulative phase error in the PLL calculated during a given time interval. By the algorithm, the subsequent model predicts the future frequency state of the oscillator on which it was trained. The predicted frequency of the model functions as a reference to correct the frequency of the oscillator in the event that no input reference timing signal is available.

Abstract: Techniques for direct modulation of a voltage-controlled oscillator (VCO) with adaptive digital gain control for wideband wireless applications are disclosed. A digital adaptive gain control loop is used to directly modulate the VCO, and a phase-locked loop (PLL) to track the frequency drift and other nonlinear effects of the VCO. As the PLL is applied to track the carrier frequency without passing the modulation signal into the PLL loop filter, the PLL can be implemented with a narrow loop bandwidth. The wideband frequency modulated signal is directly up-converted to the radio frequency (RF) signal by directly modulating the VCO through a digital-to-analog converter which is digitally controlled by an adaptive gain control loop. Thus, both wide bandwidth and low output noise for a frequency synthesizer and modulator can be achieved.

Abstract: A low phase noise YIG oscillator based phase locked loop couples an output frequency to a delay line discriminator to provide a phase noise feedback signal to a wideband tuning port of the YIG oscillator. A delay line in the delay line oscillator may be implemented with either a resonant circuit or a bandpass filter of sufficient bandwidth so that the output frequency and phase noise sidebands are not attenuated. The resonant circuit may be implemented as a YIG sphere integrated into the YIG oscillator in the same magnetic path as the YIG sphere in the oscillator circuitry.

Abstract: A cycle slip detector interfaces with a phase/frequency detector (PFD), such as might be used in a phase-locked loop circuit (PLL), and indicates when cycle slips occur in the PFD. Typically, the PFD generates output control signals as a function of the phase difference between first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD provides linear phase comparison between its input signals, provided their relative phase difference does not exceed ±2? radians. If one of the two signals leads or lags the other by more than that amount, a cycle slip occurs, and the PFD responds nonlinearly. The cycle slip detector provides logic for detecting and indicating leading and lagging cycle slips as they occur in the PDF, and is typically implemented as a minimal arrangement of logic gates and flip-flops.

Abstract: An apparatus comprising a circuit configured to generate a spread spectrum clock signal. The circuit may comprise a voltage controlled oscillator with a gain that may be automatically controlled.

Abstract: The present invention relates to a charge pump, in particular for use in a tuning system including a phase-locked loop, for generating currents, including a current amplifier, wherein the current amplifier includes a translinear circuit.

Abstract: An automatic frequency controller restores symbols carried on a received signal by a data converter, and uses an in-phase and a quadrature component obtained by phase measurement from the symbol restored by the data converter to calculate first and second phase errors. The first and second phase errors are summed together by an adder to produce a phase error of a waveform more moderate than the first phase error to decrease and increase error correction in the ranges of smaller and larger phase errors, respectively, to elongate a period of positive amplitude to expand the desired range of polarity of the phase error. A multiplier multiplies the result from the summation with a coefficient to normalize it. An integrator integrates the normalized data to produce a control signal for use in restoring the symbols.

Abstract: An electronic device, such as a microprocessor, with a timing circuit. The timing circuit contains a phase locked loop that, during a first interval, checks whether a control signal in the phase locked loop is between a maximum allowed value and a minimum allowed value. When the control signal in the phase locked loop is above a maximum allowed value or below a minimum allowed value, the control circuit disables the phase locked loop for a second interval. When the control signal in the phase locked loop is below a maximum allowed value and above a minimum allowed value, the timing circuit indicates that the output of the phase locked loop is stable.

Abstract: The invention discloses an injection synchronization narrowband regenerative phase-locked loop (ISNRPLL) circuit. The circuit includes a synchronous oscillation loop composed by the connecting of an injection synchronization narrowband regenerative voltage-controlled oscillator (ISNRVCO) and an exclusive-OR double frequency circuit; a phase-locked loop composed by the connecting of a digital phase detector, a charge pump and a loop filter, and a D type flip-flop for outputting data. The ISNRVCO does not ask much of the syntonic loop, and can be implemented by integrating inductance on a chip. Preferably, it can be integrated completely by using the deep submicron digital CMOS technology, so there are only a few external elements. Simulation shows that the capture range, capture time and phase noise etc. of the INSRPLL are all better than the conventional phase-locked loop circuit and can be used in GHz level high-speed clock recovery integrated circuit.

Abstract: A communications system using a phase locked loop employing two-point modulation is disclosed. The phase locked loop further includes a master oscillator having an output operably coupled to a first input of the phase detector; a slave oscillator having an output operably coupled to a second input of the phase detector, and a forward-gain-adaptation module having a first input operably coupled to the raw-error terminal of the phase detector.

Abstract: The invention relates to a device and a method for producing an oscillator signal based on a base signal. Said oscillator signal is actively constructed by an oscillator. The oscillator can be quasi-phase-coherently excited by the base signal.

Abstract: The present invention is related to a fast frequency locking method and architecture realized by employing adaptive asymmetric charge-pump current mechanism, whose circuit is composed of elements such as: a pair of frequency-dependent main current sources, a pair of (rising, descending) frequency-dependent assistant current sources, a digital control circuit, a voltage controlled oscillator, an impedance, a sampling frequency sampled from output frequency of the voltage controlled oscillator, a fixed reference frequency and a phase detector, etc. The difference between the present invention and traditional charge-pump circuit is that the present invention had added at least one pair of frequency-dependent assistant current sources.

Abstract: A voltage-controlled oscillator device with an LC-resonant circuit, in particular for implementing integrated voltage-controlled oscillators for the lower GHz range, is disclosed. The device achieves continuous frequency tunability in a wide range in particular with a low level of phase noise and phase jitter. In the voltage-controlled oscillator, a second inductor can be periodically switched in parallel and/or in series with at least one first inductor of the LC-resonant circuit by way of a switching means actuated with the oscillator frequency. A control input of the switching means is connected to a variable dc voltage. In that respect the relationship of the duration of the conducting state and the duration of the non-conducting state of the switching means is variable within an oscillation period of the oscillator in dependence on the value of the control voltage.

Abstract: Dual loop phase lock loops having a high loop bandwidth with low power consumption are described. Each loop is provided with a voltage supply regulator circuit which regulates the voltage of a portion of each loop. In one embodiment, the outer loop employs a regulation circuit comprising a two stage operational amplifier which is compensated by a compensation circuit that is configured to ensure that the dominant pole of the operational amplifier is associated with the first stage of the operational amplifier.

Abstract: In one embodiment, a control loop in an electrical circuit includes a variable feed-forward circuit configured to determine a setting of a variable oscillator that would result in a frequency of a first signal approximating a frequency of a second signal. The setting may be used to control the variable oscillator at a time when a phase error between the first signal and the second signal is negligibly small (e.g., substantially zero), thus allowing for relatively short loop convergence time.

Abstract: A phase locked loop for recovering a clock signal from a data signal including a delay locked loop with a nonlinear digital phase detector. The delay locked loop that is embedded in the phase locked loop acts like a linear phase detector. The phase locked loop of the present invention can be produced at low cost and is particularly suitable for use in data communication.

Abstract: A densitometer using a light-to-frequency converter is disclosed. The converter outputs an oscillating signal with frequency characteristic of the incident light intensity. Digital controls may be input to the converter to set the frequency range of the output. The period count or frequency count of the converter output may be numerically divided to obtain a quotient within a small range. A lookup table is addressed according to the period count or frequency count, and return an offset scaled logarithm. The lookup table output is processed numerically to obtain a scaled density value. The converter may be adapted to process analog voltage inputs rather than light inputs. The logarithmic conversion then becomes applicable to a variety of fields besides densitometry.

Abstract: A system for coarsely tuning at least one voltage controlled oscillator (VCO) (211) in a phase locked loop (PLL) synthesizer (200) that includes a phase-frequency detector (PFD) for determining a phase difference between a VCO frequency and a reference frequency and providing an error signal if the VCO frequency and reference frequency are at least 2&pgr; radians out of phase. A monitor (215) is then used for tracking the number of error signals produced by the PFD. The free running frequency of the VCO may be coarsely tuned in the event the monitor circuit reaches some predetermined level. The invention offers great advantage in enabling a PLL to be coarsely tuned to enable the PLL's VCO to remain with an operational range despite operational factors that effect circuit operation.

Abstract: A delay-locked loop includes a ring oscillator that generates a plurality of tap clock signals, with one tap clock signal being designated an oscillator clock signal. Each tap clock signal has a respective delay relative to the oscillator clock signal. The oscillator clock signal clocks a coarse delay counter to develop a coarse delay count that determines a coarse delay of a delayed clock signal. A fine delay of the delayed clock signal is determined by selecting one of the tap clock signals of the ring oscillator. The phase between an input clock signal and the delayed clock signal is determined and the coarse and fine delays adjusted in response to this phase to synchronize the delayed and input clock signals. The delay-locked loop may also monitor rising and falling edges of the input clock signal and develop corresponding rising-edge and falling-edge fine delays to synchronize rising and falling edges of the input clock signal.

Abstract: A frequency synthesizer, a calibrator thereof, and an operating controller thereof are described. The synthesizer comprises a main charge pump that drives a voltage controlled oscillator (VCO) through a loop filter. The calibrator includes a second, replica charge pump that can also drive the VCO, but is set up to output only its maximum or minimum analog output control voltage. Since the construction and characteristics of the replica charge pump duplicate the main charge pump, the main charge pump's minimum and maximum analog control outputs can be cloned out to the VCO on demand. A VCO calibration procedure therefore includes switching the VCO to each of its ranges set by a bank of fixed capacitors, and using the replica charge pump to drive the VCO to its minimum and maximum frequency for each range setting.

Abstract: A phase locked loop (PLL) for reducing electromagnetic interference (EMI) is provided. The PLL is not sensitive to a manufacturing process, consumes less power, occupies a small layout space, and can flexibly control a modulation frequency and a modulation rate flexibly. The PLL for reducing the EMI controls the signals having a phase difference, which is n-times (where n is an integer) the basic delay time of the output signals from a voltage controlled oscillator (VCO), and determines the modulation rate. Then, the PLL repeats the procedure during the cycle of a pre-defined modulation frequency. The PLL for reducing the EMI not only reduces the EMI, but also does not require a ROM. Therefore, the layout space can be reduced and broad frequency ranges can be obtained. In addition, since the phase difference of the output signals of the VCO is controlled by logic circuits, the PLL is insensitive to changes in the manufacturing process.

Abstract: A frequency synthesizer comprising a phase-locked loop (10) and comprising: a frequency divider (14) having integral dividing ratios, a sigma-delta modulator (30) connected to the frequency divider for obtaining a resulting mean dividing ratio having a fractional component, the modulator having an input for an adjusting instruction, and at least a frequency divider (100) having a fixed fractional dividing ratio, and means (120, 40) for activating the divider having a fractional dividing ratio when the fractional component (k) of the mean dividing ratio is contained in at least a given value range, and for modifying the adjusting instruction in corresponding manner.

Abstract: A frequency sythesizer and a method for synthesizing a signal having a given output frequency includes providing a controlled oscillator having a frequency control input and a feedback loop, applying a frequency control signal to the frequency control input, and compensating gain variation of the controlled oscillator outside of the feedback loop.

Abstract: An internal frequency reference, such as a VCO used in a PLL, having a free-running frequency fairly well controlled within a predictable range, is used as a rough frequency reference to determine, for an externally-provided frequency reference signal, which of a finite number of discrete frequencies is currently received. The VCO has a frequency range which varies less, as a percentage, than the ratio between possible reference frequency values. Consequently, the VCO is used as a frequency reference to measure the frequency reference signal. An internal signal is generated to indicate to remaining circuitry which of the possible reference frequencies is actually being provided, without requiring use of any dedicated input pins to receive a select signal. An integrated circuit device may be configured for different modes of operation as a function of which reference frequency is provided to the device.

Abstract: An oscillation frequency of a VCXO is controlled based on a phase difference between a reference phase signal outputted from a reference phase generation circuit and a feedback phase signal outputted from a feedback phase generation circuit, an oscillation frequency of a VCO is controlled based on a phase difference between an output clock of the VCXO and an audio clock obtained from a divider circuit, and a clock outputted from the VCO is determined as a restored audio clock.

Abstract: The invention relates to the locking of a phase-locked loop when the frequency setting (an) of the loop is changed. The locking speed of the loop is improved at the expense of noise characteristics so that these are momentarily degraded. When changing the frequency, the difference between the new frequency set for the VCO (430) and the actual frequency (fVCO) is measured and the VCO is immediately controlled according to this difference. To that end, counters (441, 444) dividing a reference frequency (fref) and the VCO frequency are made to simultaneously start counting from zero. Thus the length of the pulse issued by a phase difference detector (410) corresponds to the said frequency difference. After the setting of the new frequency value the loop filter (420) is turned into a purely capacitive circuit the output voltage (vc) of which changes proportionally to the length of the pulse from the phase difference detector.

Abstract: A phase locked loop (PLL) frequency synthesizer generates a high frequency signal by generating an output signal from a voltage controlled oscillator of a primary phase locked loop (PLL) circuit. The voltage controlled oscillator output is programmably divided with a reference signal output at a divide ratio such that the outputs are equal to a common phase comparison frequency. An external reference signal used for the primary phase locked loop circuit is isolated by generating a voltage controlled, clean reference signal and filtering and synchronizing the clean reference signal with the external reference signal within a secondary phase locked loop circuit to produce the reference signal output to the primary phase locked loop circuit.

Abstract: A circuit for monitoring and controlling input to a VCO, comprises: (A) a monitoring sub-circuit for monitoring input; (B) a stepping sub-circuit for stepping the VCO's frequency range; (C) an input reduction sub-circuit for reducing input into the monitoring sub-circuit; and (D) a VCO.

Abstract: A frequency detector is configured to provide reliable acquisition by a clock recovery and data regeneration circuit. A preferred frequency detector utilizes the output characteristics of a phase detector to determine a frequency difference between the recovered clock signal and the incoming data signal. The frequency detector then outputs a signal representing the frequency difference to a control device, preferably to a voltage-controlled oscillator (VCO). Upon receiving the frequency difference signal, the control device, preferably operating within a controlled-feedback loop, will begin to adjust the underlying clock frequency to approximate the incoming data frequency.

Abstract: In the case of a tuning circuit for a YIG oscillator, wherein the output frequency of the YIG oscillator which is reduced by a frequency divider or mixer is compared in a phase detector with a lower reference frequency and via a loop filter the output voltage of the phase detector feeds the air-cored coil of the YIG oscillator serving for fine tuning, the main coil of the YIG oscillator is also fed by the output voltage of the phase detector.

Abstract: Disclosed is a PLL circuit that makes fractional frequency division possible without causing spurious components to be produced in the output of a VCO. The PLL circuit comprises a frequency dividing circuit for frequency-dividing the output of a VCO; a phase adjusting circuit, to which are input two clocks of different phases obtained by frequency division performed by the frequency dividing circuit, for producing an output signal having a delay time defined by a time that is the result of internally dividing a timing difference between the two clocks; a charge pump for generating a voltage conforming to a phase difference output from the phase comparator circuit; and a loop filter for smoothing the voltage conforming to the phase difference and applying the voltage to the VCO, wherein the dividing value of the timing difference in the phase adjusting circuit is represented by MF/MD, and an accumulation operation is performed in units of MF every frequency-divided clock.

Abstract: An oscillator generates an oscillation signal, and a phase shifter outputs a phase shift oscillation signal corresponding to a difference between a frequency of the oscillation signal and a target frequency. A multiplier outputs a multiplied signal corresponding to a multiplied value of the phase shift signal and the oscillation signal, and an error signal generator outputs an error signal according to the multiplied signal. The output frequency of the oscillator is controlled according to the error signal.

Abstract: A fast lock/self-tuning VCO based PLL integrated circuit (10) adapted for implementation in wireless communication systems requiring a high transfer data rate. The present invention is preferably implemented using and RFSiGe or a CMOS process in a WDCMA chipset, and can be used in other systems such as GSM and EDGE. The present invention utilizes the content of a divider (24) as a monitor of the lock condition of the PLL (10), permitting the fast-tuning of the VCO (14) to almost the final frequency using a controller (22) and a coarse DAC (20).

Abstract: In a frequency synthesizer 1 that has a high spurious component elimination ratio, if the integer frequency division value is changed and a fractional frequency division value is to be generated, rounding circuit 6 rounds the random number generated by random number generation circuit 7. Based on the integer value that is thereby generated, frequency division value control circuit 5 generates an integer frequency division value. Because the integer frequency division value changes based on a random number, there is no regularity, and spurious components are never generated in output signal OUT. Even if compensation circuit 37 generates a compensation current and superimposes it on the output of charge pump circuit 35, the influence of the ripple current output from charge pump circuit 35 cannot be completely eliminated.

Abstract: A system for controlling an output frequency of a dual-input voltage controlled oscillator relative to a reference frequency is provided. The method includes the step of coupling a first tune control signal to a first input of the dual-input voltage controlled oscillator. The method further includes the steps of dividing the output frequency of the dual-input voltage controlled oscillator by a value substantially equal to a second tune control signal, comparing a phase of the divided output frequency with a phase of the reference frequency and coupling a phase difference of the compared phases to a second input of the dual-input voltage controlled oscillator.

Abstract: A system and method for synchronizing a plurality of synchronizable oscillators are disclosed. The method includes monitoring a respective output signal of each synchronizable oscillator, each output signal having a respective frequency, generating a synchronization signal based on the output signal having the highest frequency of all of the output signals, and providing the synchronization signal to all of the synchronizable oscillators.

Abstract: A Phase-locked Loop (PLL) (204) that is dynamically and automatically altered in response to changes in the jitter of the input is disclosed. The Analysis Block (304) receives one or more inputs from the PLL operation. The output of the Analysis Block (304) triggers a change in the Parametric Control Block (308) which in turn imparts changes on the gains of one or more of the various components or the value of &ohgr;N of the PLL Low Pass Filter (116). The dynamic change to at least one parameter of the PLL adjusts the tradeoff between removing as much of the jitter as possible and having a responsive system that has a reduced risk of buffer underflow or overflow. This abstract is provided as a tool for those searching for relevant disclosures, and not as a limitation on the scope of the claims.

Abstract: A phase-locked loop (PLL) includes a voltage controlled oscillator (VCO) and a pair of charge pump circuits (CP) and provides a stable oscillation clock signal. A phase comparator compares a reference clock signal with an oscillation clock signal generated by the VCO and generates two comparison signals. The comparison signals are input to the first CP, which generates a first CP output signal. The first CP output signal is filtered with a first low pass filter (LPF) and the filtered signal (control voltage) is provided to the VCO, which produces the oscillation clock. The second CP receives two clock signals and generates a second CP output signal. The second CP output signal is filtered with a second LPF and the filtered signal is converted to a digital signal with an A/D converter. The digital signal is applied to a bias circuit, which then produces first and second control voltages.

Abstract: A polyphase, noise-shaping, fractional-N frequency synthesizer utilizes multiple, parallel fractional-N divider channels to deliberately decorrelate noise and improve spectral purity. The synthesizer comprises a voltage controlled oscillator (VCO), a reference signal source to produce a plurality of different reference signals, a loop integrator, a plurality of desynchronized divider channels and a signal summer. Each divider channel comprises a frequency divider, a fractional-N control logic and a phase detector. Each divider channel divides an output signal from the VCO by a variable division factor and compares the divided signal to a different reference signal to produce an error signal. The signal summer combines the error signals from the desynchronized divider channels into a combined error signal. The loop integrator integrates the combined error signal to produce a control voltage that is applied to the VCO.

Abstract: Dual loop phase lock loops having a high loop bandwidth with low power consumption are described. Each loop is provided with a voltage supply regulator circuit which regulates the voltage of a portion of each loop. In one embodiment, the outer loop employs a regulation circuit comprising a two stage operational amplifier which is compensated by a compensation circuit that is configured to ensure that the dominant pole of the operational amplifier is associated with the first stage of the operational amplifier.

Abstract: Disclosed is a self-calibration device for calibrating a phase difference between output waveforms of a ring oscillator, comprising: a voltage-controlled oscillator adapted to adjust the transition time of an output signal according to an inputting of a control voltage for controlling the phase offset and generate the adjusted output signal; a divider adapted to divide a frequency of the output signal generated from the voltage-controlled oscillator by a fractional number to generate a plurality of output waveforms having different phases with them having an identical phase difference each other; a phase-locked loop (PLL) circuit adapted to correctly make a frequency and phase of the output signal of the divider coincident with those of a system clock, the phase-locked loop (PLL) circuit including at least a phase-frequency detecting means adapted to compare the frequency and phase of the output signal with those of the system clock and to output a result of the comparison; and a phase offset calibrating loop

Abstract: An adjustable bandwidth phase-locked loop including a phase-locked loop having a first input node receiving an input signal having a first frequency, a second input node receiving a feedback signal and an output node which has a signal indicative of an error signal characterizing a frequency error between the input signal and the feedback signal. The adjustable bandwidth phase-locked loop includes a voltage controlled oscillator, coupled to the second input node, receiving the error signal and generating the feedback signal where the feedback signal has a frequency which tracks the first frequency. The adjustable bandwidth phase-locked loop includes a variable loop filter, coupled between the phase-locked loop and the voltage controlled oscillator, filtering the error signal. The variable loop filter is configurable to allow for the tracking of the input signal over both of a broad bandwidth and a narrow bandwidth.

Abstract: A frequency synthesizer includes a charge pump, a fractional integration counter that alters the integrated current of the charge pump, a phase frequency detector, a proportional correction circuit, and a proportional multiplier that alters the value of the current correction output by the proportional correction circuit. The fractional integration counter alters the integrated current of the charge pump based upon a user-defined input, thereby permitting increased signal-to-noise ratio at the output of the charge pump. Similarly, the proportional multiplier alters the value of the proportional current correction based upon user-defined input, thereby modifying loop dynamics within the frequency synthesizer.

Abstract: For controlling frequency and phase of an output clock signal dependent on a reference signal, a digital phase locked loop comprises a ring oscillator connected to a switch-over unit for generating the output clock signal. The ring oscillator has a plurality of serially arranged delay units. A phase comparator for comparing the phase of the reference signal and of the output clock signal. At least one switchable frequency divider unit is provided between the phase comparator and the output clock signal. A control unit controls the ring oscillator frequency by cut-in or cut-outs of delay units with the assistance of the switchover unit.

Abstract: A frequency oscillator tuning process at the manufacturing stage is replaced with an adjustment of a resonant circuit in the frequency oscillator during an operation of the oscillator. The adjustment utilizes a crystal oscillator, a frequency oscillator such as a voltage-controlled oscillator (VCO), and a trimmer in a phase-locked loop configuration to determine a correction voltage required for an untrimmed VCO to operate at a nominally specified frequency by adjusting an input tuning voltage for a resonant circuit.

Abstract: Voltage controlled oscillator circuits are provided including a voltage controlled oscillator (VCO) having an input and an output responsive to the input. A tuning circuit coupled to the VCO sets a relationship between the input and the output of the VCO. An aided acquisition circuit is coupled to the input of the VCO. A control circuit selects a state of the tuning circuit to set the relationship between the input and the output of the VCO. The control circuit also controls operation of the aided acquisition circuit responsive to changes in the state of the tuning circuit. Methods for operating voltage controlled oscillator circuits are also provided. In addition, phase lock loop circuits and mobile terminals including the voltage controlled oscillator circuits are provided.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal having a frequency that varies in response to (i) a voltage signal and (ii) a load. The second circuit may be configured to generate the load by coupling one or more resistive devices to a reference node in response to a control signal.